Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

plat/arm/board/fvp/fvp_def.h

@@ -4,8 +4,10 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __FVP_DEF_H__
-#define __FVP_DEF_H__
+#ifndef FVP_DEF_H
+#define FVP_DEF_H
+
+#include <utils_def.h>
 
 #ifndef FVP_CLUSTER_COUNT
 #define FVP_CLUSTER_COUNT		2
@@ -153,4 +155,4 @@
 #define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
 					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
-#endif /* __FVP_DEF_H__ */
+#endif /* FVP_DEF_H */

plat/arm/board/juno/juno_def.h

 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __JUNO_DEF_H__
-#define __JUNO_DEF_H__
+#ifndef JUNO_DEF_H
+#define JUNO_DEF_H
 
+#include <utils_def.h>
 
 /*******************************************************************************
  * Juno memory map related constants
@@ -90,4 +91,4 @@
 #define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
 					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
-#endif /* __JUNO_DEF_H__ */
+#endif /* JUNO_DEF_H */

plat/arm/common/arm_nor_psci_mem_protect.c

@@ -51,14 +51,14 @@ int arm_psci_read_mem_protect(int *enabled)
  ******************************************************************************/
 int arm_nor_psci_write_mem_protect(int val)
 {
-	int enable = (val != 0);
+	int enable = (val != 0) ? 1 : 0;
 
 	if (nor_unlock(PLAT_ARM_MEM_PROT_ADDR) != 0) {
 		ERROR("unlocking memory protect variable\n");
 		return -1;
 	}
 
-	if (enable != 0) {
+	if (enable == 1) {
 		/*
 		 * If we want to write a value different than 0
 		 * then we have to erase the full block because
@@ -117,14 +117,14 @@ void arm_nor_psci_do_static_mem_protect(void)
 {
 	int enable;
 
-	arm_psci_read_mem_protect(&enable);
+	(void) arm_psci_read_mem_protect(&enable);
 	if (enable == 0)
 		return;
 
 	INFO("PSCI: Overwriting non secure memory\n");
 	clear_mem_regions(arm_ram_ranges,
 			  ARRAY_SIZE(arm_ram_ranges));
-	arm_nor_psci_write_mem_protect(0);
+	(void) arm_nor_psci_write_mem_protect(0);
 }
 
 /*******************************************************************************

plat/arm/common/arm_pm.c

@@ -26,11 +26,11 @@
 int arm_validate_power_state(unsigned int power_state,
 			    psci_power_state_t *req_state)
 {
-	int pstate = psci_get_pstate_type(power_state);
-	int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
-	int i;
+	unsigned int pstate = psci_get_pstate_type(power_state);
+	unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+	unsigned int i;
 
-	assert(req_state);
+	assert(req_state > 0U);
 
 	if (pwr_lvl > PLAT_MAX_PWR_LVL)
 		return PSCI_E_INVALID_PARAMS;
@@ -55,7 +55,7 @@ int arm_validate_power_state(unsigned int power_state,
 	/*
 	 * We expect the 'state id' to be zero.
 	 */
-	if (psci_get_pstate_id(power_state))
+	if (psci_get_pstate_id(power_state) != 0U)
 		return PSCI_E_INVALID_PARAMS;
 
 	return PSCI_E_SUCCESS;

plat/arm/css/sgi/include/platform_def.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arm_def.h>
 #include <board_arm_def.h>
@@ -13,6 +13,7 @@
 #include <common_def.h>
 #include <css_def.h>
 #include <soc_css_def.h>
+#include <utils_def.h>
 
 #define CSS_SGI_MAX_CPUS_PER_CLUSTER	4
 
@@ -57,7 +58,7 @@
 #define PLAT_ARM_NSRAM_BASE		0x06000000
 #define PLAT_ARM_NSRAM_SIZE		0x00080000	/* 512KB */
 
-#define PLAT_MAX_PWR_LVL		1
+#define PLAT_MAX_PWR_LVL		U(1)
 
 #define PLAT_ARM_G1S_IRQS		ARM_G1S_IRQS,			\
 					CSS_IRQ_MHU
@@ -108,4 +109,4 @@
 					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/common/plat_psci_common.c

 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 #pragma weak plat_psci_stat_get_residency
 
 /* Ticks elapsed in one second by a signal of 1 MHz */
-#define MHZ_TICKS_PER_SEC 1000000
+#define MHZ_TICKS_PER_SEC 1000000U
 
 /* Maximum time-stamp value read from architectural counters */
 #ifdef AARCH32
@@ -49,7 +49,7 @@ static u_register_t calc_stat_residency(unsigned long long pwrupts,
 	 * convert time-stamp into microseconds.
 	 */
 	residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC;
-	assert(residency_div);
+	assert(residency_div > 0U);
 
 	if (pwrupts < pwrdnts)
 		res = MAX_TS - pwrdnts + pwrupts;
@@ -67,7 +67,7 @@ static u_register_t calc_stat_residency(unsigned long long pwrupts,
 void plat_psci_stat_accounting_start(
 	__unused const psci_power_state_t *state_info)
 {
-	assert(state_info);
+	assert(state_info != NULL);
 	PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
 		PMF_NO_CACHE_MAINT);
 }
@@ -80,7 +80,7 @@ void plat_psci_stat_accounting_start(
 void plat_psci_stat_accounting_stop(
 	__unused const psci_power_state_t *state_info)
 {
-	assert(state_info);
+	assert(state_info != NULL);
 	PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
 		PMF_NO_CACHE_MAINT);
 }
@@ -97,12 +97,12 @@ u_register_t plat_psci_stat_get_residency(unsigned int lvl,
 	unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
 	unsigned int pmf_flags;
 
-	assert(lvl >= PSCI_CPU_PWR_LVL && lvl <= PLAT_MAX_PWR_LVL);
-	assert(state_info);
-	assert(last_cpu_idx >= 0 && last_cpu_idx <= PLATFORM_CORE_COUNT);
+	assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL));
+	assert(state_info != NULL);
+	assert(last_cpu_idx <= PLATFORM_CORE_COUNT);
 
 	if (lvl == PSCI_CPU_PWR_LVL)
-		assert(last_cpu_idx == plat_my_core_pos());
+		assert((unsigned int)last_cpu_idx == plat_my_core_pos());
 
 	/*
 	 * If power down is requested, then timestamp capture will
@@ -110,10 +110,10 @@ u_register_t plat_psci_stat_get_residency(unsigned int lvl,
 	 * when reading the timestamp.
 	 */
 	state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
-	if (is_local_state_off(state)) {
+	if (is_local_state_off(state) != 0) {
 		pmf_flags = PMF_CACHE_MAINT;
 	} else {
-		assert(is_local_state_retn(state));
+		assert(is_local_state_retn(state) == 1);
 		pmf_flags = PMF_NO_CACHE_MAINT;
 	}
 
@@ -150,14 +150,18 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
 					     unsigned int ncpu)
 {
 	plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
+	const plat_local_state_t *st = states;
+	unsigned int n = ncpu;
 
-	assert(ncpu);
+	assert(ncpu > 0U);
 
 	do {
-		temp = *states++;
+		temp = *st;
+		st++;
 		if (temp < target)
 			target = temp;
-	} while (--ncpu);
+		n--;
+	} while (n > 0U);
 
 	return target;
 }

plat/hisilicon/hikey/include/platform_def.h

@@ -4,14 +4,15 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
 #include <hikey_def.h>
 #include <hikey_layout.h>		/* BL memory region sizes, etc */
 #include <tbbr_img_def.h>
+#include <utils_def.h>
 
 /* Special value used to verify platform parameters from BL2 to BL3-1 */
 #define HIKEY_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
@@ -34,8 +35,8 @@
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
 					 PLATFORM_CLUSTER_COUNT + 1)
 
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 
 #define MAX_IO_DEVICES			3
 #define MAX_IO_HANDLES			4
@@ -79,4 +80,4 @@
 #define CACHE_WRITEBACK_SHIFT		6
 #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/hisilicon/hikey960/include/platform_def.h

@@ -4,10 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
+#include <utils_def.h>
 #include "../hikey960_def.h"
 
 /* Special value used to verify platform parameters from BL2 to BL3-1 */
@@ -31,8 +32,8 @@
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
 					 PLATFORM_CLUSTER_COUNT + 1)
 
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 
 #define MAX_IO_DEVICES			3
 #define MAX_IO_HANDLES			4
@@ -140,4 +141,4 @@
 #define CACHE_WRITEBACK_SHIFT		6
 #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/hisilicon/poplar/include/platform_def.h

 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
@@ -131,8 +131,8 @@
 
 /* Power states */
 #define PLAT_MAX_PWR_LVL		(MPIDR_AFFLVL1)
-#define PLAT_MAX_OFF_STATE		2
-#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_OFF_STATE		U(2)
+#define PLAT_MAX_RET_STATE		U(1)
 
 /* Interrupt controller */
 #define PLAT_ARM_GICD_BASE	GICD_BASE
@@ -168,4 +168,4 @@
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/imx/imx8qm/include/platform_def.h

@@ -4,6 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <utils_def.h>
+
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
 
@@ -22,10 +27,10 @@
 #define IMX_PWR_LVL1			MPIDR_AFFLVL1
 #define IMX_PWR_LVL2			MPIDR_AFFLVL2
 
-#define PWR_DOMAIN_AT_MAX_LVL		1
-#define PLAT_MAX_PWR_LVL		2
-#define PLAT_MAX_OFF_STATE		2
-#define PLAT_MAX_RET_STATE		1
+#define PWR_DOMAIN_AT_MAX_LVL		U(1)
+#define PLAT_MAX_PWR_LVL		U(2)
+#define PLAT_MAX_OFF_STATE		U(2)
+#define PLAT_MAX_RET_STATE		U(1)
 
 #define BL31_BASE			0x80000000
 #define BL31_LIMIT			0x80020000
@@ -62,3 +67,5 @@
 #define DEBUG_CONSOLE			0
 #define DEBUG_CONSOLE_A53		0
 #define PLAT_IMX8QM			1
+
+#endif /* PLATFORM_DEF_H */

plat/imx/imx8qx/include/platform_def.h

@@ -4,8 +4,10 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <utils_def.h>
 
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
@@ -20,10 +22,10 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	4
 #define PLATFORM_CLUSTER1_CORE_COUNT	0
 
-#define PWR_DOMAIN_AT_MAX_LVL           1
-#define PLAT_MAX_PWR_LVL                2
-#define PLAT_MAX_OFF_STATE              2
-#define PLAT_MAX_RET_STATE              1
+#define PWR_DOMAIN_AT_MAX_LVL           U(1)
+#define PLAT_MAX_PWR_LVL                U(2)
+#define PLAT_MAX_OFF_STATE              U(2)
+#define PLAT_MAX_RET_STATE              U(1)
 
 #define BL31_BASE			0x80000000
 #define BL31_LIMIT			0x80020000
@@ -57,4 +59,4 @@
 #define DEBUG_CONSOLE_A35		0
 #define PLAT_IMX8QX			1
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/layerscape/board/ls1043/include/ls_def.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __LS_DEF_H__
-#define __LS_DEF_H__
+#ifndef LS_DEF_H
+#define LS_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
@@ -36,14 +36,14 @@
  *  within the power-state parameter.
  */
 /* Local power state for power domains in Run state. */
-#define LS_LOCAL_STATE_RUN	0
+#define LS_LOCAL_STATE_RUN	U(0)
 /* Local power state for retention. Valid only for CPU power domains */
-#define LS_LOCAL_STATE_RET	1
+#define LS_LOCAL_STATE_RET	U(1)
 /*
  * Local power state for OFF/power-down. Valid for CPU and cluster power
  * domains
  */
-#define LS_LOCAL_STATE_OFF	2
+#define LS_LOCAL_STATE_OFF	U(2)
 
 #define LS_MAP_NS_DRAM		MAP_REGION_FLAT( \
 					(LS_NS_DRAM_BASE), \
@@ -104,4 +104,4 @@
  */
 #define PLAT_PERCPU_BAKERY_LOCK_SIZE		(1 * CACHE_WRITEBACK_GRANULE)
 
-#endif /* __LS_DEF_H__ */
+#endif /* LS_DEF_H */

plat/layerscape/board/ls1043/include/platform_def.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <common_def.h>
 #include <tzc400.h>
@@ -209,4 +209,4 @@
 #define MAX_IO_DEVICES			3
 #define MAX_IO_HANDLES			4
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/mediatek/mt6795/include/platform_def.h

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <utils_def.h>
 
 #define PLAT_PRIMARY_CPU  0x0
 
@@ -146,7 +148,7 @@
 #if ENABLE_PLAT_COMPAT
 #define PLATFORM_MAX_AFFLVL     MPIDR_AFFLVL2
 #else
-#define PLAT_MAX_PWR_LVL        2 /* MPIDR_AFFLVL2 */
+#define PLAT_MAX_PWR_LVL        U(2) /* MPIDR_AFFLVL2 */
 #endif
 
 #define PLATFORM_CACHE_LINE_SIZE      64
@@ -239,4 +241,4 @@
 #define PAGE_SIZE_2MB               (1 << PAGE_SIZE_2MB_SHIFT)
 #define PAGE_SIZE_2MB_SHIFT         TWO_MB_SHIFT
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/mediatek/mt8173/include/platform_def.h

 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <gic_common.h>
 #include <interrupt_props.h>
+#include <utils_def.h>
 #include "mt8173_def.h"
 
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
@@ -37,9 +37,9 @@
 
 #define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
 #if !ENABLE_PLAT_COMPAT
-#define PLAT_MAX_PWR_LVL		2
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_PWR_LVL		U(2)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 #endif
 #define PLATFORM_SYSTEM_COUNT		1
 #define PLATFORM_CLUSTER_COUNT		2
@@ -137,4 +137,4 @@
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/qemu/include/platform_def.h

 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
 #include <tbbr_img_def.h>
+#include <utils_def.h>
 
 /* Special value used to verify platform parameters from BL2 to BL3-1 */
 #define QEMU_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
@@ -36,13 +37,13 @@
 					PLATFORM_CORE_COUNT)
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 
 /* Local power state for power domains in Run state. */
-#define PLAT_LOCAL_STATE_RUN		0
+#define PLAT_LOCAL_STATE_RUN		U(0)
 /* Local power state for retention. Valid only for CPU power domains */
-#define PLAT_LOCAL_STATE_RET		1
+#define PLAT_LOCAL_STATE_RET		U(1)
 /*
  * Local power state for OFF/power-down. Valid for CPU and cluster power
  * domains.
@@ -229,4 +230,4 @@
  */
 #define SYS_COUNTER_FREQ_IN_TICKS	((1000 * 1000 * 1000) / 16)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/rockchip/rk3328/include/platform_def.h

 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
@@ -58,13 +58,13 @@
  * This macro defines the deepest retention state possible. A higher state
  * id will represent an invalid or a power down state.
  */
-#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_RET_STATE		U(1)
 
 /*
  * This macro defines the deepest power down states possible. Any state ID
  * higher than this is invalid.
  */
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_OFF_STATE		U(2)
 
 /*******************************************************************************
  * Platform memory map related constants
@@ -123,4 +123,4 @@
 #define PSRAM_DO_DDR_RESUME	0
 #define PSRAM_CHECK_WAKEUP_CPU	0
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/rockchip/rk3368/include/platform_def.h

 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <common_def.h>
 #include <rk3368_def.h>
+#include <utils_def.h>
 
 #define DEBUG_XLAT_TABLE 0
 
@@ -58,13 +59,13 @@
  * This macro defines the deepest retention state possible. A higher state
  * id will represent an invalid or a power down state.
  */
-#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_RET_STATE		U(1)
 
 /*
  * This macro defines the deepest power down states possible. Any state ID
  * higher than this is invalid.
  */
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_OFF_STATE		U(2)
 
 /*******************************************************************************
  * Platform memory map related constants
@@ -125,4 +126,4 @@
 #define PSRAM_DO_DDR_RESUME	0
 #define PSRAM_CHECK_WAKEUP_CPU	0
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/rockchip/rk3399/include/platform_def.h

 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <arch.h>
 #include <bl31_param.h>
 #include <common_def.h>
 #include <rk3399_def.h>
+#include <utils_def.h>
 
 #define DEBUG_XLAT_TABLE 0
 
@@ -57,13 +58,13 @@
  * This macro defines the deepest retention state possible. A higher state
  * id will represent an invalid or a power down state.
  */
-#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_RET_STATE		U(1)
 
 /*
  * This macro defines the deepest power down states possible. Any state ID
  * higher than this is invalid.
  */
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_OFF_STATE		U(2)
 
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
@@ -110,4 +111,4 @@
 #define PSRAM_DO_DDR_RESUME	1
 #define PSRAM_CHECK_WAKEUP_CPU	0
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/socionext/synquacer/include/platform_def.h

@@ -4,10 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 #include <common_def.h>
+#include <utils_def.h>
 
 /* CPU topology */
 #define PLAT_MAX_CORES_PER_CLUSTER	2
@@ -15,9 +16,9 @@
 #define PLATFORM_CORE_COUNT		(PLAT_CLUSTER_COUNT *	\
 					 PLAT_MAX_CORES_PER_CLUSTER)
 
-#define PLAT_MAX_PWR_LVL		1
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_PWR_LVL		U(1)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 
 #define SQ_LOCAL_STATE_RUN		0
 #define SQ_LOCAL_STATE_RET		1
@@ -78,4 +79,4 @@
 
 #define PLAT_SQ_GPIO_BASE		0x51000000
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */