Merge pull request #1539 from antonio-nino-diaz-arm/an/gic-misra

MISRA fixes for the GIC driver

drivers/arm/gic/common/gic_common.c

@@ -18,7 +18,8 @@
  */
 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> IGROUPR_SHIFT;
+	unsigned int n = id >> IGROUPR_SHIFT;
+
 	return mmio_read_32(base + GICD_IGROUPR + (n << 2));
 }
 
@@ -28,7 +29,8 @@ unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ISENABLER_SHIFT;
+	unsigned int n = id >> ISENABLER_SHIFT;
+
 	return mmio_read_32(base + GICD_ISENABLER + (n << 2));
 }
 
@@ -38,7 +40,8 @@ unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ICENABLER_SHIFT;
+	unsigned int n = id >> ICENABLER_SHIFT;
+
 	return mmio_read_32(base + GICD_ICENABLER + (n << 2));
 }
 
@@ -48,7 +51,8 @@ unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ISPENDR_SHIFT;
+	unsigned int n = id >> ISPENDR_SHIFT;
+
 	return mmio_read_32(base + GICD_ISPENDR + (n << 2));
 }
 
@@ -58,7 +62,8 @@ unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ICPENDR_SHIFT;
+	unsigned int n = id >> ICPENDR_SHIFT;
+
 	return mmio_read_32(base + GICD_ICPENDR + (n << 2));
 }
 
@@ -68,7 +73,8 @@ unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ISACTIVER_SHIFT;
+	unsigned int n = id >> ISACTIVER_SHIFT;
+
 	return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
 }
 
@@ -78,7 +84,8 @@ unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ICACTIVER_SHIFT;
+	unsigned int n = id >> ICACTIVER_SHIFT;
+
 	return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
 }
 
@@ -88,7 +95,8 @@ unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned int n = id >> IPRIORITYR_SHIFT;
+
 	return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
 }
 
@@ -98,7 +106,8 @@ unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> ICFGR_SHIFT;
+	unsigned int n = id >> ICFGR_SHIFT;
+
 	return mmio_read_32(base + GICD_ICFGR + (n << 2));
 }
 
@@ -108,7 +117,8 @@ unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
  */
 unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> NSACR_SHIFT;
+	unsigned int n = id >> NSACR_SHIFT;
+
 	return mmio_read_32(base + GICD_NSACR + (n << 2));
 }
 
@@ -121,7 +131,8 @@ unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
  */
 void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> IGROUPR_SHIFT;
+	unsigned int n = id >> IGROUPR_SHIFT;
+
 	mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
 }
 
@@ -131,7 +142,8 @@ void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ISENABLER_SHIFT;
+	unsigned int n = id >> ISENABLER_SHIFT;
+
 	mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
 }
 
@@ -141,7 +153,8 @@ void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ICENABLER_SHIFT;
+	unsigned int n = id >> ICENABLER_SHIFT;
+
 	mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
 }
 
@@ -151,7 +164,8 @@ void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ISPENDR_SHIFT;
+	unsigned int n = id >> ISPENDR_SHIFT;
+
 	mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
 }
 
@@ -161,7 +175,8 @@ void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ICPENDR_SHIFT;
+	unsigned int n = id >> ICPENDR_SHIFT;
+
 	mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
 }
 
@@ -171,7 +186,8 @@ void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ISACTIVER_SHIFT;
+	unsigned int n = id >> ISACTIVER_SHIFT;
+
 	mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
 }
 
@@ -181,7 +197,8 @@ void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ICACTIVER_SHIFT;
+	unsigned int n = id >> ICACTIVER_SHIFT;
+
 	mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
 }
 
@@ -191,7 +208,8 @@ void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned int n = id >> IPRIORITYR_SHIFT;
+
 	mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
 }
 
@@ -201,7 +219,8 @@ void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> ICFGR_SHIFT;
+	unsigned int n = id >> ICFGR_SHIFT;
+
 	mmio_write_32(base + GICD_ICFGR + (n << 2), val);
 }
 
@@ -211,7 +230,8 @@ void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
  */
 void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> NSACR_SHIFT;
+	unsigned int n = id >> NSACR_SHIFT;
+
 	mmio_write_32(base + GICD_NSACR + (n << 2), val);
 }
 
@@ -223,87 +243,89 @@ void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
  ******************************************************************************/
 unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 void gicd_set_igroupr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
+	gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
 }
 
 void gicd_clr_igroupr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
+	gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
 }
 
 void gicd_set_isenabler(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
 
-	gicd_write_isenabler(base, id, (1 << bit_num));
+	gicd_write_isenabler(base, id, (1U << bit_num));
 }
 
 void gicd_set_icenabler(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
 
-	gicd_write_icenabler(base, id, (1 << bit_num));
+	gicd_write_icenabler(base, id, (1U << bit_num));
 }
 
 void gicd_set_ispendr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
 
-	gicd_write_ispendr(base, id, (1 << bit_num));
+	gicd_write_ispendr(base, id, (1U << bit_num));
 }
 
 void gicd_set_icpendr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
 
-	gicd_write_icpendr(base, id, (1 << bit_num));
+	gicd_write_icpendr(base, id, (1U << bit_num));
 }
 
 unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
 {
-	unsigned int bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_isactiver(base, id);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 void gicd_set_isactiver(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
 
-	gicd_write_isactiver(base, id, (1 << bit_num));
+	gicd_write_isactiver(base, id, (1U << bit_num));
 }
 
 void gicd_set_icactiver(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
 
-	gicd_write_icactiver(base, id, (1 << bit_num));
+	gicd_write_icactiver(base, id, (1U << bit_num));
 }
 
 void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
 {
-	mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK);
+	uint8_t val = pri & GIC_PRI_MASK;
+
+	mmio_write_8(base + GICD_IPRIORITYR + id, val);
 }
 
 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
 {
 	/* Interrupt configuration is a 2-bit field */
-	unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
 	unsigned int bit_shift = bit_num << 1;
 
 	uint32_t reg_val = gicd_read_icfgr(base, id);

drivers/arm/gic/v2/gicv2_helpers.c

@@ -94,24 +94,24 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base)
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
 	/*
 	 * Treat all SPIs as G1NS by default. The number of interrupts is
 	 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
 	 */
-	for (index = MIN_SPI_ID; index < num_ints; index += 32)
+	for (index = MIN_SPI_ID; index < num_ints; index += 32U)
 		gicd_write_igroupr(gicd_base, index, ~0U);
 
 	/* Setup the default SPI priorities doing four at a time */
-	for (index = MIN_SPI_ID; index < num_ints; index += 4)
+	for (index = MIN_SPI_ID; index < num_ints; index += 4U)
 		gicd_write_ipriorityr(gicd_base,
 				      index,
 				      GICD_IPRIORITYR_DEF_VAL);
 
 	/* Treat all SPIs as level triggered by default, 16 at a time */
-	for (index = MIN_SPI_ID; index < num_ints; index += 16)
-		gicd_write_icfgr(gicd_base, index, 0);
+	for (index = MIN_SPI_ID; index < num_ints; index += 16U)
+		gicd_write_icfgr(gicd_base, index, 0U);
 }
 
 #if !ERROR_DEPRECATED
@@ -125,7 +125,8 @@ void gicv2_secure_spis_configure(uintptr_t gicd_base,
 	unsigned int index, irq_num;
 
 	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+	if (num_ints != 0U)
+		assert(sec_intr_list != NULL);
 
 	for (index = 0; index < num_ints; index++) {
 		irq_num = sec_intr_list[index];
@@ -161,7 +162,8 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
 	const interrupt_prop_t *prop_desc;
 
 	/* Make sure there's a valid property array */
-	assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
+	if (interrupt_props_num != 0U)
+		assert(interrupt_props != NULL);
 
 	for (i = 0; i < interrupt_props_num; i++) {
 		prop_desc = &interrupt_props[i];
@@ -252,20 +254,21 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
 	const interrupt_prop_t *prop_desc;
 
 	/* Make sure there's a valid property array */
-	assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
+	if (interrupt_props_num != 0U)
+		assert(interrupt_props != NULL);
 
 	/*
 	 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
 	 * more scalable approach as it avoids clearing the enable bits in the
 	 * GICD_CTLR.
 	 */
-	gicd_write_icenabler(gicd_base, 0, ~0);
+	gicd_write_icenabler(gicd_base, 0U, ~0U);
 
 	/* Setup the default PPI/SGI priorities doing four at a time */
-	for (i = 0; i < MIN_SPI_ID; i += 4)
+	for (i = 0U; i < MIN_SPI_ID; i += 4U)
 		gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
 
-	for (i = 0; i < interrupt_props_num; i++) {
+	for (i = 0U; i < interrupt_props_num; i++) {
 		prop_desc = &interrupt_props[i];
 
 		if (prop_desc->intr_num >= MIN_SPI_ID)

drivers/arm/gic/v2/gicv2_main.c

@@ -12,6 +12,8 @@
 #include <gicv2.h>
 #include <interrupt_props.h>
 #include <spinlock.h>
+#include <stdbool.h>
+
 #include "../common/gic_common_private.h"
 #include "gicv2_private.h"
 
@@ -32,8 +34,8 @@ void gicv2_cpuif_enable(void)
 {
 	unsigned int val;
 
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	/*
 	 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1
@@ -55,8 +57,8 @@ void gicv2_cpuif_disable(void)
 {
 	unsigned int val;
 
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	/* Disable secure, non-secure interrupts and disable their bypass */
 	val = gicc_read_ctlr(driver_data->gicc_base);
@@ -74,8 +76,8 @@ void gicv2_pcpu_distif_init(void)
 {
 	unsigned int ctlr;
 
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
 #if !ERROR_DEPRECATED
 	if (driver_data->interrupt_props != NULL) {
@@ -101,7 +103,7 @@ void gicv2_pcpu_distif_init(void)
 
 	/* Enable G0 interrupts if not already */
 	ctlr = gicd_read_ctlr(driver_data->gicd_base);
-	if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) {
+	if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) {
 		gicd_write_ctlr(driver_data->gicd_base,
 				ctlr | CTLR_ENABLE_G0_BIT);
 	}
@@ -116,8 +118,8 @@ void gicv2_distif_init(void)
 {
 	unsigned int ctlr;
 
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
 	/* Disable the distributor before going further */
 	ctlr = gicd_read_ctlr(driver_data->gicd_base);
@@ -162,9 +164,10 @@ void gicv2_distif_init(void)
 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
 {
 	unsigned int gic_version;
-	assert(plat_driver_data);
-	assert(plat_driver_data->gicd_base);
-	assert(plat_driver_data->gicc_base);
+
+	assert(plat_driver_data != NULL);
+	assert(plat_driver_data->gicd_base != 0U);
+	assert(plat_driver_data->gicc_base != 0U);
 
 #if !ERROR_DEPRECATED
 	if (plat_driver_data->interrupt_props == NULL) {
@@ -212,7 +215,8 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
 	 * - interrupt priority drop.
 	 * - interrupt signal bypass.
 	 */
-	assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
+	assert((gic_version == ARCH_REV_GICV2) ||
+	       (gic_version == ARCH_REV_GICV1));
 
 	driver_data = plat_driver_data;
 
@@ -238,11 +242,11 @@ unsigned int gicv2_is_fiq_enabled(void)
 {
 	unsigned int gicc_ctlr;
 
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
-	return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1;
+	return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U;
 }
 
 /*******************************************************************************
@@ -255,8 +259,8 @@ unsigned int gicv2_is_fiq_enabled(void)
  ******************************************************************************/
 unsigned int gicv2_get_pending_interrupt_type(void)
 {
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
 }
@@ -270,8 +274,8 @@ unsigned int gicv2_get_pending_interrupt_id(void)
 {
 	unsigned int id;
 
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
 
@@ -292,8 +296,8 @@ unsigned int gicv2_get_pending_interrupt_id(void)
  ******************************************************************************/
 unsigned int gicv2_acknowledge_interrupt(void)
 {
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	return gicc_read_IAR(driver_data->gicc_base);
 }
@@ -304,8 +308,8 @@ unsigned int gicv2_acknowledge_interrupt(void)
  ******************************************************************************/
 void gicv2_end_of_interrupt(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	gicc_write_EOIR(driver_data->gicc_base, id);
 }
@@ -318,8 +322,8 @@ void gicv2_end_of_interrupt(unsigned int id)
  ******************************************************************************/
 unsigned int gicv2_get_interrupt_group(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
 	return gicd_get_igroupr(driver_data->gicd_base, id);
 }
@@ -330,8 +334,8 @@ unsigned int gicv2_get_interrupt_group(unsigned int id)
  ******************************************************************************/
 unsigned int gicv2_get_running_priority(void)
 {
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	return gicc_read_rpr(driver_data->gicc_base);
 }
@@ -344,21 +348,21 @@ unsigned int gicv2_get_running_priority(void)
  ******************************************************************************/
 void gicv2_set_pe_target_mask(unsigned int proc_num)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
-	assert(driver_data->target_masks);
-	assert(proc_num < GICV2_MAX_TARGET_PE);
-	assert(proc_num < driver_data->target_masks_num);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
+	assert(driver_data->target_masks != NULL);
+	assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+	assert((unsigned int)proc_num < driver_data->target_masks_num);
 
 	/* Return if the target mask is already populated */
-	if (driver_data->target_masks[proc_num])
+	if (driver_data->target_masks[proc_num] != 0U)
 		return;
 
 	/*
 	 * Update target register corresponding to this CPU and flush for it to
 	 * be visible to other CPUs.
 	 */
-	if (driver_data->target_masks[proc_num] == 0) {
+	if (driver_data->target_masks[proc_num] == 0U) {
 		driver_data->target_masks[proc_num] =
 			gicv2_get_cpuif_id(driver_data->gicd_base);
 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
@@ -382,8 +386,8 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
  ******************************************************************************/
 unsigned int gicv2_get_interrupt_active(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 	assert(id <= MAX_SPI_ID);
 
 	return gicd_get_isactiver(driver_data->gicd_base, id);
@@ -394,8 +398,8 @@ unsigned int gicv2_get_interrupt_active(unsigned int id)
  ******************************************************************************/
 void gicv2_enable_interrupt(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -411,8 +415,8 @@ void gicv2_enable_interrupt(unsigned int id)
  ******************************************************************************/
 void gicv2_disable_interrupt(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -429,8 +433,8 @@ void gicv2_disable_interrupt(unsigned int id)
  ******************************************************************************/
 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 	assert(id <= MAX_SPI_ID);
 
 	gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
@@ -442,8 +446,8 @@ void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
  ******************************************************************************/
 void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 	assert(id <= MAX_SPI_ID);
 
 	/* Serialize read-modify-write to Distributor registers */
@@ -456,7 +460,7 @@ void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
 		gicd_clr_igroupr(driver_data->gicd_base, id);
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 	spin_unlock(&gic_lock);
@@ -472,20 +476,20 @@ void gicv2_raise_sgi(int sgi_num, int proc_num)
 {
 	unsigned int sgir_val, target;
 
-	assert(driver_data);
-	assert(proc_num < GICV2_MAX_TARGET_PE);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+	assert(driver_data->gicd_base != 0U);
 
 	/*
 	 * Target masks array must have been supplied, and the core position
 	 * should be valid.
 	 */
-	assert(driver_data->target_masks);
-	assert(proc_num < driver_data->target_masks_num);
+	assert(driver_data->target_masks != NULL);
+	assert((unsigned int)proc_num < driver_data->target_masks_num);
 
 	/* Don't raise SGI if the mask hasn't been populated */
 	target = driver_data->target_masks[proc_num];
-	assert(target != 0);
+	assert(target != 0U);
 
 	sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
 
@@ -505,20 +509,20 @@ void gicv2_raise_sgi(int sgi_num, int proc_num)
  ******************************************************************************/
 void gicv2_set_spi_routing(unsigned int id, int proc_num)
 {
-	int target;
+	unsigned int target;
 
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
-	assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
+	assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
 
 	/*
 	 * Target masks array must have been supplied, and the core position
 	 * should be valid.
 	 */
-	assert(driver_data->target_masks);
-	assert(proc_num < GICV2_MAX_TARGET_PE);
-	assert(proc_num < driver_data->target_masks_num);
+	assert(driver_data->target_masks != NULL);
+	assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+	assert((unsigned int)proc_num < driver_data->target_masks_num);
 
 	if (proc_num < 0) {
 		/* Target all PEs */
@@ -526,7 +530,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num)
 	} else {
 		/* Don't route interrupt if the mask hasn't been populated */
 		target = driver_data->target_masks[proc_num];
-		assert(target != 0);
+		assert(target != 0U);
 	}
 
 	gicd_set_itargetsr(driver_data->gicd_base, id, target);
@@ -537,8 +541,8 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num)
  ******************************************************************************/
 void gicv2_clear_interrupt_pending(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
 	/* SGIs can't be cleared pending */
 	assert(id >= MIN_PPI_ID);
@@ -556,8 +560,8 @@ void gicv2_clear_interrupt_pending(unsigned int id)
  ******************************************************************************/
 void gicv2_set_interrupt_pending(unsigned int id)
 {
-	assert(driver_data);
-	assert(driver_data->gicd_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicd_base != 0U);
 
 	/* SGIs can't be cleared pending */
 	assert(id >= MIN_PPI_ID);
@@ -578,8 +582,8 @@ unsigned int gicv2_set_pmr(unsigned int mask)
 {
 	unsigned int old_mask;
 
-	assert(driver_data);
-	assert(driver_data->gicc_base);
+	assert(driver_data != NULL);
+	assert(driver_data->gicc_base != 0U);
 
 	old_mask = gicc_read_pmr(driver_data->gicc_base);
 

drivers/arm/gic/v2/gicv2_private.h

@@ -50,7 +50,9 @@ static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id)
 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
 		unsigned int target)
 {
-	mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
+	uint8_t val = target & GIC_TARGET_CPU_MASK;
+
+	mmio_write_8(base + GICD_ITARGETSR + id, val);
 }
 
 static inline void gicd_write_sgir(uintptr_t base, unsigned int val)

drivers/arm/gic/v3/gicv3_helpers.c

@@ -19,7 +19,8 @@
  */
 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> IGRPMODR_SHIFT;
+	unsigned int n = id >> IGRPMODR_SHIFT;
+
 	return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
 }
 
@@ -29,7 +30,8 @@ unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
  */
 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> IGRPMODR_SHIFT;
+	unsigned int n = id >> IGRPMODR_SHIFT;
+
 	mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
 }
 
@@ -39,10 +41,10 @@ void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
  */
 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igrpmodr(base, id);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 /*
@@ -51,10 +53,10 @@ unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
  */
 void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igrpmodr(base, id);
 
-	gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num));
+	gicd_write_igrpmodr(base, id, reg_val | (1U << bit_num));
 }
 
 /*
@@ -63,10 +65,10 @@ void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
  */
 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igrpmodr(base, id);
 
-	gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num));
+	gicd_write_igrpmodr(base, id, reg_val & ~(1U << bit_num));
 }
 
 /*
@@ -75,7 +77,8 @@ void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
  */
 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned int n = id >> IPRIORITYR_SHIFT;
+
 	return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
 }
 
@@ -85,7 +88,8 @@ unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
  */
 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned int n = id >> IPRIORITYR_SHIFT;
+
 	mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
 }
 
@@ -95,10 +99,10 @@ void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
  */
 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igroupr0(base);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 /*
@@ -107,10 +111,10 @@ unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
  */
 void gicr_set_igroupr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igroupr0(base);
 
-	gicr_write_igroupr0(base, reg_val | (1 << bit_num));
+	gicr_write_igroupr0(base, reg_val | (1U << bit_num));
 }
 
 /*
@@ -119,10 +123,10 @@ void gicr_set_igroupr0(uintptr_t base, unsigned int id)
  */
 void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igroupr0(base);
 
-	gicr_write_igroupr0(base, reg_val & ~(1 << bit_num));
+	gicr_write_igroupr0(base, reg_val & ~(1U << bit_num));
 }
 
 /*
@@ -131,10 +135,10 @@ void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
  */
 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igrpmodr0(base);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 /*
@@ -143,10 +147,10 @@ unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
  */
 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igrpmodr0(base);
 
-	gicr_write_igrpmodr0(base, reg_val | (1 << bit_num));
+	gicr_write_igrpmodr0(base, reg_val | (1U << bit_num));
 }
 
 /*
@@ -155,10 +159,10 @@ void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
  */
 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_igrpmodr0(base);
 
-	gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num));
+	gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num));
 }
 
 /*
@@ -167,9 +171,9 @@ void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
  */
 void gicr_set_isenabler0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
 
-	gicr_write_isenabler0(base, (1 << bit_num));
+	gicr_write_isenabler0(base, (1U << bit_num));
 }
 
 /*
@@ -178,9 +182,9 @@ void gicr_set_isenabler0(uintptr_t base, unsigned int id)
  */
 void gicr_set_icenabler0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
 
-	gicr_write_icenabler0(base, (1 << bit_num));
+	gicr_write_icenabler0(base, (1U << bit_num));
 }
 
 /*
@@ -189,10 +193,10 @@ void gicr_set_icenabler0(uintptr_t base, unsigned int id)
  */
 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
 	unsigned int reg_val = gicr_read_isactiver0(base);
 
-	return (reg_val >> bit_num) & 0x1;
+	return (reg_val >> bit_num) & 0x1U;
 }
 
 /*
@@ -201,9 +205,9 @@ unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
  */
 void gicr_set_icpendr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
 
-	gicr_write_icpendr0(base, (1 << bit_num));
+	gicr_write_icpendr0(base, (1U << bit_num));
 }
 
 /*
@@ -212,9 +216,9 @@ void gicr_set_icpendr0(uintptr_t base, unsigned int id)
  */
 void gicr_set_ispendr0(uintptr_t base, unsigned int id)
 {
-	unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
+	unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
 
-	gicr_write_ispendr0(base, (1 << bit_num));
+	gicr_write_ispendr0(base, (1U << bit_num));
 }
 
 /*
@@ -223,7 +227,9 @@ void gicr_set_ispendr0(uintptr_t base, unsigned int id)
  */
 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
 {
-	mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK);
+	uint8_t val = pri & GIC_PRI_MASK;
+
+	mmio_write_8(base + GICR_IPRIORITYR + id, val);
 }
 
 /*
@@ -233,8 +239,8 @@ void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
 void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
 {
 	/* Interrupt configuration is a 2-bit field */
-	unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
-	unsigned int bit_shift = bit_num << 1;
+	unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+	unsigned int bit_shift = bit_num << 1U;
 
 	uint32_t reg_val = gicr_read_icfgr0(base);
 
@@ -252,8 +258,8 @@ void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
 void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
 {
 	/* Interrupt configuration is a 2-bit field */
-	unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
-	unsigned int bit_shift = bit_num << 1;
+	unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+	unsigned int bit_shift = bit_num << 1U;
 
 	uint32_t reg_val = gicr_read_icfgr1(base);
 
@@ -274,13 +280,13 @@ void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
 	 * The WAKER_PS_BIT should be changed to 0
 	 * only when WAKER_CA_BIT is 1.
 	 */
-	assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
+	assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
 
 	/* Mark the connected core as awake */
 	gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
 
 	/* Wait till the WAKER_CA_BIT changes to 0 */
-	while (gicr_read_waker(gicr_base) & WAKER_CA_BIT)
+	while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U)
 		;
 }
 
@@ -295,7 +301,7 @@ void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
 	gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
 
 	/* Wait till the WAKER_CA_BIT changes to 1 */
-	while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT))
+	while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U)
 		;
 }
 
@@ -312,10 +318,10 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
 {
 	u_register_t mpidr;
 	unsigned int proc_num;
-	unsigned long long typer_val;
+	uint64_t typer_val;
 	uintptr_t rdistif_base = gicr_base;
 
-	assert(rdistif_base_addrs);
+	assert(rdistif_base_addrs != NULL);
 
 	/*
 	 * Iterate over the Redistributor frames. Store the base address of each
@@ -326,7 +332,7 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
 	 */
 	do {
 		typer_val = gicr_read_typer(rdistif_base);
-		if (mpidr_to_core_pos) {
+		if (mpidr_to_core_pos != NULL) {
 			mpidr = mpidr_from_gicr_typer(typer_val);
 			proc_num = mpidr_to_core_pos(mpidr);
 		} else {
@@ -335,8 +341,8 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
 		}
 		assert(proc_num < rdistif_num);
 		rdistif_base_addrs[proc_num] = rdistif_base;
-		rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
-	} while (!(typer_val & TYPER_LAST_BIT));
+		rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
+	} while ((typer_val & TYPER_LAST_BIT) == 0U);
 }
 
 /*******************************************************************************
@@ -348,17 +354,17 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
 	/*
 	 * Treat all SPIs as G1NS by default. The number of interrupts is
 	 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
 	 */
-	for (index = MIN_SPI_ID; index < num_ints; index += 32)
+	for (index = MIN_SPI_ID; index < num_ints; index += 32U)
 		gicd_write_igroupr(gicd_base, index, ~0U);
 
 	/* Setup the default SPI priorities doing four at a time */
-	for (index = MIN_SPI_ID; index < num_ints; index += 4)
+	for (index = MIN_SPI_ID; index < num_ints; index += 4U)
 		gicd_write_ipriorityr(gicd_base,
 				      index,
 				      GICD_IPRIORITYR_DEF_VAL);
@@ -367,8 +373,8 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
 	 * Treat all SPIs as level triggered by default, write 16 at
 	 * a time
 	 */
-	for (index = MIN_SPI_ID; index < num_ints; index += 16)
-		gicd_write_icfgr(gicd_base, index, 0);
+	for (index = MIN_SPI_ID; index < num_ints; index += 16U)
+		gicd_write_icfgr(gicd_base, index, 0U);
 }
 
 #if !ERROR_DEPRECATED
@@ -385,9 +391,10 @@ void gicv3_secure_spis_config(uintptr_t gicd_base,
 
 	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
 	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+	if (num_ints != 0U)
+		assert(sec_intr_list != NULL);
 
-	for (index = 0; index < num_ints; index++) {
+	for (index = 0U; index < num_ints; index++) {
 		irq_num = sec_intr_list[index];
 		if (irq_num >= MIN_SPI_ID) {
 
@@ -407,7 +414,7 @@ void gicv3_secure_spis_config(uintptr_t gicd_base,
 
 			/* Target SPIs to the primary CPU */
 			gic_affinity_val =
-				gicd_irouter_val_from_mpidr(read_mpidr(), 0);
+				gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
 			gicd_write_irouter(gicd_base,
 					   irq_num,
 					   gic_affinity_val);
@@ -430,12 +437,13 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
 	unsigned int i;
 	const interrupt_prop_t *current_prop;
 	unsigned long long gic_affinity_val;
-	unsigned int ctlr_enable = 0;
+	unsigned int ctlr_enable = 0U;
 
 	/* Make sure there's a valid property array */
-	assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
+	if (interrupt_props_num > 0U)
+		assert(interrupt_props != NULL);
 
-	for (i = 0; i < interrupt_props_num; i++) {
+	for (i = 0U; i < interrupt_props_num; i++) {
 		current_prop = &interrupt_props[i];
 
 		if (current_prop->intr_num < MIN_SPI_ID)
@@ -464,7 +472,8 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
 				current_prop->intr_pri);
 
 		/* Target SPIs to the primary CPU */
-		gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
+		gic_affinity_val =
+			gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
 		gicd_write_irouter(gicd_base, current_prop->intr_num,
 				gic_affinity_val);
 
@@ -487,20 +496,20 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
 	 * more scalable approach as it avoids clearing the enable bits in the
 	 * GICD_CTLR
 	 */
-	gicr_write_icenabler0(gicr_base, ~0);
+	gicr_write_icenabler0(gicr_base, ~0U);
 	gicr_wait_for_pending_write(gicr_base);
 
 	/* Treat all SGIs/PPIs as G1NS by default. */
 	gicr_write_igroupr0(gicr_base, ~0U);
 
 	/* Setup the default PPI/SGI priorities doing four at a time */
-	for (index = 0; index < MIN_SPI_ID; index += 4)
+	for (index = 0U; index < MIN_SPI_ID; index += 4U)
 		gicr_write_ipriorityr(gicr_base,
 				      index,
 				      GICD_IPRIORITYR_DEF_VAL);
 
 	/* Configure all PPIs as level triggered by default */
-	gicr_write_icfgr1(gicr_base, 0);
+	gicr_write_icfgr1(gicr_base, 0U);
 }
 
 #if !ERROR_DEPRECATED
@@ -516,7 +525,8 @@ void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
 
 	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
 	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+	if (num_ints != 0U)
+		assert(sec_intr_list != NULL);
 
 	for (index = 0; index < num_ints; index++) {
 		irq_num = sec_intr_list[index];
@@ -552,12 +562,13 @@ unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
 {
 	unsigned int i;
 	const interrupt_prop_t *current_prop;
-	unsigned int ctlr_enable = 0;
+	unsigned int ctlr_enable = 0U;
 
 	/* Make sure there's a valid property array */
-	assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
+	if (interrupt_props_num > 0U)
+		assert(interrupt_props != NULL);
 
-	for (i = 0; i < interrupt_props_num; i++) {
+	for (i = 0U; i < interrupt_props_num; i++) {
 		current_prop = &interrupt_props[i];
 
 		if (current_prop->intr_num >= MIN_SPI_ID)

drivers/arm/gic/v3/gicv3_main.c

@@ -34,21 +34,21 @@ static spinlock_t gic_lock;
 /* Helper macros to save and restore GICD registers to and from the context */
 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG)		\
 	do {								\
-		for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
-				int_id += (1 << REG##_SHIFT)) {		\
+		for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
+				int_id += (1U << REG##_SHIFT)) {	\
 			gicd_write_##reg(base, int_id,			\
 				ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
 		}							\
-	} while (0)
+	} while (false)
 
 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG)			\
 	do {								\
-		for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
-				int_id += (1 << REG##_SHIFT)) {		\
+		for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
+				int_id += (1U << REG##_SHIFT)) {	\
 			ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
 					gicd_read_##reg(base, int_id);	\
 		}							\
-	} while (0)
+	} while (false)
 
 
 /*******************************************************************************
@@ -59,11 +59,11 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 {
 	unsigned int gic_version;
 
-	assert(plat_driver_data);
-	assert(plat_driver_data->gicd_base);
-	assert(plat_driver_data->gicr_base);
-	assert(plat_driver_data->rdistif_num);
-	assert(plat_driver_data->rdistif_base_addrs);
+	assert(plat_driver_data != NULL);
+	assert(plat_driver_data->gicd_base != 0U);
+	assert(plat_driver_data->gicr_base != 0U);
+	assert(plat_driver_data->rdistif_num != 0U);
+	assert(plat_driver_data->rdistif_base_addrs != NULL);
 
 	assert(IS_IN_EL3());
 
@@ -109,10 +109,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 
 	/* Check for system register support */
 #ifdef AARCH32
-	assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
+	assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
 #else
-	assert(read_id_aa64pfr0_el1() &
-			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
+	assert((read_id_aa64pfr0_el1() &
+			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
 #endif /* AARCH32 */
 
 	/* The GIC version should be 3.0 */
@@ -170,8 +170,8 @@ void gicv3_distif_init(void)
 {
 	unsigned int bitmap = 0;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	assert(IS_IN_EL3());
 
@@ -245,16 +245,16 @@ void gicv3_distif_init(void)
 void gicv3_rdistif_init(unsigned int proc_num)
 {
 	uintptr_t gicr_base;
-	unsigned int bitmap = 0;
+	unsigned int bitmap = 0U;
 	uint32_t ctlr;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
-	assert(ctlr & CTLR_ARE_S_BIT);
+	assert((ctlr & CTLR_ARE_S_BIT) != 0U);
 
 	assert(IS_IN_EL3());
 
@@ -333,9 +333,9 @@ void gicv3_cpuif_enable(unsigned int proc_num)
 	unsigned int scr_el3;
 	unsigned int icc_sre_el3;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
 
 	/* Mark the connected core as awake */
@@ -353,7 +353,7 @@ void gicv3_cpuif_enable(unsigned int proc_num)
 	icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
 	write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
 
-	scr_el3 = read_scr_el3();
+	scr_el3 = (uint32_t) read_scr_el3();
 
 	/*
 	 * Switch to NS state to write Non secure ICC_SRE_EL1 and
@@ -393,9 +393,9 @@ void gicv3_cpuif_disable(unsigned int proc_num)
 {
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	assert(IS_IN_EL3());
 
@@ -429,14 +429,14 @@ unsigned int gicv3_get_pending_interrupt_id(void)
 	unsigned int id;
 
 	assert(IS_IN_EL3());
-	id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
+	id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
 
 	/*
 	 * If the ID is special identifier corresponding to G1S or G1NS
 	 * interrupt, then read the highest pending group 1 interrupt.
 	 */
 	if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
-		return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
+		return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
 
 	return id;
 }
@@ -453,7 +453,7 @@ unsigned int gicv3_get_pending_interrupt_id(void)
 unsigned int gicv3_get_pending_interrupt_type(void)
 {
 	assert(IS_IN_EL3());
-	return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
+	return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
 }
 
 /*******************************************************************************
@@ -473,10 +473,10 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
 	uintptr_t gicr_base;
 
 	assert(IS_IN_EL3());
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 
 	/* Ensure the parameters are valid */
-	assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID);
+	assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
 	assert(proc_num < gicv3_driver_data->rdistif_num);
 
 	/* All LPI interrupts are Group 1 non secure */
@@ -484,12 +484,12 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
 		return INTR_GROUP1NS;
 
 	if (id < MIN_SPI_ID) {
-		assert(gicv3_driver_data->rdistif_base_addrs);
+		assert(gicv3_driver_data->rdistif_base_addrs != 0U);
 		gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 		igroup = gicr_get_igroupr0(gicr_base, id);
 		grpmodr = gicr_get_igrpmodr0(gicr_base, id);
 	} else {
-		assert(gicv3_driver_data->gicd_base);
+		assert(gicv3_driver_data->gicd_base != 0U);
 		igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
 		grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
 	}
@@ -498,11 +498,11 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
 	 * If the IGROUP bit is set, then it is a Group 1 Non secure
 	 * interrupt
 	 */
-	if (igroup)
+	if (igroup != 0U)
 		return INTR_GROUP1NS;
 
 	/* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
-	if (grpmodr)
+	if (grpmodr != 0U)
 		return INTR_GROUP1S;
 
 	/* Else it is a Group 0 Secure interrupt */
@@ -522,12 +522,12 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
  *****************************************************************************/
 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
 {
-	int i;
+	unsigned int i;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(IS_IN_EL3());
-	assert(its_ctx);
-	assert(gits_base);
+	assert(its_ctx != NULL);
+	assert(gits_base != 0U);
 
 	its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
 
@@ -555,16 +555,16 @@ void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx
  *****************************************************************************/
 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
 {
-	int i;
+	unsigned int i;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(IS_IN_EL3());
-	assert(its_ctx);
-	assert(gits_base);
+	assert(its_ctx != NULL);
+	assert(gits_base != 0U);
 
 	/* Assert that the GITS is disabled and quiescent */
-	assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0);
-	assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0);
+	assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
+	assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
 
 	gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
 	gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
@@ -586,11 +586,11 @@ void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_
 	uintptr_t gicr_base;
 	unsigned int int_id;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
-	assert(rdist_ctx);
+	assert(rdist_ctx != NULL);
 
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 
@@ -614,7 +614,7 @@ void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_
 	rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
 	rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
 	for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
-			int_id += (1 << IPRIORITYR_SHIFT)) {
+			int_id += (1U << IPRIORITYR_SHIFT)) {
 		rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
 				gicr_read_ipriorityr(gicr_base, int_id);
 	}
@@ -641,11 +641,11 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
 	uintptr_t gicr_base;
 	unsigned int int_id;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
-	assert(rdist_ctx);
+	assert(rdist_ctx != NULL);
 
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 
@@ -664,7 +664,7 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
 	 * more scalable approach as it avoids clearing the enable bits in the
 	 * GICD_CTLR
 	 */
-	gicr_write_icenabler0(gicr_base, ~0);
+	gicr_write_icenabler0(gicr_base, ~0U);
 	/* Wait for pending writes to GICR_ICENABLER */
 	gicr_wait_for_pending_write(gicr_base);
 
@@ -682,7 +682,7 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
 	gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
 
 	for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
-			int_id += (1 << IPRIORITYR_SHIFT)) {
+			int_id += (1U << IPRIORITYR_SHIFT)) {
 		gicr_write_ipriorityr(gicr_base, int_id,
 		rdist_ctx->gicr_ipriorityr[
 				(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
@@ -722,18 +722,18 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
 {
 	unsigned int num_ints;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
-	assert(dist_ctx);
+	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= MAX_SPI_ID + 1);
+	assert(num_ints <= (MAX_SPI_ID + 1U));
 
 	/* Wait for pending write to complete */
 	gicd_wait_for_pending_write(gicd_base);
@@ -784,12 +784,12 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
  *****************************************************************************/
 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int num_ints = 0;
+	unsigned int num_ints = 0U;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
-	assert(dist_ctx);
+	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
 
@@ -809,9 +809,9 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= MAX_SPI_ID + 1);
+	assert(num_ints <= (MAX_SPI_ID + 1U));
 
 	/* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
@@ -857,7 +857,7 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
  ******************************************************************************/
 unsigned int gicv3_get_running_priority(void)
 {
-	return read_icc_rpr_el1();
+	return (unsigned int)read_icc_rpr_el1();
 }
 
 /*******************************************************************************
@@ -870,10 +870,10 @@ unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
 {
 	unsigned int value;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	if (id < MIN_SPI_ID) {
@@ -894,10 +894,10 @@ unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
  ******************************************************************************/
 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -922,10 +922,10 @@ void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
  ******************************************************************************/
 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -960,10 +960,10 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
 {
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	if (id < MIN_SPI_ID) {
@@ -982,29 +982,29 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
 		unsigned int type)
 {
-	unsigned int igroup = 0, grpmod = 0;
+	bool igroup = false, grpmod = false;
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	switch (type) {
 	case INTR_GROUP1S:
-		igroup = 0;
-		grpmod = 1;
+		igroup = false;
+		grpmod = true;
 		break;
 	case INTR_GROUP0:
-		igroup = 0;
-		grpmod = 0;
+		igroup = false;
+		grpmod = false;
 		break;
 	case INTR_GROUP1NS:
-		igroup = 1;
-		grpmod = 0;
+		igroup = true;
+		grpmod = false;
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 
@@ -1040,7 +1040,7 @@ void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
  *
  * The target parameter must be a valid MPIDR in the system.
  ******************************************************************************/
-void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
+void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
 {
 	unsigned int tgt, aff3, aff2, aff1, aff0;
 	uint64_t sgi_val;
@@ -1059,7 +1059,7 @@ void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
 	 * this PE.
 	 */
 	assert(aff0 < GICV3_MAX_SGI_TARGETS);
-	tgt = BIT(aff0);
+	tgt = BIT_32(aff0);
 
 	/* Raise SGI to PE specified by its affinity */
 	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
@@ -1090,11 +1090,11 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
 	unsigned long long aff;
 	uint64_t router;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
-	assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
+	assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
 
 	aff = gicd_irouter_val_from_mpidr(mpidr, irm);
 	gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
@@ -1105,7 +1105,7 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
 	 */
 	if (irm == GICV3_IRM_ANY) {
 		router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
-		if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) {
+		if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
 			ERROR("GICv3 implementation doesn't support routing ANY\n");
 			panic();
 		}
@@ -1119,10 +1119,10 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
  ******************************************************************************/
 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	/*
 	 * Clear pending interrupt, and ensure that any shared variable updates
@@ -1145,10 +1145,10 @@ void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
  ******************************************************************************/
 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	/*
 	 * Ensure that any shared variable updates depending on out of band
@@ -1172,7 +1172,7 @@ unsigned int gicv3_set_pmr(unsigned int mask)
 {
 	unsigned int old_mask;
 
-	old_mask = read_icc_pmr_el1();
+	old_mask = (uint32_t) read_icc_pmr_el1();
 
 	/*
 	 * Order memory updates w.r.t. PMR write, and ensure they're visible

drivers/arm/gic/v3/gicv3_private.h

@@ -19,28 +19,36 @@
  ******************************************************************************/
 
 /* Constants to indicate the status of the RWP bit */
-#define RWP_TRUE		1
-#define RWP_FALSE		0
+#define RWP_TRUE		U(1)
+#define RWP_FALSE		U(0)
 
 /*
  * Macro to convert an mpidr to a value suitable for programming into a
  * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
  * to GICv3.
  */
-#define gicd_irouter_val_from_mpidr(_mpidr, _irm)		\
-	((_mpidr & ~(0xff << 24)) |			\
-	 (_irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
+static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr,
+						       unsigned int irm)
+{
+	return (mpidr & ~(U(0xff) << 24)) |
+		((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT);
+}
 
 /*
  * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
  * are zeroes.
  */
 #ifdef AARCH32
-#define mpidr_from_gicr_typer(_typer_val)	(((_typer_val) >> 32) & 0xffffff)
+static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
+{
+	return (((typer_val) >> 32) & U(0xffffff));
+}
 #else
-#define mpidr_from_gicr_typer(_typer_val)				 \
-	(((((_typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
-	 (((_typer_val) >> 32) & 0xffffff))
+static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
+{
+	return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
+		((typer_val >> 32) & U(0xffffff));
+}
 #endif
 
 /*******************************************************************************
@@ -121,7 +129,7 @@ void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
  */
 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
 {
-	while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
+	while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U)
 		;
 }
 
@@ -149,7 +157,7 @@ static inline void gicd_clr_ctlr(uintptr_t base,
 				 unsigned int rwp)
 {
 	gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
-	if (rwp)
+	if (rwp != 0U)
 		gicd_wait_for_pending_write(base);
 }
 
@@ -158,21 +166,21 @@ static inline void gicd_set_ctlr(uintptr_t base,
 				 unsigned int rwp)
 {
 	gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
-	if (rwp)
+	if (rwp != 0U)
 		gicd_wait_for_pending_write(base);
 }
 
 /*******************************************************************************
  * GIC Redistributor interface accessors
  ******************************************************************************/
-static inline unsigned long long gicr_read_ctlr(uintptr_t base)
+static inline uint32_t gicr_read_ctlr(uintptr_t base)
 {
-	return mmio_read_64(base + GICR_CTLR);
+	return mmio_read_32(base + GICR_CTLR);
 }
 
-static inline void gicr_write_ctlr(uintptr_t base, uint64_t val)
+static inline void gicr_write_ctlr(uintptr_t base, uint32_t val)
 {
-	mmio_write_64(base + GICR_CTLR, val);
+	mmio_write_32(base + GICR_CTLR, val);
 }
 
 static inline unsigned long long gicr_read_typer(uintptr_t base)
@@ -199,13 +207,13 @@ static inline void gicr_write_waker(uintptr_t base, unsigned int val)
  */
 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
 {
-	while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
+	while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U)
 		;
 }
 
 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
 {
-	while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT)
+	while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U)
 		;
 }
 
@@ -313,24 +321,24 @@ static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
 	mmio_write_32(base + GICR_ICFGR1, val);
 }
 
-static inline unsigned int gicr_read_propbaser(uintptr_t base)
+static inline uint64_t gicr_read_propbaser(uintptr_t base)
 {
-	return mmio_read_32(base + GICR_PROPBASER);
+	return mmio_read_64(base + GICR_PROPBASER);
 }
 
-static inline void gicr_write_propbaser(uintptr_t base, unsigned int val)
+static inline void gicr_write_propbaser(uintptr_t base, uint64_t val)
 {
-	mmio_write_32(base + GICR_PROPBASER, val);
+	mmio_write_64(base + GICR_PROPBASER, val);
 }
 
-static inline unsigned int gicr_read_pendbaser(uintptr_t base)
+static inline uint64_t gicr_read_pendbaser(uintptr_t base)
 {
-	return mmio_read_32(base + GICR_PENDBASER);
+	return mmio_read_64(base + GICR_PENDBASER);
 }
 
-static inline void gicr_write_pendbaser(uintptr_t base, unsigned int val)
+static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val)
 {
-	mmio_write_32(base + GICR_PENDBASER, val);
+	mmio_write_64(base + GICR_PENDBASER, val);
 }
 
 /*******************************************************************************
@@ -353,7 +361,7 @@ static inline uint64_t gits_read_cbaser(uintptr_t base)
 
 static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
 {
-	mmio_write_32(base + GITS_CBASER, val);
+	mmio_write_64(base + GITS_CBASER, val);
 }
 
 static inline uint64_t gits_read_cwriter(uintptr_t base)
@@ -363,19 +371,19 @@ static inline uint64_t gits_read_cwriter(uintptr_t base)
 
 static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
 {
-	mmio_write_32(base + GITS_CWRITER, val);
+	mmio_write_64(base + GITS_CWRITER, val);
 }
 
 static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id)
 {
-	assert(its_table_id < 8);
-	return mmio_read_64(base + GITS_BASER + (8 * its_table_id));
+	assert(its_table_id < 8U);
+	return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
 }
 
 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val)
 {
-	assert(its_table_id < 8);
-	mmio_write_64(base + GITS_BASER + (8 * its_table_id), val);
+	assert(its_table_id < 8U);
+	mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
 }
 
 /*
@@ -383,8 +391,8 @@ static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, u
  */
 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
 {
-	assert(!(gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT));
-	while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0)
+	assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
+	while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U)
 		;
 }
 

include/drivers/arm/gic_common.h

@@ -13,23 +13,23 @@
  * GIC Distributor interface general definitions
  ******************************************************************************/
 /* Constants to categorise interrupts */
-#define MIN_SGI_ID		0
-#define MIN_SEC_SGI_ID		8
-#define MIN_PPI_ID		16
-#define MIN_SPI_ID		32
-#define MAX_SPI_ID		1019
+#define MIN_SGI_ID		U(0)
+#define MIN_SEC_SGI_ID		U(8)
+#define MIN_PPI_ID		U(16)
+#define MIN_SPI_ID		U(32)
+#define MAX_SPI_ID		U(1019)
 
-#define TOTAL_SPI_INTR_NUM	(MAX_SPI_ID - MIN_SPI_ID + 1)
+#define TOTAL_SPI_INTR_NUM	(MAX_SPI_ID - MIN_SPI_ID + U(1))
 #define TOTAL_PCPU_INTR_NUM	(MIN_SPI_ID - MIN_SGI_ID)
 
 /* Mask for the priority field common to all GIC interfaces */
-#define GIC_PRI_MASK			0xff
+#define GIC_PRI_MASK			U(0xff)
 
 /* Mask for the configuration field common to all GIC interfaces */
-#define GIC_CFG_MASK			0x3
+#define GIC_CFG_MASK			U(0x3)
 
 /* Constant to indicate a spurious interrupt in all GIC versions */
-#define GIC_SPURIOUS_INTERRUPT		1023
+#define GIC_SPURIOUS_INTERRUPT		U(1023)
 
 /* Interrupt configurations: 2-bit fields with LSB reserved */
 #define GIC_INTR_CFG_LEVEL		(0 << 1)
@@ -44,38 +44,38 @@
 /*******************************************************************************
  * GIC Distributor interface register offsets that are common to GICv3 & GICv2
  ******************************************************************************/
-#define GICD_CTLR		0x0
-#define GICD_TYPER		0x4
-#define GICD_IIDR		0x8
-#define GICD_IGROUPR		0x80
-#define GICD_ISENABLER		0x100
-#define GICD_ICENABLER		0x180
-#define GICD_ISPENDR		0x200
-#define GICD_ICPENDR		0x280
-#define GICD_ISACTIVER		0x300
-#define GICD_ICACTIVER		0x380
-#define GICD_IPRIORITYR		0x400
-#define GICD_ICFGR		0xc00
-#define GICD_NSACR		0xe00
+#define GICD_CTLR		U(0x0)
+#define GICD_TYPER		U(0x4)
+#define GICD_IIDR		U(0x8)
+#define GICD_IGROUPR		U(0x80)
+#define GICD_ISENABLER		U(0x100)
+#define GICD_ICENABLER		U(0x180)
+#define GICD_ISPENDR		U(0x200)
+#define GICD_ICPENDR		U(0x280)
+#define GICD_ISACTIVER		U(0x300)
+#define GICD_ICACTIVER		U(0x380)
+#define GICD_IPRIORITYR		U(0x400)
+#define GICD_ICFGR		U(0xc00)
+#define GICD_NSACR		U(0xe00)
 
 /* GICD_CTLR bit definitions */
 #define CTLR_ENABLE_G0_SHIFT		0
-#define CTLR_ENABLE_G0_MASK		0x1
-#define CTLR_ENABLE_G0_BIT		(1 << CTLR_ENABLE_G0_SHIFT)
+#define CTLR_ENABLE_G0_MASK		U(0x1)
+#define CTLR_ENABLE_G0_BIT		BIT_32(CTLR_ENABLE_G0_SHIFT)
 
 
 /*******************************************************************************
  * GIC Distributor interface register constants that are common to GICv3 & GICv2
  ******************************************************************************/
 #define PIDR2_ARCH_REV_SHIFT	4
-#define PIDR2_ARCH_REV_MASK	0xf
+#define PIDR2_ARCH_REV_MASK	U(0xf)
 
 /* GICv3 revision as reported by the PIDR2 register */
-#define ARCH_REV_GICV3		0x3
+#define ARCH_REV_GICV3		U(0x3)
 /* GICv2 revision as reported by the PIDR2 register */
-#define ARCH_REV_GICV2		0x2
+#define ARCH_REV_GICV2		U(0x2)
 /* GICv1 revision as reported by the PIDR2 register */
-#define ARCH_REV_GICV1		0x1
+#define ARCH_REV_GICV1		U(0x1)
 
 #define IGROUPR_SHIFT		5
 #define ISENABLER_SHIFT		5
@@ -90,8 +90,8 @@
 #define NSACR_SHIFT		4
 
 /* GICD_TYPER shifts and masks */
-#define TYPER_IT_LINES_NO_SHIFT	0
-#define TYPER_IT_LINES_NO_MASK	0x1f
+#define TYPER_IT_LINES_NO_SHIFT	U(0)
+#define TYPER_IT_LINES_NO_MASK	U(0x1f)
 
 /* Value used to initialize Normal world interrupt priorities four at a time */
 #define GICD_IPRIORITYR_DEF_VAL			\

include/drivers/arm/gicv2.h

@@ -12,37 +12,37 @@
  ******************************************************************************/
 
 /* Interrupt group definitions */
-#define GICV2_INTR_GROUP0	0
-#define GICV2_INTR_GROUP1	1
+#define GICV2_INTR_GROUP0	U(0)
+#define GICV2_INTR_GROUP1	U(1)
 
 /* Interrupt IDs reported by the HPPIR and IAR registers */
-#define PENDING_G1_INTID	1022
+#define PENDING_G1_INTID	U(1022)
 
 /* GICv2 can only target up to 8 PEs */
-#define GICV2_MAX_TARGET_PE	8
+#define GICV2_MAX_TARGET_PE	U(8)
 
 /*******************************************************************************
  * GICv2 specific Distributor interface register offsets and constants.
  ******************************************************************************/
-#define GICD_ITARGETSR		0x800
-#define GICD_SGIR		0xF00
-#define GICD_CPENDSGIR		0xF10
-#define GICD_SPENDSGIR		0xF20
-#define GICD_PIDR2_GICV2	0xFE8
+#define GICD_ITARGETSR		U(0x800)
+#define GICD_SGIR		U(0xF00)
+#define GICD_CPENDSGIR		U(0xF10)
+#define GICD_SPENDSGIR		U(0xF20)
+#define GICD_PIDR2_GICV2	U(0xFE8)
 
 #define ITARGETSR_SHIFT		2
-#define GIC_TARGET_CPU_MASK	0xff
+#define GIC_TARGET_CPU_MASK	U(0xff)
 
 #define CPENDSGIR_SHIFT		2
 #define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
 
 #define SGIR_TGTLSTFLT_SHIFT	24
-#define SGIR_TGTLSTFLT_MASK	0x3
+#define SGIR_TGTLSTFLT_MASK	U(0x3)
 #define SGIR_TGTLST_SHIFT	16
-#define SGIR_TGTLST_MASK	0xff
-#define SGIR_INTID_MASK		0xf
+#define SGIR_TGTLST_MASK	U(0xff)
+#define SGIR_INTID_MASK		ULL(0xf)
 
-#define SGIR_TGT_SPECIFIC	0
+#define SGIR_TGT_SPECIFIC	U(0)
 
 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
 	((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
@@ -53,29 +53,29 @@
  * GICv2 specific CPU interface register offsets and constants.
  ******************************************************************************/
 /* Physical CPU Interface registers */
-#define GICC_CTLR		0x0
-#define GICC_PMR		0x4
-#define GICC_BPR		0x8
-#define GICC_IAR		0xC
-#define GICC_EOIR		0x10
-#define GICC_RPR		0x14
-#define GICC_HPPIR		0x18
-#define GICC_AHPPIR		0x28
-#define GICC_IIDR		0xFC
-#define GICC_DIR		0x1000
+#define GICC_CTLR		U(0x0)
+#define GICC_PMR		U(0x4)
+#define GICC_BPR		U(0x8)
+#define GICC_IAR		U(0xC)
+#define GICC_EOIR		U(0x10)
+#define GICC_RPR		U(0x14)
+#define GICC_HPPIR		U(0x18)
+#define GICC_AHPPIR		U(0x28)
+#define GICC_IIDR		U(0xFC)
+#define GICC_DIR		U(0x1000)
 #define GICC_PRIODROP		GICC_EOIR
 
 /* GICC_CTLR bit definitions */
-#define EOI_MODE_NS		(1 << 10)
-#define EOI_MODE_S		(1 << 9)
-#define IRQ_BYP_DIS_GRP1	(1 << 8)
-#define FIQ_BYP_DIS_GRP1	(1 << 7)
-#define IRQ_BYP_DIS_GRP0	(1 << 6)
-#define FIQ_BYP_DIS_GRP0	(1 << 5)
-#define CBPR			(1 << 4)
+#define EOI_MODE_NS		BIT_32(10)
+#define EOI_MODE_S		BIT_32(9)
+#define IRQ_BYP_DIS_GRP1	BIT_32(8)
+#define FIQ_BYP_DIS_GRP1	BIT_32(7)
+#define IRQ_BYP_DIS_GRP0	BIT_32(6)
+#define FIQ_BYP_DIS_GRP0	BIT_32(5)
+#define CBPR			BIT_32(4)
 #define FIQ_EN_SHIFT		3
-#define FIQ_EN_BIT		(1 << FIQ_EN_SHIFT)
-#define ACK_CTL			(1 << 2)
+#define FIQ_EN_BIT		BIT_32(FIQ_EN_SHIFT)
+#define ACK_CTL			BIT_32(2)
 
 /* GICC_IIDR bit masks and shifts */
 #define GICC_IIDR_PID_SHIFT	20
@@ -83,36 +83,36 @@
 #define GICC_IIDR_REV_SHIFT	12
 #define GICC_IIDR_IMP_SHIFT	0
 
-#define GICC_IIDR_PID_MASK	0xfff
-#define GICC_IIDR_ARCH_MASK	0xf
-#define GICC_IIDR_REV_MASK	0xf
-#define GICC_IIDR_IMP_MASK	0xfff
+#define GICC_IIDR_PID_MASK	U(0xfff)
+#define GICC_IIDR_ARCH_MASK	U(0xf)
+#define GICC_IIDR_REV_MASK	U(0xf)
+#define GICC_IIDR_IMP_MASK	U(0xfff)
 
 /* HYP view virtual CPU Interface registers */
-#define GICH_CTL		0x0
-#define GICH_VTR		0x4
-#define GICH_ELRSR0		0x30
-#define GICH_ELRSR1		0x34
-#define GICH_APR0		0xF0
-#define GICH_LR_BASE		0x100
+#define GICH_CTL		U(0x0)
+#define GICH_VTR		U(0x4)
+#define GICH_ELRSR0		U(0x30)
+#define GICH_ELRSR1		U(0x34)
+#define GICH_APR0		U(0xF0)
+#define GICH_LR_BASE		U(0x100)
 
 /* Virtual CPU Interface registers */
-#define GICV_CTL		0x0
-#define GICV_PRIMASK		0x4
-#define GICV_BP			0x8
-#define GICV_INTACK		0xC
-#define GICV_EOI		0x10
-#define GICV_RUNNINGPRI		0x14
-#define GICV_HIGHESTPEND	0x18
-#define GICV_DEACTIVATE		0x1000
+#define GICV_CTL		U(0x0)
+#define GICV_PRIMASK		U(0x4)
+#define GICV_BP			U(0x8)
+#define GICV_INTACK		U(0xC)
+#define GICV_EOI		U(0x10)
+#define GICV_RUNNINGPRI		U(0x14)
+#define GICV_HIGHESTPEND	U(0x18)
+#define GICV_DEACTIVATE		U(0x1000)
 
 /* GICD_CTLR bit definitions */
 #define CTLR_ENABLE_G1_SHIFT		1
-#define CTLR_ENABLE_G1_MASK		0x1
-#define CTLR_ENABLE_G1_BIT		(1 << CTLR_ENABLE_G1_SHIFT)
+#define CTLR_ENABLE_G1_MASK		U(0x1)
+#define CTLR_ENABLE_G1_BIT		BIT_32(CTLR_ENABLE_G1_SHIFT)
 
 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
-#define INT_ID_MASK		0x3ff
+#define INT_ID_MASK		U(0x3ff)
 
 #ifndef __ASSEMBLY__
 

include/drivers/arm/gicv3.h

@@ -11,35 +11,35 @@
  * GICv3 miscellaneous definitions
  ******************************************************************************/
 /* Interrupt group definitions */
-#define INTR_GROUP1S		0
-#define INTR_GROUP0		1
-#define INTR_GROUP1NS		2
+#define INTR_GROUP1S		U(0)
+#define INTR_GROUP0		U(1)
+#define INTR_GROUP1NS		U(2)
 
 /* Interrupt IDs reported by the HPPIR and IAR registers */
-#define PENDING_G1S_INTID	1020
-#define PENDING_G1NS_INTID	1021
+#define PENDING_G1S_INTID	U(1020)
+#define PENDING_G1NS_INTID	U(1021)
 
 /* Constant to categorize LPI interrupt */
-#define MIN_LPI_ID		8192
+#define MIN_LPI_ID		U(8192)
 
 /* GICv3 can only target up to 16 PEs with SGI */
-#define GICV3_MAX_SGI_TARGETS	16
+#define GICV3_MAX_SGI_TARGETS	U(16)
 
 /*******************************************************************************
  * GICv3 specific Distributor interface register offsets and constants.
  ******************************************************************************/
-#define GICD_STATUSR		0x10
-#define GICD_SETSPI_NSR		0x40
-#define GICD_CLRSPI_NSR		0x48
-#define GICD_SETSPI_SR		0x50
-#define GICD_CLRSPI_SR		0x50
-#define GICD_IGRPMODR		0xd00
+#define GICD_STATUSR		U(0x10)
+#define GICD_SETSPI_NSR		U(0x40)
+#define GICD_CLRSPI_NSR		U(0x48)
+#define GICD_SETSPI_SR		U(0x50)
+#define GICD_CLRSPI_SR		U(0x50)
+#define GICD_IGRPMODR		U(0xd00)
 /*
  * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
  * n >= 32, making the effective offset as 0x6100.
  */
-#define GICD_IROUTER		0x6000
-#define GICD_PIDR2_GICV3	0xffe8
+#define GICD_IROUTER		U(0x6000)
+#define GICD_PIDR2_GICV3	U(0xffe8)
 
 #define IGRPMODR_SHIFT		5
 
@@ -52,29 +52,29 @@
 #define CTLR_E1NWF_SHIFT		7
 #define GICD_CTLR_RWP_SHIFT		31
 
-#define CTLR_ENABLE_G1NS_MASK		0x1
-#define CTLR_ENABLE_G1S_MASK		0x1
-#define CTLR_ARE_S_MASK			0x1
-#define CTLR_ARE_NS_MASK		0x1
-#define CTLR_DS_MASK			0x1
-#define CTLR_E1NWF_MASK			0x1
-#define GICD_CTLR_RWP_MASK		0x1
-
-#define CTLR_ENABLE_G1NS_BIT		(1 << CTLR_ENABLE_G1NS_SHIFT)
-#define CTLR_ENABLE_G1S_BIT		(1 << CTLR_ENABLE_G1S_SHIFT)
-#define CTLR_ARE_S_BIT			(1 << CTLR_ARE_S_SHIFT)
-#define CTLR_ARE_NS_BIT			(1 << CTLR_ARE_NS_SHIFT)
-#define CTLR_DS_BIT			(1 << CTLR_DS_SHIFT)
-#define CTLR_E1NWF_BIT			(1 << CTLR_E1NWF_SHIFT)
-#define GICD_CTLR_RWP_BIT		(1 << GICD_CTLR_RWP_SHIFT)
+#define CTLR_ENABLE_G1NS_MASK		U(0x1)
+#define CTLR_ENABLE_G1S_MASK		U(0x1)
+#define CTLR_ARE_S_MASK			U(0x1)
+#define CTLR_ARE_NS_MASK		U(0x1)
+#define CTLR_DS_MASK			U(0x1)
+#define CTLR_E1NWF_MASK			U(0x1)
+#define GICD_CTLR_RWP_MASK		U(0x1)
+
+#define CTLR_ENABLE_G1NS_BIT		BIT_32(CTLR_ENABLE_G1NS_SHIFT)
+#define CTLR_ENABLE_G1S_BIT		BIT_32(CTLR_ENABLE_G1S_SHIFT)
+#define CTLR_ARE_S_BIT			BIT_32(CTLR_ARE_S_SHIFT)
+#define CTLR_ARE_NS_BIT			BIT_32(CTLR_ARE_NS_SHIFT)
+#define CTLR_DS_BIT			BIT_32(CTLR_DS_SHIFT)
+#define CTLR_E1NWF_BIT			BIT_32(CTLR_E1NWF_SHIFT)
+#define GICD_CTLR_RWP_BIT		BIT_32(GICD_CTLR_RWP_SHIFT)
 
 /* GICD_IROUTER shifts and masks */
 #define IROUTER_SHIFT		0
 #define IROUTER_IRM_SHIFT	31
-#define IROUTER_IRM_MASK	0x1
+#define IROUTER_IRM_MASK	U(0x1)
 
-#define GICV3_IRM_PE		0
-#define GICV3_IRM_ANY		1
+#define GICV3_IRM_PE		U(0)
+#define GICV3_IRM_ANY		U(1)
 
 #define NUM_OF_DIST_REGS	30
 
@@ -82,54 +82,54 @@
  * GICv3 Re-distributor interface registers & constants
  ******************************************************************************/
 #define GICR_PCPUBASE_SHIFT	0x11
-#define GICR_SGIBASE_OFFSET	(1 << 0x10)	/* 64 KB */
-#define GICR_CTLR		0x0
-#define GICR_TYPER		0x08
-#define GICR_WAKER		0x14
-#define GICR_PROPBASER		0x70
-#define GICR_PENDBASER		0x78
-#define GICR_IGROUPR0		(GICR_SGIBASE_OFFSET + 0x80)
-#define GICR_ISENABLER0		(GICR_SGIBASE_OFFSET + 0x100)
-#define GICR_ICENABLER0		(GICR_SGIBASE_OFFSET + 0x180)
-#define GICR_ISPENDR0		(GICR_SGIBASE_OFFSET + 0x200)
-#define GICR_ICPENDR0		(GICR_SGIBASE_OFFSET + 0x280)
-#define GICR_ISACTIVER0		(GICR_SGIBASE_OFFSET + 0x300)
-#define GICR_ICACTIVER0		(GICR_SGIBASE_OFFSET + 0x380)
-#define GICR_IPRIORITYR		(GICR_SGIBASE_OFFSET + 0x400)
-#define GICR_ICFGR0		(GICR_SGIBASE_OFFSET + 0xc00)
-#define GICR_ICFGR1		(GICR_SGIBASE_OFFSET + 0xc04)
-#define GICR_IGRPMODR0		(GICR_SGIBASE_OFFSET + 0xd00)
-#define GICR_NSACR		(GICR_SGIBASE_OFFSET + 0xe00)
+#define GICR_SGIBASE_OFFSET	U(65536)	/* 64 KB */
+#define GICR_CTLR		U(0x0)
+#define GICR_TYPER		U(0x08)
+#define GICR_WAKER		U(0x14)
+#define GICR_PROPBASER		U(0x70)
+#define GICR_PENDBASER		U(0x78)
+#define GICR_IGROUPR0		(GICR_SGIBASE_OFFSET + U(0x80))
+#define GICR_ISENABLER0		(GICR_SGIBASE_OFFSET + U(0x100))
+#define GICR_ICENABLER0		(GICR_SGIBASE_OFFSET + U(0x180))
+#define GICR_ISPENDR0		(GICR_SGIBASE_OFFSET + U(0x200))
+#define GICR_ICPENDR0		(GICR_SGIBASE_OFFSET + U(0x280))
+#define GICR_ISACTIVER0		(GICR_SGIBASE_OFFSET + U(0x300))
+#define GICR_ICACTIVER0		(GICR_SGIBASE_OFFSET + U(0x380))
+#define GICR_IPRIORITYR		(GICR_SGIBASE_OFFSET + U(0x400))
+#define GICR_ICFGR0		(GICR_SGIBASE_OFFSET + U(0xc00))
+#define GICR_ICFGR1		(GICR_SGIBASE_OFFSET + U(0xc04))
+#define GICR_IGRPMODR0		(GICR_SGIBASE_OFFSET + U(0xd00))
+#define GICR_NSACR		(GICR_SGIBASE_OFFSET + U(0xe00))
 
 /* GICR_CTLR bit definitions */
 #define GICR_CTLR_UWP_SHIFT	31
-#define GICR_CTLR_UWP_MASK	0x1
-#define GICR_CTLR_UWP_BIT	(1U << GICR_CTLR_UWP_SHIFT)
+#define GICR_CTLR_UWP_MASK	U(0x1)
+#define GICR_CTLR_UWP_BIT	BIT_32(GICR_CTLR_UWP_SHIFT)
 #define GICR_CTLR_RWP_SHIFT	3
-#define GICR_CTLR_RWP_MASK	0x1
-#define GICR_CTLR_RWP_BIT	(1U << GICR_CTLR_RWP_SHIFT)
-#define GICR_CTLR_EN_LPIS_BIT	(1U << 0)
+#define GICR_CTLR_RWP_MASK	U(0x1)
+#define GICR_CTLR_RWP_BIT	BIT_32(GICR_CTLR_RWP_SHIFT)
+#define GICR_CTLR_EN_LPIS_BIT	BIT_32(0)
 
 /* GICR_WAKER bit definitions */
 #define WAKER_CA_SHIFT		2
 #define WAKER_PS_SHIFT		1
 
-#define WAKER_CA_MASK		0x1
-#define WAKER_PS_MASK		0x1
+#define WAKER_CA_MASK		U(0x1)
+#define WAKER_PS_MASK		U(0x1)
 
-#define WAKER_CA_BIT		(1 << WAKER_CA_SHIFT)
-#define WAKER_PS_BIT		(1 << WAKER_PS_SHIFT)
+#define WAKER_CA_BIT		BIT_32(WAKER_CA_SHIFT)
+#define WAKER_PS_BIT		BIT_32(WAKER_PS_SHIFT)
 
 /* GICR_TYPER bit definitions */
 #define TYPER_AFF_VAL_SHIFT	32
 #define TYPER_PROC_NUM_SHIFT	8
 #define TYPER_LAST_SHIFT	4
 
-#define TYPER_AFF_VAL_MASK	0xffffffff
-#define TYPER_PROC_NUM_MASK	0xffff
-#define TYPER_LAST_MASK		0x1
+#define TYPER_AFF_VAL_MASK	U(0xffffffff)
+#define TYPER_PROC_NUM_MASK	U(0xffff)
+#define TYPER_LAST_MASK		U(0x1)
 
-#define TYPER_LAST_BIT		(1 << TYPER_LAST_SHIFT)
+#define TYPER_LAST_BIT		BIT_32(TYPER_LAST_SHIFT)
 
 #define NUM_OF_REDIST_REGS	30
 
@@ -137,102 +137,120 @@
  * GICv3 CPU interface registers & constants
  ******************************************************************************/
 /* ICC_SRE bit definitions*/
-#define ICC_SRE_EN_BIT		(1 << 3)
-#define ICC_SRE_DIB_BIT		(1 << 2)
-#define ICC_SRE_DFB_BIT		(1 << 1)
-#define ICC_SRE_SRE_BIT		(1 << 0)
+#define ICC_SRE_EN_BIT		BIT_32(3)
+#define ICC_SRE_DIB_BIT		BIT_32(2)
+#define ICC_SRE_DFB_BIT		BIT_32(1)
+#define ICC_SRE_SRE_BIT		BIT_32(0)
 
 /* ICC_IGRPEN1_EL3 bit definitions */
 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT	0
 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT	1
 
-#define IGRPEN1_EL3_ENABLE_G1NS_BIT	(1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
-#define IGRPEN1_EL3_ENABLE_G1S_BIT	(1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)
+#define IGRPEN1_EL3_ENABLE_G1NS_BIT	BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
+#define IGRPEN1_EL3_ENABLE_G1S_BIT	BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
 
 /* ICC_IGRPEN0_EL1 bit definitions */
 #define IGRPEN1_EL1_ENABLE_G0_SHIFT	0
-#define IGRPEN1_EL1_ENABLE_G0_BIT	(1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)
+#define IGRPEN1_EL1_ENABLE_G0_BIT	BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
 
 /* ICC_HPPIR0_EL1 bit definitions */
 #define HPPIR0_EL1_INTID_SHIFT		0
-#define HPPIR0_EL1_INTID_MASK		0xffffff
+#define HPPIR0_EL1_INTID_MASK		U(0xffffff)
 
 /* ICC_HPPIR1_EL1 bit definitions */
 #define HPPIR1_EL1_INTID_SHIFT		0
-#define HPPIR1_EL1_INTID_MASK		0xffffff
+#define HPPIR1_EL1_INTID_MASK		U(0xffffff)
 
 /* ICC_IAR0_EL1 bit definitions */
 #define IAR0_EL1_INTID_SHIFT		0
-#define IAR0_EL1_INTID_MASK		0xffffff
+#define IAR0_EL1_INTID_MASK		U(0xffffff)
 
 /* ICC_IAR1_EL1 bit definitions */
 #define IAR1_EL1_INTID_SHIFT		0
-#define IAR1_EL1_INTID_MASK		0xffffff
+#define IAR1_EL1_INTID_MASK		U(0xffffff)
 
 /* ICC SGI macros */
-#define SGIR_TGT_MASK			0xffff
+#define SGIR_TGT_MASK			ULL(0xffff)
 #define SGIR_AFF1_SHIFT			16
 #define SGIR_INTID_SHIFT		24
-#define SGIR_INTID_MASK			0xf
+#define SGIR_INTID_MASK			ULL(0xf)
 #define SGIR_AFF2_SHIFT			32
 #define SGIR_IRM_SHIFT			40
-#define SGIR_IRM_MASK			0x1
+#define SGIR_IRM_MASK			ULL(0x1)
 #define SGIR_AFF3_SHIFT			48
-#define SGIR_AFF_MASK			0xf
+#define SGIR_AFF_MASK			ULL(0xf)
 
-#define SGIR_IRM_TO_AFF			0
+#define SGIR_IRM_TO_AFF			U(0)
 
-#define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \
-	((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
-	 (((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
-	 (((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
-	 (((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
-	 (((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
-	 ((tgt) & SGIR_TGT_MASK))
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt)	\
+	((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) |	\
+	 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) |	\
+	 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) |	\
+	 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) |		\
+	 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) |		\
+	 ((_tgt) & SGIR_TGT_MASK))
 
 /*****************************************************************************
  * GICv3 ITS registers and constants
  *****************************************************************************/
 
-#define GITS_CTLR			0x0
-#define GITS_IIDR			0x4
-#define GITS_TYPER			0x8
-#define GITS_CBASER			0x80
-#define GITS_CWRITER			0x88
-#define GITS_CREADR			0x90
-#define GITS_BASER			0x100
+#define GITS_CTLR			U(0x0)
+#define GITS_IIDR			U(0x4)
+#define GITS_TYPER			U(0x8)
+#define GITS_CBASER			U(0x80)
+#define GITS_CWRITER			U(0x88)
+#define GITS_CREADR			U(0x90)
+#define GITS_BASER			U(0x100)
 
 /* GITS_CTLR bit definitions */
-#define GITS_CTLR_ENABLED_BIT		1
+#define GITS_CTLR_ENABLED_BIT		BIT_32(0)
 #define GITS_CTLR_QUIESCENT_SHIFT	31
-#define GITS_CTLR_QUIESCENT_BIT		(1U << GITS_CTLR_QUIESCENT_SHIFT)
+#define GITS_CTLR_QUIESCENT_BIT		BIT_32(GITS_CTLR_QUIESCENT_SHIFT)
 
 #ifndef __ASSEMBLY__
 
+#include <arch_helpers.h>
 #include <gic_common.h>
 #include <interrupt_props.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <utils_def.h>
 
-#define gicv3_is_intr_id_special_identifier(id)	\
-	(((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
+static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
+{
+	return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
+}
 
 /*******************************************************************************
  * Helper GICv3 macros for SEL1
  ******************************************************************************/
-#define gicv3_acknowledge_interrupt_sel1()	read_icc_iar1_el1() &\
-							IAR1_EL1_INTID_MASK
-#define gicv3_get_pending_interrupt_id_sel1()	read_icc_hppir1_el1() &\
-							HPPIR1_EL1_INTID_MASK
-#define gicv3_end_of_interrupt_sel1(id)		write_icc_eoir1_el1(id)
+static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
+{
+	return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
+}
 
+static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
+{
+	return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
+}
+
+static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
+{
+	write_icc_eoir1_el1(id);
+}
 
 /*******************************************************************************
  * Helper GICv3 macros for EL3
  ******************************************************************************/
-#define gicv3_acknowledge_interrupt()		read_icc_iar0_el1() &\
-							IAR0_EL1_INTID_MASK
-#define gicv3_end_of_interrupt(id)		write_icc_eoir0_el1(id)
+static inline uint32_t gicv3_acknowledge_interrupt(void)
+{
+	return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
+}
+
+static inline void gicv3_end_of_interrupt(unsigned int id)
+{
+	return write_icc_eoir0_el1(id);
+}
 
 /*
  * This macro returns the total number of GICD registers corresponding to
@@ -245,7 +263,7 @@
 	DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT))
 
 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
-#define INT_ID_MASK	0xffffff
+#define INT_ID_MASK	U(0xffffff)
 
 /*******************************************************************************
  * This structure describes some of the implementation defined attributes of the
@@ -402,7 +420,7 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
 		unsigned int priority);
 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
 		unsigned int type);
-void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target);
+void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target);
 void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
 		u_register_t mpidr);
 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);

include/plat/arm/common/arm_def.h

@@ -186,25 +186,25 @@
  * as Group 0 interrupts.
  */
 #define ARM_G1S_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE)
 
 #define ARM_G0_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_EDGE)
 
 #define ARM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\

plat/common/plat_gicv2.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <gicv2.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
+#include <stdbool.h>
 
 /*
  * The following platform GIC functions are weakly defined. They
@@ -101,7 +102,7 @@ uint32_t plat_ic_get_interrupt_type(uint32_t id)
 	type = gicv2_get_interrupt_group(id);
 
 	/* Assume that all secure interrupts are S-EL1 interrupts */
-	return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS :
+	return (type == GICV2_INTR_GROUP1) ? INTR_TYPE_NS :
 #if GICV2_G0_FOR_EL3
 		INTR_TYPE_EL3;
 #else
@@ -130,9 +131,8 @@ void plat_ic_end_of_interrupt(uint32_t id)
 uint32_t plat_interrupt_type_to_line(uint32_t type,
 				uint32_t security_state)
 {
-	assert(type == INTR_TYPE_S_EL1 ||
-		       type == INTR_TYPE_EL3 ||
-		       type == INTR_TYPE_NS);
+	assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
+	       (type == INTR_TYPE_NS));
 
 	assert(sec_state_is_valid(security_state));
 
@@ -144,8 +144,8 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
 	 * Secure interrupts are signaled using the IRQ line if the FIQ is
 	 * not enabled else they are signaled using the FIQ line.
 	 */
-	return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) :
-						__builtin_ctz(SCR_IRQ_BIT));
+	return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) :
+						 __builtin_ctz(SCR_IRQ_BIT));
 }
 
 unsigned int plat_ic_get_running_priority(void)
@@ -211,7 +211,7 @@ int plat_ic_has_interrupt_type(unsigned int type)
 
 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
 {
-	int gicv2_type = 0;
+	unsigned int gicv2_type = 0U;
 
 	/* Map canonical interrupt type to GICv2 type */
 	switch (type) {
@@ -226,7 +226,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
 		gicv2_type = GICV2_INTR_GROUP1;
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 
@@ -247,7 +247,7 @@ void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
 
 	gicv2_raise_sgi(sgi_num, id);
 #else
-	assert(0);
+	assert(false);
 #endif
 }
 
@@ -266,7 +266,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
 		proc_num = -1;
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 

plat/common/plat_gicv3.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #include <gicv3.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
+#include <stdbool.h>
 
 #ifdef IMAGE_BL31
 
@@ -54,7 +55,7 @@ uint32_t plat_ic_get_pending_interrupt_id(void)
 
 	assert(IS_IN_EL3());
 	irqnr = gicv3_get_pending_interrupt_id();
-	return (gicv3_is_intr_id_special_identifier(irqnr)) ?
+	return gicv3_is_intr_id_special_identifier(irqnr) ?
 				INTR_ID_UNAVAILABLE : irqnr;
 }
 
@@ -73,20 +74,27 @@ uint32_t plat_ic_get_pending_interrupt_id(void)
 uint32_t plat_ic_get_pending_interrupt_type(void)
 {
 	unsigned int irqnr;
+	uint32_t type;
 
 	assert(IS_IN_EL3());
 	irqnr = gicv3_get_pending_interrupt_type();
 
 	switch (irqnr) {
 	case PENDING_G1S_INTID:
-		return INTR_TYPE_S_EL1;
+		type = INTR_TYPE_S_EL1;
+		break;
 	case PENDING_G1NS_INTID:
-		return INTR_TYPE_NS;
+		type = INTR_TYPE_NS;
+		break;
 	case GIC_SPURIOUS_INTERRUPT:
-		return INTR_TYPE_INVAL;
+		type = INTR_TYPE_INVAL;
+		break;
 	default:
-		return INTR_TYPE_EL3;
+		type = INTR_TYPE_EL3;
+		break;
 	}
+
+	return type;
 }
 
 /*
@@ -132,9 +140,9 @@ void plat_ic_end_of_interrupt(uint32_t id)
 uint32_t plat_interrupt_type_to_line(uint32_t type,
 				uint32_t security_state)
 {
-	assert(type == INTR_TYPE_S_EL1 ||
-	       type == INTR_TYPE_EL3 ||
-	       type == INTR_TYPE_NS);
+	assert((type == INTR_TYPE_S_EL1) ||
+	       (type == INTR_TYPE_EL3) ||
+	       (type == INTR_TYPE_NS));
 
 	assert(sec_state_is_valid(security_state));
 	assert(IS_IN_EL3());
@@ -227,9 +235,10 @@ void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
 	assert(plat_core_pos_by_mpidr(target) >= 0);
 
 	/* Verify that this is a secure EL3 SGI */
-	assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3);
+	assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) ==
+					  INTR_TYPE_EL3);
 
-	gicv3_raise_secure_g0_sgi(sgi_num, target);
+	gicv3_raise_secure_g0_sgi((unsigned int)sgi_num, target);
 }
 
 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
@@ -246,7 +255,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
 		irm = GICV3_IRM_ANY;
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 
@@ -274,10 +283,10 @@ unsigned int plat_ic_set_priority_mask(unsigned int mask)
 
 unsigned int plat_ic_get_interrupt_id(unsigned int raw)
 {
-	unsigned int id = (raw & INT_ID_MASK);
+	unsigned int id = raw & INT_ID_MASK;
 
-	return (gicv3_is_intr_id_special_identifier(id) ?
-			INTR_ID_UNAVAILABLE : id);
+	return gicv3_is_intr_id_special_identifier(id) ?
+			INTR_ID_UNAVAILABLE : id;
 }
 #endif
 #ifdef IMAGE_BL32