Update mediatek platform to not rely on undefined overflow behaviour

This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

plat/mediatek/mt8183/drivers/mcsi/mcsi.h

@@ -41,7 +41,7 @@
 #define BD_CTRL_REG			0x40
 
 /* Snoop Control register bit definitions */
-#define DVM_SUPPORT			(1 << 31)
+#define DVM_SUPPORT			(1U << 31)
 #define SNP_SUPPORT			(1 << 30)
 #define SHAREABLE_OVWRT			(1 << 2)
 #define DVM_EN_BIT			(1 << 1)

plat/mediatek/mt8183/include/mcucfg.h

@@ -197,7 +197,7 @@ enum {
 	MP0_CPUCFG_64BIT_SHIFT = 12,
 	MP1_CPUCFG_64BIT_SHIFT = 28,
 	MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
-	MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
+	MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
 };
 
 /* scu related */

plat/mediatek/mt8183/include/platform_def.h

@@ -180,7 +180,7 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
 #define MTK_WDT_STATUS_SECURITY_RST         (1 << 28)
 #define MTK_WDT_STATUS_IRQ_ASSERT           (1 << 29)
 #define MTK_WDT_STATUS_SW_WDT_RST           (1 << 30)
-#define MTK_WDT_STATUS_HW_WDT_RST           (1 << 31)
+#define MTK_WDT_STATUS_HW_WDT_RST           (1U << 31)
 
 /* RGU other related */
 #define MTK_WDT_MODE_DUAL_MODE    0x0040