plat: fix switch statements to comply with MISRA rules

Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.

Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>

plat/arm/board/fvp/fvp_pm.c

@@ -324,13 +324,11 @@ static int fvp_node_hw_state(u_register_t target_cpu,
 	if (psysr == PSYSR_INVALID)
 		return PSCI_E_INVALID_PARAMS;
 
-	switch (power_level) {
-	case ARM_PWR_LVL0:
+	if (power_level == ARM_PWR_LVL0) {
 		ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
-		break;
-	case ARM_PWR_LVL1:
+	} else {
+		/* power_level == ARM_PWR_LVL1 */
 		ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
-		break;
 	}
 
 	return ret;

plat/arm/common/arm_bl2_setup.c

@@ -305,6 +305,9 @@ int arm_bl2_handle_post_image_load(unsigned int image_id)
 		}
 		break;
 #endif
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/common/plat_gicv2.c

@@ -190,6 +190,8 @@ void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
 
 int plat_ic_has_interrupt_type(unsigned int type)
 {
+	int has_interrupt_type = 0;
+
 	switch (type) {
 #if GICV2_G0_FOR_EL3
 	case INTR_TYPE_EL3:
@@ -197,10 +199,14 @@ int plat_ic_has_interrupt_type(unsigned int type)
 	case INTR_TYPE_S_EL1:
 #endif
 	case INTR_TYPE_NS:
-		return 1;
+		has_interrupt_type = 1;
+		break;
 	default:
-		return 0;
+		/* Do nothing in default case */
+		break;
 	}
+
+	return has_interrupt_type;
 }
 
 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
@@ -221,6 +227,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
 		break;
 	default:
 		assert(0);
+		break;
 	}
 
 	gicv2_set_interrupt_type(id, gicv2_type);
@@ -260,6 +267,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
 		break;
 	default:
 		assert(0);
+		break;
 	}
 
 	gicv2_set_spi_routing(id, proc_num);

plat/common/plat_gicv3.c

@@ -247,6 +247,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
 		break;
 	default:
 		assert(0);
+		break;
 	}
 
 	gicv3_set_spi_routing(id, irm, mpidr);

plat/hisilicon/hikey/hikey_bl2_setup.c

@@ -175,6 +175,9 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id)
 		}
 		break;
 #endif
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/hisilicon/hikey960/hikey960_bl2_setup.c

@@ -267,6 +267,9 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id)
 		}
 		break;
 #endif
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/hisilicon/poplar/bl2_plat_setup.c

@@ -193,6 +193,9 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id)
 		}
 		break;
 #endif
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/mediatek/common/custom/oem_svc.c

@@ -41,15 +41,8 @@ uint64_t oem_smc_handler(uint32_t smc_fid,
 			void *handle,
 			uint64_t flags)
 {
-	uint64_t rc;
-
-	switch (smc_fid) {
-	default:
-		rc = SMC_UNK;
-		WARN("Unimplemented OEM Call: 0x%x\n", smc_fid);
-	}
-
-	SMC_RET1(handle, rc);
+	WARN("Unimplemented OEM Call: 0x%x\n", smc_fid);
+	SMC_RET1(handle, SMC_UNK);
 }
 
 /*

plat/mediatek/common/mtk_sip_svc.c

@@ -71,6 +71,9 @@ uint64_t mediatek_sip_handler(uint32_t smc_fid,
 			boot_to_kernel(x1, x2, x3, x4);
 			SMC_RET0(handle);
 #endif
+		default:
+			/* Do nothing in default case */
+			break;
 		}
 	}
 

plat/qemu/qemu_bl2_setup.c

@@ -287,6 +287,9 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id)
 		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
 		bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/rockchip/common/rockchip_sip_svc.c

@@ -59,13 +59,11 @@ uint64_t sip_smc_handler(uint32_t smc_fid,
 	case SIP_SVC_UID:
 		/* Return UID to the caller */
 		SMC_UUID_RET(handle, rk_sip_svc_uid);
-		break;
 
 	case SIP_SVC_VERSION:
 		/* Return the version of current implementation */
 		SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR,
 			RK_SIP_SVC_VERSION_MINOR);
-		break;
 
 	default:
 		return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4,

plat/rockchip/rk3368/plat_sip_calls.c

@@ -19,9 +19,6 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
 				   void *handle,
 				   uint64_t flags)
 {
-	switch (smc_fid) {
-	default:
-		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
-		SMC_RET1(handle, SMC_UNK);
-	}
+	ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+	SMC_RET1(handle, SMC_UNK);
 }

plat/rockchip/rk3399/drivers/dram/dfs.c

@@ -207,6 +207,9 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config,
 		ptiming_config->rdbi = 0;
 		ptiming_config->wdbi = 0;
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 	ptiming_config->dramds = drv_config->dram_side_drv;
 	ptiming_config->dramodt = drv_config->dram_side_dq_odt;

plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c

@@ -1314,5 +1314,8 @@ void dram_get_parameter(struct timing_related_config *timing_config,
 	case LPDDR4:
 		lpddr4_get_parameter(timing_config, pdram_timing);
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 }

plat/rockchip/rk3399/drivers/pmu/pmu.c

@@ -310,6 +310,7 @@ static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state)
 		pmu_bus_idle_req(BUS_ID_PERIHP, state);
 		break;
 	default:
+		/* Do nothing in default case */
 		break;
 	}
 
@@ -647,12 +648,8 @@ int rockchip_soc_cores_pwr_dm_off(void)
 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
 				 plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_suspend(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -675,12 +672,8 @@ int rockchip_soc_cores_pwr_dm_suspend(void)
 
 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_suspend(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -698,12 +691,8 @@ int rockchip_soc_cores_pwr_dm_on_finish(void)
 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
 				       plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_resume(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -721,11 +710,8 @@ int rockchip_soc_cores_pwr_dm_resume(void)
 
 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_resume(lvl_state);
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;

plat/rpi3/rpi3_bl2_setup.c

@@ -83,6 +83,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 		bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
 		break;
 
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return err;

plat/socionext/uniphier/uniphier_bl2_setup.c

@@ -85,6 +85,7 @@ void bl2_el3_plat_arch_setup(void)
 		break;
 	default:
 		plat_error_handler(-ENOTSUP);
+		break;
 	}
 
 	if (!skip_scp) {

plat/xilinx/zynqmp/aarch64/zynqmp_common.c

@@ -48,6 +48,9 @@ unsigned int zynqmp_get_uart_clk(void)
 		return 25000000;
 	case ZYNQMP_CSU_VERSION_QEMU:
 		return 133000000;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return 100000000;
@@ -187,6 +190,9 @@ static void zynqmp_print_platform_name(void)
 	case ZYNQMP_CSU_VERSION_SILICON:
 		label = "silicon";
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x%s\n",
@@ -258,6 +264,9 @@ unsigned int plat_get_syscnt_freq2(void)
 		return 4000000;
 	case ZYNQMP_CSU_VERSION_QEMU:
 		return 50000000;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 
 	return mmio_read_32(IOU_SCNTRS_BASEFREQ);