rcar_gen3: drivers: staging

 - ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.

drivers/staging/renesas/rcar/ddr/boot_init_dram.h

+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	__BOOT_INIT_DRAM_
+#define	__BOOT_INIT_DRAM_
+
+extern int32_t rcar_dram_init(void);
+
+#define INITDRAM_OK (0)
+#define INITDRAM_NG (0xffffffff)
+#define INITDRAM_ERR_I (0xffffffff)
+#define INITDRAM_ERR_O (0xfffffffe)
+#define INITDRAM_ERR_T (0xfffffff0)
+
+#endif

drivers/staging/renesas/rcar/ddr/ddr.mk

+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else
+    include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
+endif
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c

drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h

+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef BOOT_INIT_DRAM_REGDEF_E3_H_
+#define BOOT_INIT_DRAM_REGDEF_E3_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif				/* __cplusplus */
+
+#define				BIT0						0x00000001U
+#define				BIT11						0x00000800U
+#define				BIT30						0x40000000U
+
+/* DBSC registers */
+
+#define				DBSC_E3_DBSYSCONF1         0xE6790004U
+#define				DBSC_E3_DBPHYCONF0         0xE6790010U
+#define				DBSC_E3_DBKIND             0xE6790020U
+#define				DBSC_E3_DBMEMCONF00        0xE6790030U
+#define				DBSC_E3_DBSYSCNT0          0xE6790100U
+#define				DBSC_E3_DBACEN             0xE6790200U
+#define				DBSC_E3_DBRFEN             0xE6790204U
+#define				DBSC_E3_DBCMD              0xE6790208U
+#define				DBSC_E3_DBWAIT             0xE6790210U
+#define				DBSC_E3_DBTR0              0xE6790300U
+#define				DBSC_E3_DBTR1              0xE6790304U
+#define				DBSC_E3_DBTR2              0xE6790308U
+#define				DBSC_E3_DBTR3              0xE679030CU
+#define				DBSC_E3_DBTR4              0xE6790310U
+#define				DBSC_E3_DBTR5              0xE6790314U
+#define				DBSC_E3_DBTR6              0xE6790318U
+#define				DBSC_E3_DBTR7              0xE679031CU
+#define				DBSC_E3_DBTR8              0xE6790320U
+#define				DBSC_E3_DBTR9              0xE6790324U
+#define				DBSC_E3_DBTR10             0xE6790328U
+#define				DBSC_E3_DBTR11             0xE679032CU
+#define				DBSC_E3_DBTR12             0xE6790330U
+#define				DBSC_E3_DBTR13             0xE6790334U
+#define				DBSC_E3_DBTR14             0xE6790338U
+#define				DBSC_E3_DBTR15             0xE679033CU
+#define				DBSC_E3_DBTR16             0xE6790340U
+#define				DBSC_E3_DBTR17             0xE6790344U
+#define				DBSC_E3_DBTR18             0xE6790348U
+#define				DBSC_E3_DBTR19             0xE679034CU
+#define				DBSC_E3_DBTR20             0xE6790350U
+#define				DBSC_E3_DBTR21             0xE6790354U
+#define				DBSC_E3_DBBL               0xE6790400U
+#define				DBSC_E3_DBRFCNF1           0xE6790414U
+#define				DBSC_E3_DBRFCNF2           0xE6790418U
+#define				DBSC_E3_DBCALCNF           0xE6790424U
+#define				DBSC_E3_DBODT0             0xE6790460U
+#define				DBSC_E3_DBADJ0             0xE6790500U
+#define				DBSC_E3_DBDFICUPDCNF       0xE679052CU
+#define				DBSC_E3_DBDFICNT0          0xE6790604U
+#define				DBSC_E3_DBPDLK0            0xE6790620U
+#define				DBSC_E3_DBPDRGA0           0xE6790624U
+#define				DBSC_E3_DBPDRGD0           0xE6790628U
+#define				DBSC_E3_DBBUS0CNF1         0xE6790804U
+#define				DBSC_E3_DBCAM0CNF1         0xE6790904U
+#define				DBSC_E3_DBCAM0CNF2         0xE6790908U
+#define				DBSC_E3_DBCAM0STAT0        0xE6790980U
+#define				DBSC_E3_DBBCAMDIS          0xE67909FCU
+#define				DBSC_E3_DBSCHCNT0          0xE6791000U
+#define				DBSC_E3_DBSCHSZ0           0xE6791010U
+#define				DBSC_E3_DBSCHRW0           0xE6791020U
+#define				DBSC_E3_DBSCHRW1           0xE6791024U
+#define				DBSC_E3_DBSCHQOS00         0xE6791030U
+#define				DBSC_E3_DBSCHQOS01         0xE6791034U
+#define				DBSC_E3_DBSCHQOS02         0xE6791038U
+#define				DBSC_E3_DBSCHQOS03         0xE679103CU
+#define				DBSC_E3_DBSCHQOS40         0xE6791070U
+#define				DBSC_E3_DBSCHQOS41         0xE6791074U
+#define				DBSC_E3_DBSCHQOS42         0xE6791078U
+#define				DBSC_E3_DBSCHQOS43         0xE679107CU
+#define				DBSC_E3_DBSCHQOS90         0xE67910C0U
+#define				DBSC_E3_DBSCHQOS91         0xE67910C4U
+#define				DBSC_E3_DBSCHQOS92         0xE67910C8U
+#define				DBSC_E3_DBSCHQOS93         0xE67910CCU
+#define				DBSC_E3_DBSCHQOS130        0xE6791100U
+#define				DBSC_E3_DBSCHQOS131        0xE6791104U
+#define				DBSC_E3_DBSCHQOS132        0xE6791108U
+#define				DBSC_E3_DBSCHQOS133        0xE679110CU
+#define				DBSC_E3_DBSCHQOS140        0xE6791110U
+#define				DBSC_E3_DBSCHQOS141        0xE6791114U
+#define				DBSC_E3_DBSCHQOS142        0xE6791118U
+#define				DBSC_E3_DBSCHQOS143        0xE679111CU
+#define				DBSC_E3_DBSCHQOS150        0xE6791120U
+#define				DBSC_E3_DBSCHQOS151        0xE6791124U
+#define				DBSC_E3_DBSCHQOS152        0xE6791128U
+#define				DBSC_E3_DBSCHQOS153        0xE679112CU
+#define				DBSC_E3_SCFCTST0           0xE6791700U
+#define				DBSC_E3_SCFCTST1           0xE6791708U
+#define				DBSC_E3_SCFCTST2           0xE679170CU
+
+/* CPG registers */
+
+#define				CPG_SRCR4                  0xE61500BCU
+#define				CPG_PLLECR                 0xE61500D0U
+#define				CPG_CPGWPR                 0xE6150900U
+#define				CPG_CPGWPCR                0xE6150904U
+#define				CPG_SRSTCLR4               0xE6150950U
+
+/* MODE Monitor registers */
+
+#define				RST_MODEMR                 0xE6160060U
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* BOOT_INIT_DRAM_REGDEF_E3_H_ */

drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk

+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c

drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h

+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#pragma once
+#include <stdint.h>
+
+#ifndef	__DDR_INIT_E3_
+#define	__DDR_INIT_E3_
+
+#define RCAR_E3_DDR_VERSION    "rev.0.09"
+
+#ifdef ddr_qos_init_setting
+   #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */
+#else
+   #if RCAR_REF_INT == 0
+      #define REFRESH_RATE  3900
+   #elif RCAR_REF_INT == 1
+      #define REFRESH_RATE  7800
+   #else
+      #define REFRESH_RATE  3900
+   #endif
+#endif
+
+extern int32_t InitDram(void);
+#define INITDRAM_OK (0)
+#define INITDRAM_NG (0xffffffff)
+#define INITDRAM_ERR_I (0xffffffff)
+#define INITDRAM_ERR_O (0xfffffffe)
+#define INITDRAM_ERR_T (0xfffffff0)
+
+#endif /* __DDR_INIT_E3_ */

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h

+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RCAR_DDR_VERSION        "rev.0.33"
+#define DRAM_CH_CNT		(0x04)
+#define SLICE_CNT		(0x04)
+#define CS_CNT			(0x02)
+
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT		(CS_CNT * 2)
+
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT		(DRAM_CH_CNT * 2)
+
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+
+/* for ddr deisity setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw) 	\
+	((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+
+#define DBMEMCONF_REGD(density) 		\
+(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
+
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+
+/* refresh mode */
+#define DBSC_REFINTS		(0x0)
+
+/* system registers */
+#define CPG_BASE		(0xE6150000U)
+#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
+
+#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
+#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
+#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
+#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
+
+#define CPG_FRQCRB_KICK_BIT	(1U<<31)
+#define CPG_PLLECR_PLL3E_BIT	(1U<<3)
+#define CPG_PLLECR_PLL3ST_BIT	(1U<<11)
+#define CPG_ZB3CKCR_ZB3ST_BIT	(1U<<11)
+
+#define RST_BASE		(0xE6160000U)
+#define RST_MODEMR		(RST_BASE + 0x0060U)
+
+#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
+
+/* Product Register */
+#define PRR			(0xFFF00044U)
+#define PRR_PRODUCT_MASK	(0x00007F00U)
+#define PRR_CUT_MASK		(0x000000FFU)
+#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3   */
+#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3-W */
+#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3-N */
+#define PRR_PRODUCT_V3H		(0x00005600U)	/* R-Car V3H  */
+#define PRR_PRODUCT_10		(0x00U)	/*   Ver.1.0  */
+#define PRR_PRODUCT_11		(0x01U)	/*   Ver.1.1  */
+#define PRR_PRODUCT_20		(0x10U)	/*   Ver.2.0  */
+#define PRR_PRODUCT_30		(0x20U)	/*   Ver.3.0  */
+
+/* DBSC registers */
+#define DBSC_DBSYSCONF1		0xE6790004U
+#define DBSC_DBPHYCONF0		0xE6790010U
+#define DBSC_DBKIND		0xE6790020U
+
+#define DBSC_DBMEMCONF(ch, cs)	(0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
+#define DBSC_DBMEMCONF_0_0	0xE6790030U
+#define DBSC_DBMEMCONF_0_1	0xE6790034U
+#define DBSC_DBMEMCONF_0_2	0xE6790038U
+#define DBSC_DBMEMCONF_0_3	0xE679003CU
+#define DBSC_DBMEMCONF_1_2	0xE6790048U
+#define DBSC_DBMEMCONF_1_3	0xE679004CU
+#define DBSC_DBMEMCONF_1_0	0xE6790040U
+#define DBSC_DBMEMCONF_1_1	0xE6790044U
+#define DBSC_DBMEMCONF_2_0	0xE6790050U
+#define DBSC_DBMEMCONF_2_1	0xE6790054U
+#define DBSC_DBMEMCONF_2_2	0xE6790058U
+#define DBSC_DBMEMCONF_2_3	0xE679005CU
+#define DBSC_DBMEMCONF_3_0	0xE6790060U
+#define DBSC_DBMEMCONF_3_1	0xE6790064U
+#define DBSC_DBMEMCONF_3_2	0xE6790068U
+#define DBSC_DBMEMCONF_3_3	0xE679006CU
+
+#define DBSC_DBSYSCNT0		0xE6790100U
+
+#define DBSC_DBACEN		0xE6790200U
+#define DBSC_DBRFEN		0xE6790204U
+#define DBSC_DBCMD		0xE6790208U
+#define DBSC_DBWAIT		0xE6790210U
+#define DBSC_DBSYSCTRL0		0xE6790280U
+
+#define DBSC_DBTR(x)		(0xE6790300U + 0x04U * (x))
+#define DBSC_DBTR0		0xE6790300U
+#define DBSC_DBTR1		0xE6790304U
+#define DBSC_DBTR3		0xE679030CU
+#define DBSC_DBTR4		0xE6790310U
+#define DBSC_DBTR5		0xE6790314U
+#define DBSC_DBTR6		0xE6790318U
+#define DBSC_DBTR7		0xE679031CU
+#define DBSC_DBTR8		0xE6790320U
+#define DBSC_DBTR9		0xE6790324U
+#define DBSC_DBTR10		0xE6790328U
+#define DBSC_DBTR11		0xE679032CU
+#define DBSC_DBTR12		0xE6790330U
+#define DBSC_DBTR13		0xE6790334U
+#define DBSC_DBTR14		0xE6790338U
+#define DBSC_DBTR15		0xE679033CU
+#define DBSC_DBTR16		0xE6790340U
+#define DBSC_DBTR17		0xE6790344U
+#define DBSC_DBTR18		0xE6790348U
+#define DBSC_DBTR19		0xE679034CU
+#define DBSC_DBTR20		0xE6790350U
+#define DBSC_DBTR21		0xE6790354U
+#define DBSC_DBTR22		0xE6790358U
+#define DBSC_DBTR23		0xE679035CU
+#define DBSC_DBTR24		0xE6790360U
+#define DBSC_DBTR25		0xE6790364U
+#define DBSC_DBTR26		0xE6790368U
+
+#define DBSC_DBBL		0xE6790400U
+#define DBSC_DBRFCNF1		0xE6790414U
+#define DBSC_DBRFCNF2		0xE6790418U
+#define DBSC_DBTSPCNF		0xE6790420U
+#define DBSC_DBCALCNF		0xE6790424U
+#define DBSC_DBRNK(x)		(0xE6790430U + 0x04U * (x))
+#define DBSC_DBRNK2		0xE6790438U
+#define DBSC_DBRNK3		0xE679043CU
+#define DBSC_DBRNK4		0xE6790440U
+#define DBSC_DBRNK5		0xE6790444U
+#define DBSC_DBODT(x)		(0xE6790460U + 0x04U * (x))
+
+#define DBSC_DBADJ0		0xE6790500U
+#define DBSC_DBDBICNT		0xE6790518U
+#define DBSC_DBDFIPMSTRCNF	0xE6790520U
+#define DBSC_DBDFICUPDCNF	0xE679052CU
+
+#define DBSC_INITCOMP(ch)	(0xE6790600U + 0x40U * (ch))
+#define DBSC_INITCOMP_0		0xE6790600U
+#define DBSC_INITCOMP_1		0xE6790640U
+#define DBSC_INITCOMP_2		0xE6790680U
+#define DBSC_INITCOMP_3		0xE67906C0U
+
+#define DBSC_DBDFICNT(ch)	(0xE6790604U + 0x40U * (ch))
+#define DBSC_DBDFICNT_0		0xE6790604U
+#define DBSC_DBDFICNT_1		0xE6790644U
+#define DBSC_DBDFICNT_2		0xE6790684U
+#define DBSC_DBDFICNT_3		0xE67906C4U
+
+#define DBSC_DBPDCNT0(ch)	(0xE6790610U + 0x40U * (ch))
+#define DBSC_DBPDCNT0_0		0xE6790610U
+#define DBSC_DBPDCNT0_1		0xE6790650U
+#define DBSC_DBPDCNT0_2		0xE6790690U
+#define DBSC_DBPDCNT0_3		0xE67906D0U
+
+#define DBSC_DBPDCNT1(ch)	(0xE6790614U + 0x40U * (ch))
+#define DBSC_DBPDCNT1_0		0xE6790614U
+#define DBSC_DBPDCNT1_1		0xE6790654U
+#define DBSC_DBPDCNT1_2		0xE6790694U
+#define DBSC_DBPDCNT1_3		0xE67906D4U
+
+#define DBSC_DBPDCNT2(ch)	(0xE6790618U + 0x40U * (ch))
+#define DBSC_DBPDCNT2_0		0xE6790618U
+#define DBSC_DBPDCNT2_1		0xE6790658U
+#define DBSC_DBPDCNT2_2		0xE6790698U
+#define DBSC_DBPDCNT2_3		0xE67906D8U
+
+#define DBSC_DBPDCNT3(ch)	(0xE679061CU + 0x40U * (ch))
+#define DBSC_DBPDCNT3_0		0xE679061CU
+#define DBSC_DBPDCNT3_1		0xE679065CU
+#define DBSC_DBPDCNT3_2		0xE679069CU
+#define DBSC_DBPDCNT3_3		0xE67906DCU
+
+#define DBSC_DBPDLK(ch)		(0xE6790620U + 0x40U * (ch))
+#define DBSC_DBPDLK_0		0xE6790620U
+#define DBSC_DBPDLK_1		0xE6790660U
+#define DBSC_DBPDLK_2		0xE67906a0U
+#define DBSC_DBPDLK_3		0xE67906e0U
+
+#define DBSC_DBPDRGA(ch)	(0xE6790624U + 0x40U * (ch))
+#define DBSC_DBPDRGD(ch)	(0xE6790628U + 0x40U * (ch))
+#define DBSC_DBPDRGA_0		0xE6790624U
+#define DBSC_DBPDRGD_0		0xE6790628U
+#define DBSC_DBPDRGA_1		0xE6790664U
+#define DBSC_DBPDRGD_1		0xE6790668U
+#define DBSC_DBPDRGA_2		0xE67906A4U
+#define DBSC_DBPDRGD_2		0xE67906A8U
+#define DBSC_DBPDRGA_3		0xE67906E4U
+#define DBSC_DBPDRGD_3		0xE67906E8U
+
+#define DBSC_DBPDSTAT(ch)	(0xE6790630U + 0x40U * (ch))
+#define DBSC_DBPDSTAT_0		0xE6790630U
+#define DBSC_DBPDSTAT_1		0xE6790670U
+#define DBSC_DBPDSTAT_2		0xE67906B0U
+#define DBSC_DBPDSTAT_3		0xE67906F0U
+
+#define DBSC_DBBUS0CNF0		0xE6790800U
+#define DBSC_DBBUS0CNF1		0xE6790804U
+
+#define DBSC_DBCAM0CNF1		0xE6790904U
+#define DBSC_DBCAM0CNF2		0xE6790908U
+#define DBSC_DBCAM0CNF3		0xE679090CU
+#define DBSC_DBBSWAP		0xE67909F0U
+#define DBSC_DBBCAMDIS		0xE67909FCU
+#define DBSC_DBSCHCNT0		0xE6791000U
+#define DBSC_DBSCHCNT1		0xE6791004U
+#define DBSC_DBSCHSZ0		0xE6791010U
+#define DBSC_DBSCHRW0		0xE6791020U
+#define DBSC_DBSCHRW1		0xE6791024U
+
+#define DBSC_DBSCHQOS_0(x)	(0xE6791030U +0x10U * (x))
+#define DBSC_DBSCHQOS_1(x)	(0xE6791034U +0x10U * (x))
+#define DBSC_DBSCHQOS_2(x)	(0xE6791038U +0x10U * (x))
+#define DBSC_DBSCHQOS_3(x)	(0xE679103CU +0x10U * (x))
+
+#define DBSC_DBSCTR0		0xE6791700U
+#define DBSC_DBSCTR1		0xE6791708U
+#define DBSC_DBSCHRW2		0xE679170CU
+
+#define DBSC_SCFCTST01(x)	(0xE6791700U + 0x08U * (x))
+#define DBSC_SCFCTST0		0xE6791700U
+#define DBSC_SCFCTST1		0xE6791708U
+#define DBSC_SCFCTST2		0xE679170CU
+
+#define DBSC_DBMRRDR(chab)	(0xE6791800U + 0x04U * (chab))
+#define DBSC_DBMRRDR_0		0xE6791800U
+#define DBSC_DBMRRDR_1		0xE6791804U
+#define DBSC_DBMRRDR_2		0xE6791808U
+#define DBSC_DBMRRDR_3		0xE679180CU
+#define DBSC_DBMRRDR_4		0xE6791810U
+#define DBSC_DBMRRDR_5		0xE6791814U
+#define DBSC_DBMRRDR_6		0xE6791818U
+#define DBSC_DBMRRDR_7		0xE679181CU
+
+#define DBSC_DBMEMSWAPCONF0	0xE6792000U
+
+#define DBSC_DBMONCONF4		0xE6793010U
+
+#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0		0xE6794054U
+#define DBSC_PLL_LOCK_1		0xE6794154U
+#define DBSC_PLL_LOCK_2		0xE6794254U
+#define DBSC_PLL_LOCK_3		0xE6794354U
+
+/* STAT registers */
+#define MSTAT_SL_INIT		0xE67E8000U
+#define MSTAT_REF_ARS		0xE67E8004U
+#define MSTATQ_STATQC		0xE67E8008U
+#define MSTATQ_WTENABLE		0xE67E8030U
+#define MSTATQ_WTREFRESH	0xE67E8034U
+#define MSTATQ_WTSETTING0	0xE67E8038U
+#define MSTATQ_WTSETTING1	0xE67E803CU
+
+#define QOS_BASE1		(0xE67F0000U)
+#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
+
+/* other module */
+#define THS1_THCTR		0xE6198020U
+#define THS1_TEMP		0xE6198028U
+
+#define	DBSC_BASE		(0xE6790000U)
+#define DBSC_DBSCHQOS00		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS01		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS02		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS03		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS40		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS41		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS42		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS43		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS90		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS91		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS92		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS93		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS120	(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS121	(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS122	(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS123	(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS130	(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS131	(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS132	(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS133	(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS140	(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS141	(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS142	(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS143	(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS150	(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS151	(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS152	(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS153	(DBSC_BASE + 0x112CU)

drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk

+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h

+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3  0x0680
+#define DDR_PHY_ADR_G_REGSET_OFS_H3  0x0700
+#define DDR_PI_REGSET_OFS_H3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
+#define DDR_PI_REGSET_SIZE_H3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3  88
+#define DDR_PHY_ADR_V_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3  59
+#define DDR_PI_REGSET_NUM_H3         181
+
+static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
+/*0400*/ 0x000004f0,
+/*0401*/ 0x00000000,
+/*0402*/ 0x00000000,
+/*0403*/ 0x00000100,
+/*0404*/ 0x01003c0c,
+/*0405*/ 0x02003c0c,
+/*0406*/ 0x00010300,
+/*0407*/ 0x04000100,
+/*0408*/ 0x00000300,
+/*0409*/ 0x000700c0,
+/*040a*/ 0x00b00201,
+/*040b*/ 0x00000020,
+/*040c*/ 0x00000000,
+/*040d*/ 0x00000000,
+/*040e*/ 0x00000000,
+/*040f*/ 0x00000000,
+/*0410*/ 0x00000000,
+/*0411*/ 0x00000000,
+/*0412*/ 0x00000000,
+/*0413*/ 0x09000000,
+/*0414*/ 0x04080000,
+/*0415*/ 0x04080400,
+/*0416*/ 0x00000000,
+/*0417*/ 0x32103210,
+/*0418*/ 0x00800708,
+/*0419*/ 0x000f000c,
+/*041a*/ 0x00000100,
+/*041b*/ 0x55aa55aa,
+/*041c*/ 0x33cc33cc,
+/*041d*/ 0x0ff00ff0,
+/*041e*/ 0x0f0ff0f0,
+/*041f*/ 0x00008e38,
+/*0420*/ 0x76543210,
+/*0421*/ 0x00000001,
+/*0422*/ 0x00000000,
+/*0423*/ 0x00000000,
+/*0424*/ 0x00000000,
+/*0425*/ 0x00000000,
+/*0426*/ 0x00000000,
+/*0427*/ 0x00000000,
+/*0428*/ 0x00000000,
+/*0429*/ 0x00000000,
+/*042a*/ 0x00000000,
+/*042b*/ 0x00000000,
+/*042c*/ 0x00000000,
+/*042d*/ 0x00000000,
+/*042e*/ 0x00000000,
+/*042f*/ 0x00000000,
+/*0430*/ 0x00000000,
+/*0431*/ 0x00000000,
+/*0432*/ 0x00000000,
+/*0433*/ 0x00200000,
+/*0434*/ 0x08200820,
+/*0435*/ 0x08200820,
+/*0436*/ 0x08200820,
+/*0437*/ 0x08200820,
+/*0438*/ 0x08200820,
+/*0439*/ 0x00000820,
+/*043a*/ 0x03000300,
+/*043b*/ 0x03000300,
+/*043c*/ 0x03000300,
+/*043d*/ 0x03000300,
+/*043e*/ 0x00000300,
+/*043f*/ 0x00000000,
+/*0440*/ 0x00000000,
+/*0441*/ 0x00000000,
+/*0442*/ 0x00000000,
+/*0443*/ 0x00a000a0,
+/*0444*/ 0x00a000a0,
+/*0445*/ 0x00a000a0,
+/*0446*/ 0x00a000a0,
+/*0447*/ 0x00a000a0,
+/*0448*/ 0x00a000a0,
+/*0449*/ 0x00a000a0,
+/*044a*/ 0x00a000a0,
+/*044b*/ 0x00a000a0,
+/*044c*/ 0x01040109,
+/*044d*/ 0x00000200,
+/*044e*/ 0x01000000,
+/*044f*/ 0x00000200,
+/*0450*/ 0x4041a141,
+/*0451*/ 0xc00141a0,
+/*0452*/ 0x0e0100c0,
+/*0453*/ 0x0010000c,
+/*0454*/ 0x0c064208,
+/*0455*/ 0x000f0c18,
+/*0456*/ 0x00e00140,
+/*0457*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
+/*0600*/ 0x00000000,
+/*0601*/ 0x00000000,
+/*0602*/ 0x00000000,
+/*0603*/ 0x00000000,
+/*0604*/ 0x00000000,
+/*0605*/ 0x00000000,
+/*0606*/ 0x00000002,
+/*0607*/ 0x00000000,
+/*0608*/ 0x00000000,
+/*0609*/ 0x00000000,
+/*060a*/ 0x00400320,
+/*060b*/ 0x00000040,
+/*060c*/ 0x00dcba98,
+/*060d*/ 0x00000000,
+/*060e*/ 0x00dcba98,
+/*060f*/ 0x01000000,
+/*0610*/ 0x00020003,
+/*0611*/ 0x00000000,
+/*0612*/ 0x00000000,
+/*0613*/ 0x00000000,
+/*0614*/ 0x00002a01,
+/*0615*/ 0x00000015,
+/*0616*/ 0x00000015,
+/*0617*/ 0x0000002a,
+/*0618*/ 0x00000033,
+/*0619*/ 0x0000000c,
+/*061a*/ 0x0000000c,
+/*061b*/ 0x00000033,
+/*061c*/ 0x00418820,
+/*061d*/ 0x003f0000,
+/*061e*/ 0x0000003f,
+/*061f*/ 0x0002006e,
+/*0620*/ 0x02000200,
+/*0621*/ 0x02000200,
+/*0622*/ 0x00000200,
+/*0623*/ 0x42080010,
+/*0624*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
+/*0680*/ 0x04040404,
+/*0681*/ 0x00000404,
+/*0682*/ 0x00000000,
+/*0683*/ 0x00000000,
+/*0684*/ 0x00000000,
+/*0685*/ 0x00000000,
+/*0686*/ 0x00000002,
+/*0687*/ 0x00000000,
+/*0688*/ 0x00000000,
+/*0689*/ 0x00000000,
+/*068a*/ 0x00400320,
+/*068b*/ 0x00000040,
+/*068c*/ 0x00000000,
+/*068d*/ 0x00000000,
+/*068e*/ 0x00000000,
+/*068f*/ 0x01000000,
+/*0690*/ 0x00020003,
+/*0691*/ 0x00000000,
+/*0692*/ 0x00000000,
+/*0693*/ 0x00000000,
+/*0694*/ 0x00002a01,
+/*0695*/ 0x00000015,
+/*0696*/ 0x00000015,
+/*0697*/ 0x0000002a,
+/*0698*/ 0x00000033,
+/*0699*/ 0x0000000c,
+/*069a*/ 0x0000000c,
+/*069b*/ 0x00000033,
+/*069c*/ 0x00000000,
+/*069d*/ 0x00000000,
+/*069e*/ 0x00000000,
+/*069f*/ 0x0002006e,
+/*06a0*/ 0x02000200,
+/*06a1*/ 0x02000200,
+/*06a2*/ 0x00000200,
+/*06a3*/ 0x42080010,
+/*06a4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
+/*0700*/ 0x00000001,
+/*0701*/ 0x00000000,
+/*0702*/ 0x00000005,
+/*0703*/ 0x04000f00,
+/*0704*/ 0x00020080,
+/*0705*/ 0x00020055,
+/*0706*/ 0x00000000,
+/*0707*/ 0x00000000,
+/*0708*/ 0x00000000,
+/*0709*/ 0x00000050,
+/*070a*/ 0x00000000,
+/*070b*/ 0x01010100,
+/*070c*/ 0x00000200,
+/*070d*/ 0x00001102,
+/*070e*/ 0x00000000,
+/*070f*/ 0x000f1f00,
+/*0710*/ 0x0f1f0f1f,
+/*0711*/ 0x0f1f0f1f,
+/*0712*/ 0x00020003,
+/*0713*/ 0x02000200,
+/*0714*/ 0x00000200,
+/*0715*/ 0x00001102,
+/*0716*/ 0x00000064,
+/*0717*/ 0x00000000,
+/*0718*/ 0x00000000,
+/*0719*/ 0x00000502,
+/*071a*/ 0x027f6e00,
+/*071b*/ 0x007f007f,
+/*071c*/ 0x00007f3c,
+/*071d*/ 0x00047f6e,
+/*071e*/ 0x0003154f,
+/*071f*/ 0x0001154f,
+/*0720*/ 0x0001154f,
+/*0721*/ 0x0001154f,
+/*0722*/ 0x0001154f,
+/*0723*/ 0x00003fee,
+/*0724*/ 0x0001154f,
+/*0725*/ 0x00003fee,
+/*0726*/ 0x0001154f,
+/*0727*/ 0x00007f3c,
+/*0728*/ 0x0001154f,
+/*0729*/ 0x00000000,
+/*072a*/ 0x00000000,
+/*072b*/ 0x00000000,
+/*072c*/ 0x65000000,
+/*072d*/ 0x00000000,
+/*072e*/ 0x00000000,
+/*072f*/ 0x00000201,
+/*0730*/ 0x00000000,
+/*0731*/ 0x00000000,
+/*0732*/ 0x00000000,
+/*0733*/ 0x00000000,
+/*0734*/ 0x00000000,
+/*0735*/ 0x00000000,
+/*0736*/ 0x00000000,
+/*0737*/ 0x00000000,
+/*0738*/ 0x00000000,
+/*0739*/ 0x00000000,
+/*073a*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00000000,
+/*0203*/ 0x0000ffff,
+/*0204*/ 0x00000000,
+/*0205*/ 0x0000ffff,
+/*0206*/ 0x00000000,
+/*0207*/ 0x304cffff,
+/*0208*/ 0x00000200,
+/*0209*/ 0x00000200,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x0000304c,
+/*020d*/ 0x00000200,
+/*020e*/ 0x00000200,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x0000304c,
+/*0212*/ 0x00000200,
+/*0213*/ 0x00000200,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00010000,
+/*0217*/ 0x00000003,
+/*0218*/ 0x01000001,
+/*0219*/ 0x00000000,
+/*021a*/ 0x00000000,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x0f000101,
+/*022a*/ 0x08492d25,
+/*022b*/ 0x500e0c04,
+/*022c*/ 0x0002500e,
+/*022d*/ 0x00460003,
+/*022e*/ 0x182600cf,
+/*022f*/ 0x182600cf,
+/*0230*/ 0x00000005,
+/*0231*/ 0x00000000,
+/*0232*/ 0x00000000,
+/*0233*/ 0x00000000,
+/*0234*/ 0x00000000,
+/*0235*/ 0x00000000,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x01000000,
+/*0239*/ 0x00040404,
+/*023a*/ 0x01280a00,
+/*023b*/ 0x00000000,
+/*023c*/ 0x000f0000,
+/*023d*/ 0x00001803,
+/*023e*/ 0x00000000,
+/*023f*/ 0x00000000,
+/*0240*/ 0x00060002,
+/*0241*/ 0x00010001,
+/*0242*/ 0x01000101,
+/*0243*/ 0x04020201,
+/*0244*/ 0x00080804,
+/*0245*/ 0x00000000,
+/*0246*/ 0x08030000,
+/*0247*/ 0x15150408,
+/*0248*/ 0x00000000,
+/*0249*/ 0x00000000,
+/*024a*/ 0x00000000,
+/*024b*/ 0x001e0f0f,
+/*024c*/ 0x00000000,
+/*024d*/ 0x01000300,
+/*024e*/ 0x00000000,
+/*024f*/ 0x00000000,
+/*0250*/ 0x01000000,
+/*0251*/ 0x00010101,
+/*0252*/ 0x000e0e0e,
+/*0253*/ 0x000c0c0c,
+/*0254*/ 0x02060601,
+/*0255*/ 0x00000000,
+/*0256*/ 0x00000003,
+/*0257*/ 0x00181703,
+/*0258*/ 0x00280006,
+/*0259*/ 0x00280016,
+/*025a*/ 0x00000016,
+/*025b*/ 0x00000000,
+/*025c*/ 0x00000000,
+/*025d*/ 0x00000000,
+/*025e*/ 0x140a0000,
+/*025f*/ 0x0005010a,
+/*0260*/ 0x03018d03,
+/*0261*/ 0x000a018d,
+/*0262*/ 0x00060100,
+/*0263*/ 0x01000006,
+/*0264*/ 0x018e018e,
+/*0265*/ 0x018e0100,
+/*0266*/ 0x1111018e,
+/*0267*/ 0x10010204,
+/*0268*/ 0x09090650,
+/*0269*/ 0x20110202,
+/*026a*/ 0x00201000,
+/*026b*/ 0x00201000,
+/*026c*/ 0x04041000,
+/*026d*/ 0x18020100,
+/*026e*/ 0x00010118,
+/*026f*/ 0x004b004a,
+/*0270*/ 0x050f0000,
+/*0271*/ 0x0c01021e,
+/*0272*/ 0x34000000,
+/*0273*/ 0x00000000,
+/*0274*/ 0x00000000,
+/*0275*/ 0x00000000,
+/*0276*/ 0x312ed400,
+/*0277*/ 0xd4111132,
+/*0278*/ 0x1132312e,
+/*0279*/ 0x312ed411,
+/*027a*/ 0x00111132,
+/*027b*/ 0x32312ed4,
+/*027c*/ 0x2ed41111,
+/*027d*/ 0x11113231,
+/*027e*/ 0x32312ed4,
+/*027f*/ 0xd4001111,
+/*0280*/ 0x1132312e,
+/*0281*/ 0x312ed411,
+/*0282*/ 0xd4111132,
+/*0283*/ 0x1132312e,
+/*0284*/ 0x2ed40011,
+/*0285*/ 0x11113231,
+/*0286*/ 0x32312ed4,
+/*0287*/ 0x2ed41111,
+/*0288*/ 0x11113231,
+/*0289*/ 0x00020000,
+/*028a*/ 0x018d018d,
+/*028b*/ 0x0c08018d,
+/*028c*/ 0x1f121d22,
+/*028d*/ 0x4301b344,
+/*028e*/ 0x10172006,
+/*028f*/ 0x121d220c,
+/*0290*/ 0x01b3441f,
+/*0291*/ 0x17200643,
+/*0292*/ 0x1d220c10,
+/*0293*/ 0x00001f12,
+/*0294*/ 0x4301b344,
+/*0295*/ 0x10172006,
+/*0296*/ 0x00020002,
+/*0297*/ 0x00020002,
+/*0298*/ 0x00020002,
+/*0299*/ 0x00020002,
+/*029a*/ 0x00020002,
+/*029b*/ 0x00000000,
+/*029c*/ 0x00000000,
+/*029d*/ 0x00000000,
+/*029e*/ 0x00000000,
+/*029f*/ 0x00000000,
+/*02a0*/ 0x00000000,
+/*02a1*/ 0x00000000,
+/*02a2*/ 0x00000000,
+/*02a3*/ 0x00000000,
+/*02a4*/ 0x00000000,
+/*02a5*/ 0x00000000,
+/*02a6*/ 0x00000000,
+/*02a7*/ 0x01000400,
+/*02a8*/ 0x00304c00,
+/*02a9*/ 0x0001e2f8,
+/*02aa*/ 0x0000304c,
+/*02ab*/ 0x0001e2f8,
+/*02ac*/ 0x0000304c,
+/*02ad*/ 0x0001e2f8,
+/*02ae*/ 0x08000000,
+/*02af*/ 0x00000100,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000002
+};

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h

+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3VER2  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2  0x0640
+#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2  0x0680
+#define DDR_PI_REGSET_OFS_H3VER2         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
+#define DDR_PI_REGSET_SIZE_H3VER2        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3VER2  97
+#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2  79
+#define DDR_PI_REGSET_NUM_H3VER2         245
+
+static const uint32_t
+    DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
+/*0400*/ 0x76543210,
+/*0401*/ 0x0004f008,
+/*0402*/ 0x00020133,
+/*0403*/ 0x00000000,
+/*0404*/ 0x00000000,
+/*0405*/ 0x00010000,
+/*0406*/ 0x016e6e0e,
+/*0407*/ 0x026e6e0e,
+/*0408*/ 0x00010300,
+/*0409*/ 0x04000100,
+/*040a*/ 0x01000000,
+/*040b*/ 0x00000000,
+/*040c*/ 0x00000000,
+/*040d*/ 0x00000100,
+/*040e*/ 0x001700c0,
+/*040f*/ 0x020100b0,
+/*0410*/ 0x00030020,
+/*0411*/ 0x00000000,
+/*0412*/ 0x00000000,
+/*0413*/ 0x00000000,
+/*0414*/ 0x00000000,
+/*0415*/ 0x00000000,
+/*0416*/ 0x00000000,
+/*0417*/ 0x00000000,
+/*0418*/ 0x09000000,
+/*0419*/ 0x04080000,
+/*041a*/ 0x04080400,
+/*041b*/ 0x08000000,
+/*041c*/ 0x0c008007,
+/*041d*/ 0x00000f00,
+/*041e*/ 0x00000100,
+/*041f*/ 0x55aa55aa,
+/*0420*/ 0x33cc33cc,
+/*0421*/ 0x0ff00ff0,
+/*0422*/ 0x0f0ff0f0,
+/*0423*/ 0x00018e38,
+/*0424*/ 0x00000000,
+/*0425*/ 0x00000000,
+/*0426*/ 0x00000000,
+/*0427*/ 0x00000000,
+/*0428*/ 0x00000000,
+/*0429*/ 0x00000000,
+/*042a*/ 0x00000000,
+/*042b*/ 0x00000000,
+/*042c*/ 0x00000000,
+/*042d*/ 0x00000000,
+/*042e*/ 0x00000000,
+/*042f*/ 0x00000000,
+/*0430*/ 0x00000000,
+/*0431*/ 0x00000000,
+/*0432*/ 0x00000000,
+/*0433*/ 0x00000000,
+/*0434*/ 0x00000000,
+/*0435*/ 0x00000000,
+/*0436*/ 0x00000000,
+/*0437*/ 0x00000000,
+/*0438*/ 0x00000104,
+/*0439*/ 0x00082020,
+/*043a*/ 0x08200820,
+/*043b*/ 0x08200820,
+/*043c*/ 0x08200820,
+/*043d*/ 0x08200820,
+/*043e*/ 0x08200820,
+/*043f*/ 0x00000000,
+/*0440*/ 0x00000000,
+/*0441*/ 0x03000300,
+/*0442*/ 0x03000300,
+/*0443*/ 0x03000300,
+/*0444*/ 0x03000300,
+/*0445*/ 0x00000300,
+/*0446*/ 0x00000000,
+/*0447*/ 0x00000000,
+/*0448*/ 0x00000000,
+/*0449*/ 0x00000000,
+/*044a*/ 0x00000000,
+/*044b*/ 0x00a000a0,
+/*044c*/ 0x00a000a0,
+/*044d*/ 0x00a000a0,
+/*044e*/ 0x00a000a0,
+/*044f*/ 0x00a000a0,
+/*0450*/ 0x00a000a0,
+/*0451*/ 0x00a000a0,
+/*0452*/ 0x00a000a0,
+/*0453*/ 0x00a000a0,
+/*0454*/ 0x01040109,
+/*0455*/ 0x00000200,
+/*0456*/ 0x01000000,
+/*0457*/ 0x00000200,
+/*0458*/ 0x00000004,
+/*0459*/ 0x4041a141,
+/*045a*/ 0xc00141a0,
+/*045b*/ 0x0e0000c0,
+/*045c*/ 0x0010000c,
+/*045d*/ 0x063e4208,
+/*045e*/ 0x0f0c180c,
+/*045f*/ 0x00e00140,
+/*0460*/ 0x00000c20
+};
+
+static const uint32_t
+    DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
+/*0600*/ 0x00000000,
+/*0601*/ 0x00000000,
+/*0602*/ 0x00000000,
+/*0603*/ 0x00000000,
+/*0604*/ 0x00000000,
+/*0605*/ 0x00000000,
+/*0606*/ 0x00000000,
+/*0607*/ 0x00010000,
+/*0608*/ 0x00000200,
+/*0609*/ 0x00000000,
+/*060a*/ 0x00000000,
+/*060b*/ 0x00000000,
+/*060c*/ 0x00400320,
+/*060d*/ 0x00000040,
+/*060e*/ 0x00dcba98,
+/*060f*/ 0x03000000,
+/*0610*/ 0x00000200,
+/*0611*/ 0x00000000,
+/*0612*/ 0x00000000,
+/*0613*/ 0x00000000,
+/*0614*/ 0x0000002a,
+/*0615*/ 0x00000015,
+/*0616*/ 0x00000015,
+/*0617*/ 0x0000002a,
+/*0618*/ 0x00000033,
+/*0619*/ 0x0000000c,
+/*061a*/ 0x0000000c,
+/*061b*/ 0x00000033,
+/*061c*/ 0x00418820,
+/*061d*/ 0x003f0000,
+/*061e*/ 0x0000003f,
+/*061f*/ 0x0002c06e,
+/*0620*/ 0x02c002c0,
+/*0621*/ 0x02c002c0,
+/*0622*/ 0x000002c0,
+/*0623*/ 0x42080010,
+/*0624*/ 0x0000033e
+};
+
+static const uint32_t
+    DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
+/*0640*/ 0x00000000,
+/*0641*/ 0x00000000,
+/*0642*/ 0x00000000,
+/*0643*/ 0x00000000,
+/*0644*/ 0x00000000,
+/*0645*/ 0x00000000,
+/*0646*/ 0x00000000,
+/*0647*/ 0x00000000,
+/*0648*/ 0x00000000,
+/*0649*/ 0x00000000,
+/*064a*/ 0x00000000,
+/*064b*/ 0x00000000,
+/*064c*/ 0x00000000,
+/*064d*/ 0x00000000,
+/*064e*/ 0x00000000,
+/*064f*/ 0x00000000,
+/*0650*/ 0x00000000,
+/*0651*/ 0x00000000,
+/*0652*/ 0x00000000,
+/*0653*/ 0x00000000,
+/*0654*/ 0x00000000,
+/*0655*/ 0x00000000,
+/*0656*/ 0x00000000,
+/*0657*/ 0x00000000,
+/*0658*/ 0x00000000,
+/*0659*/ 0x00000000,
+/*065a*/ 0x00000000,
+/*065b*/ 0x00000000,
+/*065c*/ 0x00000000,
+/*065d*/ 0x00000000,
+/*065e*/ 0x00000000,
+/*065f*/ 0x00000000,
+/*0660*/ 0x00000000,
+/*0661*/ 0x00000000,
+/*0662*/ 0x00000000,
+/*0663*/ 0x00000000,
+/*0664*/ 0x00000000
+};
+
+static const uint32_t
+    DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
+/*0680*/ 0x00000000,
+/*0681*/ 0x00000100,
+/*0682*/ 0x00000000,
+/*0683*/ 0x00050000,
+/*0684*/ 0x0f000000,
+/*0685*/ 0x00800400,
+/*0686*/ 0x00020032,
+/*0687*/ 0x00020055,
+/*0688*/ 0x00000000,
+/*0689*/ 0x00000000,
+/*068a*/ 0x00000000,
+/*068b*/ 0x00000050,
+/*068c*/ 0x00000000,
+/*068d*/ 0x01010100,
+/*068e*/ 0x01000200,
+/*068f*/ 0x00000000,
+/*0690*/ 0x00010100,
+/*0691*/ 0x00000000,
+/*0692*/ 0x00000000,
+/*0693*/ 0x00000000,
+/*0694*/ 0x00000000,
+/*0695*/ 0x00005064,
+/*0696*/ 0x01421142,
+/*0697*/ 0x00000142,
+/*0698*/ 0x00000000,
+/*0699*/ 0x000f1100,
+/*069a*/ 0x0f110f11,
+/*069b*/ 0x09000f11,
+/*069c*/ 0x00000003,
+/*069d*/ 0x0002c000,
+/*069e*/ 0x02c002c0,
+/*069f*/ 0x000002c0,
+/*06a0*/ 0x01421142,
+/*06a1*/ 0x00000142,
+/*06a2*/ 0x00000000,
+/*06a3*/ 0x00000000,
+/*06a4*/ 0x05020000,
+/*06a5*/ 0x14000000,
+/*06a6*/ 0x027f6e00,
+/*06a7*/ 0x047f027f,
+/*06a8*/ 0x00027f6e,
+/*06a9*/ 0x00047f6e,
+/*06aa*/ 0x0003554f,
+/*06ab*/ 0x0001554f,
+/*06ac*/ 0x0001554f,
+/*06ad*/ 0x0001554f,
+/*06ae*/ 0x0001554f,
+/*06af*/ 0x00003fee,
+/*06b0*/ 0x0001554f,
+/*06b1*/ 0x00003fee,
+/*06b2*/ 0x0001554f,
+/*06b3*/ 0x00027f6e,
+/*06b4*/ 0x0001554f,
+/*06b5*/ 0x00004011,
+/*06b6*/ 0x00004410,
+/*06b7*/ 0x00000000,
+/*06b8*/ 0x00000000,
+/*06b9*/ 0x00000000,
+/*06ba*/ 0x00000065,
+/*06bb*/ 0x00000000,
+/*06bc*/ 0x00020201,
+/*06bd*/ 0x00000000,
+/*06be*/ 0x03000000,
+/*06bf*/ 0x00000008,
+/*06c0*/ 0x00000000,
+/*06c1*/ 0x00000000,
+/*06c2*/ 0x00000000,
+/*06c3*/ 0x00000000,
+/*06c4*/ 0x00000001,
+/*06c5*/ 0x00000000,
+/*06c6*/ 0x00000000,
+/*06c7*/ 0x00000000,
+/*06c8*/ 0x000000e4,
+/*06c9*/ 0x00010198,
+/*06ca*/ 0x00000000,
+/*06cb*/ 0x00000000,
+/*06cc*/ 0x07010000,
+/*06cd*/ 0x00000104,
+/*06ce*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00640000,
+/*0203*/ 0x00000000,
+/*0204*/ 0x0000ffff,
+/*0205*/ 0x00000000,
+/*0206*/ 0x0000ffff,
+/*0207*/ 0x00000000,
+/*0208*/ 0x0000ffff,
+/*0209*/ 0x0000304c,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x00000200,
+/*020d*/ 0x00000200,
+/*020e*/ 0x0000304c,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x00000200,
+/*0212*/ 0x00000200,
+/*0213*/ 0x0000304c,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00000200,
+/*0217*/ 0x00000200,
+/*0218*/ 0x00010000,
+/*0219*/ 0x00000003,
+/*021a*/ 0x01000001,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x00000000,
+/*022a*/ 0x00000000,
+/*022b*/ 0x0f000101,
+/*022c*/ 0x08492d25,
+/*022d*/ 0x500e0c04,
+/*022e*/ 0x0002500e,
+/*022f*/ 0x00000301,
+/*0230*/ 0x00000046,
+/*0231*/ 0x000000cf,
+/*0232*/ 0x00001826,
+/*0233*/ 0x000000cf,
+/*0234*/ 0x00001826,
+/*0235*/ 0x00000005,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x00000000,
+/*0239*/ 0x00000000,
+/*023a*/ 0x00000000,
+/*023b*/ 0x00000000,
+/*023c*/ 0x00000000,
+/*023d*/ 0x00000000,
+/*023e*/ 0x04010000,
+/*023f*/ 0x00000404,
+/*0240*/ 0x0101280a,
+/*0241*/ 0x00000000,
+/*0242*/ 0x00000000,
+/*0243*/ 0x0003000f,
+/*0244*/ 0x00000018,
+/*0245*/ 0x00000000,
+/*0246*/ 0x00000000,
+/*0247*/ 0x00060002,
+/*0248*/ 0x00010001,
+/*0249*/ 0x01000101,
+/*024a*/ 0x04020201,
+/*024b*/ 0x00080804,
+/*024c*/ 0x00000000,
+/*024d*/ 0x08030000,
+/*024e*/ 0x15150408,
+/*024f*/ 0x00000000,
+/*0250*/ 0x00000000,
+/*0251*/ 0x00000000,
+/*0252*/ 0x0f0f0000,
+/*0253*/ 0x0000001e,
+/*0254*/ 0x00000000,
+/*0255*/ 0x01000300,
+/*0256*/ 0x00000100,
+/*0257*/ 0x00000000,
+/*0258*/ 0x00000000,
+/*0259*/ 0x01000000,
+/*025a*/ 0x00000101,
+/*025b*/ 0x55555a5a,
+/*025c*/ 0x55555a5a,
+/*025d*/ 0x55555a5a,
+/*025e*/ 0x55555a5a,
+/*025f*/ 0x0e0e0001,
+/*0260*/ 0x0c0c000e,
+/*0261*/ 0x0601000c,
+/*0262*/ 0x17170106,
+/*0263*/ 0x00020202,
+/*0264*/ 0x03000000,
+/*0265*/ 0x00000000,
+/*0266*/ 0x00181703,
+/*0267*/ 0x00280006,
+/*0268*/ 0x00280016,
+/*0269*/ 0x00000016,
+/*026a*/ 0x00000000,
+/*026b*/ 0x00000000,
+/*026c*/ 0x00000000,
+/*026d*/ 0x0a000000,
+/*026e*/ 0x00010a14,
+/*026f*/ 0x00030005,
+/*0270*/ 0x0003018d,
+/*0271*/ 0x000a018d,
+/*0272*/ 0x00060100,
+/*0273*/ 0x01000006,
+/*0274*/ 0x018e018e,
+/*0275*/ 0x018e0100,
+/*0276*/ 0x1111018e,
+/*0277*/ 0x10010204,
+/*0278*/ 0x09090650,
+/*0279*/ 0xff110202,
+/*027a*/ 0x00ff1000,
+/*027b*/ 0x00ff1000,
+/*027c*/ 0x04041000,
+/*027d*/ 0x18020100,
+/*027e*/ 0x01010018,
+/*027f*/ 0x004a004a,
+/*0280*/ 0x004b004a,
+/*0281*/ 0x050f0000,
+/*0282*/ 0x0c01021e,
+/*0283*/ 0x34000000,
+/*0284*/ 0x00000000,
+/*0285*/ 0x00000000,
+/*0286*/ 0x00000000,
+/*0287*/ 0x00000000,
+/*0288*/ 0x36312ed4,
+/*0289*/ 0x2ed41111,
+/*028a*/ 0x11113631,
+/*028b*/ 0x36312ed4,
+/*028c*/ 0xd4001111,
+/*028d*/ 0x1136312e,
+/*028e*/ 0x312ed411,
+/*028f*/ 0xd4111136,
+/*0290*/ 0x1136312e,
+/*0291*/ 0x2ed40011,
+/*0292*/ 0x11113631,
+/*0293*/ 0x36312ed4,
+/*0294*/ 0x2ed41111,
+/*0295*/ 0x11113631,
+/*0296*/ 0x312ed400,
+/*0297*/ 0xd4111136,
+/*0298*/ 0x1136312e,
+/*0299*/ 0x312ed411,
+/*029a*/ 0x00111136,
+/*029b*/ 0x018d0200,
+/*029c*/ 0x018d018d,
+/*029d*/ 0x1d220c08,
+/*029e*/ 0x00001f12,
+/*029f*/ 0x4301b344,
+/*02a0*/ 0x10172006,
+/*02a1*/ 0x121d220c,
+/*02a2*/ 0x01b3441f,
+/*02a3*/ 0x17200643,
+/*02a4*/ 0x1d220c10,
+/*02a5*/ 0x00001f12,
+/*02a6*/ 0x4301b344,
+/*02a7*/ 0x10172006,
+/*02a8*/ 0x00020002,
+/*02a9*/ 0x00020002,
+/*02aa*/ 0x00020002,
+/*02ab*/ 0x00020002,
+/*02ac*/ 0x00020002,
+/*02ad*/ 0x00000000,
+/*02ae*/ 0x00000000,
+/*02af*/ 0x00000000,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000000,
+/*02b5*/ 0x00000000,
+/*02b6*/ 0x00000000,
+/*02b7*/ 0x00000000,
+/*02b8*/ 0x00000000,
+/*02b9*/ 0x00000400,
+/*02ba*/ 0x05040302,
+/*02bb*/ 0x01000f0e,
+/*02bc*/ 0x07060504,
+/*02bd*/ 0x03020100,
+/*02be*/ 0x02010000,
+/*02bf*/ 0x00000103,
+/*02c0*/ 0x0000304c,
+/*02c1*/ 0x0001e2f8,
+/*02c2*/ 0x0000304c,
+/*02c3*/ 0x0001e2f8,
+/*02c4*/ 0x0000304c,
+/*02c5*/ 0x0001e2f8,
+/*02c6*/ 0x08000000,
+/*02c7*/ 0x00000100,
+/*02c8*/ 0x00000000,
+/*02c9*/ 0x00000000,
+/*02ca*/ 0x00000000,
+/*02cb*/ 0x00000000,
+/*02cc*/ 0x00010000,
+/*02cd*/ 0x00000000,
+/*02ce*/ 0x00000000,
+/*02cf*/ 0x00000000,
+/*02d0*/ 0x00000000,
+/*02d1*/ 0x00000000,
+/*02d2*/ 0x00000000,
+/*02d3*/ 0x00000000,
+/*02d4*/ 0x00000000,
+/*02d5*/ 0x00000000,
+/*02d6*/ 0x00000000,
+/*02d7*/ 0x00000000,
+/*02d8*/ 0x00000000,
+/*02d9*/ 0x00000000,
+/*02da*/ 0x00000000,
+/*02db*/ 0x00000000,
+/*02dc*/ 0x00000000,
+/*02dd*/ 0x00000000,
+/*02de*/ 0x00000000,
+/*02df*/ 0x00000000,
+/*02e0*/ 0x00000000,
+/*02e1*/ 0x00000000,
+/*02e2*/ 0x00000000,
+/*02e3*/ 0x00000000,
+/*02e4*/ 0x00000000,
+/*02e5*/ 0x00000000,
+/*02e6*/ 0x00000000,
+/*02e7*/ 0x00000000,
+/*02e8*/ 0x00000000,
+/*02e9*/ 0x00000000,
+/*02ea*/ 0x00000000,
+/*02eb*/ 0x00000000,
+/*02ec*/ 0x00000000,
+/*02ed*/ 0x00000000,
+/*02ee*/ 0x00000002,
+/*02ef*/ 0x00000000,
+/*02f0*/ 0x00000000,
+/*02f1*/ 0x00000000,
+/*02f2*/ 0x00000000,
+/*02f3*/ 0x00000000,
+/*02f4*/ 0x00000000
+};

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h

+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_M3  0x0800
+#define DDR_PHY_ADR_V_REGSET_OFS_M3  0x0a00
+#define DDR_PHY_ADR_I_REGSET_OFS_M3  0x0a80
+#define DDR_PHY_ADR_G_REGSET_OFS_M3  0x0b80
+#define DDR_PI_REGSET_OFS_M3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
+#define DDR_PI_REGSET_SIZE_M3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_M3  89
+#define DDR_PHY_ADR_V_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_M3  64
+#define DDR_PI_REGSET_NUM_M3         202
+
+static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
+/*0800*/ 0x76543210,
+/*0801*/ 0x0004f008,
+/*0802*/ 0x00000000,
+/*0803*/ 0x00000000,
+/*0804*/ 0x00010000,
+/*0805*/ 0x036e6e0e,
+/*0806*/ 0x026e6e0e,
+/*0807*/ 0x00010300,
+/*0808*/ 0x04000100,
+/*0809*/ 0x00000300,
+/*080a*/ 0x001700c0,
+/*080b*/ 0x00b00201,
+/*080c*/ 0x00030020,
+/*080d*/ 0x00000000,
+/*080e*/ 0x00000000,
+/*080f*/ 0x00000000,
+/*0810*/ 0x00000000,
+/*0811*/ 0x00000000,
+/*0812*/ 0x00000000,
+/*0813*/ 0x00000000,
+/*0814*/ 0x09000000,
+/*0815*/ 0x04080000,
+/*0816*/ 0x04080400,
+/*0817*/ 0x00000000,
+/*0818*/ 0x32103210,
+/*0819*/ 0x00800708,
+/*081a*/ 0x000f000c,
+/*081b*/ 0x00000100,
+/*081c*/ 0x55aa55aa,
+/*081d*/ 0x33cc33cc,
+/*081e*/ 0x0ff00ff0,
+/*081f*/ 0x0f0ff0f0,
+/*0820*/ 0x00018e38,
+/*0821*/ 0x00000000,
+/*0822*/ 0x00000000,
+/*0823*/ 0x00000000,
+/*0824*/ 0x00000000,
+/*0825*/ 0x00000000,
+/*0826*/ 0x00000000,
+/*0827*/ 0x00000000,
+/*0828*/ 0x00000000,
+/*0829*/ 0x00000000,
+/*082a*/ 0x00000000,
+/*082b*/ 0x00000000,
+/*082c*/ 0x00000000,
+/*082d*/ 0x00000000,
+/*082e*/ 0x00000000,
+/*082f*/ 0x00000000,
+/*0830*/ 0x00000000,
+/*0831*/ 0x00000000,
+/*0832*/ 0x00000000,
+/*0833*/ 0x00200000,
+/*0834*/ 0x08200820,
+/*0835*/ 0x08200820,
+/*0836*/ 0x08200820,
+/*0837*/ 0x08200820,
+/*0838*/ 0x08200820,
+/*0839*/ 0x00000820,
+/*083a*/ 0x03000300,
+/*083b*/ 0x03000300,
+/*083c*/ 0x03000300,
+/*083d*/ 0x03000300,
+/*083e*/ 0x00000300,
+/*083f*/ 0x00000000,
+/*0840*/ 0x00000000,
+/*0841*/ 0x00000000,
+/*0842*/ 0x00000000,
+/*0843*/ 0x00a00000,
+/*0844*/ 0x00a000a0,
+/*0845*/ 0x00a000a0,
+/*0846*/ 0x00a000a0,
+/*0847*/ 0x00a000a0,
+/*0848*/ 0x00a000a0,
+/*0849*/ 0x00a000a0,
+/*084a*/ 0x00a000a0,
+/*084b*/ 0x00a000a0,
+/*084c*/ 0x010900a0,
+/*084d*/ 0x02000104,
+/*084e*/ 0x00000000,
+/*084f*/ 0x00010000,
+/*0850*/ 0x00000200,
+/*0851*/ 0x4041a141,
+/*0852*/ 0xc00141a0,
+/*0853*/ 0x0e0100c0,
+/*0854*/ 0x0010000c,
+/*0855*/ 0x0c064208,
+/*0856*/ 0x000f0c18,
+/*0857*/ 0x00e00140,
+/*0858*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
+/*0a00*/ 0x00000000,
+/*0a01*/ 0x00000000,
+/*0a02*/ 0x00000000,
+/*0a03*/ 0x00000000,
+/*0a04*/ 0x00000000,
+/*0a05*/ 0x00000000,
+/*0a06*/ 0x00000002,
+/*0a07*/ 0x00000000,
+/*0a08*/ 0x00000000,
+/*0a09*/ 0x00000000,
+/*0a0a*/ 0x00400320,
+/*0a0b*/ 0x00000040,
+/*0a0c*/ 0x00dcba98,
+/*0a0d*/ 0x00000000,
+/*0a0e*/ 0x00dcba98,
+/*0a0f*/ 0x01000000,
+/*0a10*/ 0x00020003,
+/*0a11*/ 0x00000000,
+/*0a12*/ 0x00000000,
+/*0a13*/ 0x00000000,
+/*0a14*/ 0x0000002a,
+/*0a15*/ 0x00000015,
+/*0a16*/ 0x00000015,
+/*0a17*/ 0x0000002a,
+/*0a18*/ 0x00000033,
+/*0a19*/ 0x0000000c,
+/*0a1a*/ 0x0000000c,
+/*0a1b*/ 0x00000033,
+/*0a1c*/ 0x0a418820,
+/*0a1d*/ 0x003f0000,
+/*0a1e*/ 0x0000003f,
+/*0a1f*/ 0x0002c06e,
+/*0a20*/ 0x02c002c0,
+/*0a21*/ 0x02c002c0,
+/*0a22*/ 0x000002c0,
+/*0a23*/ 0x42080010,
+/*0a24*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
+/*0a80*/ 0x04040404,
+/*0a81*/ 0x00000404,
+/*0a82*/ 0x00000000,
+/*0a83*/ 0x00000000,
+/*0a84*/ 0x00000000,
+/*0a85*/ 0x00000000,
+/*0a86*/ 0x00000002,
+/*0a87*/ 0x00000000,
+/*0a88*/ 0x00000000,
+/*0a89*/ 0x00000000,
+/*0a8a*/ 0x00400320,
+/*0a8b*/ 0x00000040,
+/*0a8c*/ 0x00000000,
+/*0a8d*/ 0x00000000,
+/*0a8e*/ 0x00000000,
+/*0a8f*/ 0x01000000,
+/*0a90*/ 0x00020003,
+/*0a91*/ 0x00000000,
+/*0a92*/ 0x00000000,
+/*0a93*/ 0x00000000,
+/*0a94*/ 0x0000002a,
+/*0a95*/ 0x00000015,
+/*0a96*/ 0x00000015,
+/*0a97*/ 0x0000002a,
+/*0a98*/ 0x00000033,
+/*0a99*/ 0x0000000c,
+/*0a9a*/ 0x0000000c,
+/*0a9b*/ 0x00000033,
+/*0a9c*/ 0x00000000,
+/*0a9d*/ 0x00000000,
+/*0a9e*/ 0x00000000,
+/*0a9f*/ 0x0002c06e,
+/*0aa0*/ 0x02c002c0,
+/*0aa1*/ 0x02c002c0,
+/*0aa2*/ 0x000002c0,
+/*0aa3*/ 0x42080010,
+/*0aa4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
+/*0b80*/ 0x00000001,
+/*0b81*/ 0x00000000,
+/*0b82*/ 0x00000005,
+/*0b83*/ 0x04000f00,
+/*0b84*/ 0x00020080,
+/*0b85*/ 0x00020055,
+/*0b86*/ 0x00000000,
+/*0b87*/ 0x00000000,
+/*0b88*/ 0x00000000,
+/*0b89*/ 0x00000050,
+/*0b8a*/ 0x00000000,
+/*0b8b*/ 0x01010100,
+/*0b8c*/ 0x00000600,
+/*0b8d*/ 0x50640000,
+/*0b8e*/ 0x01421142,
+/*0b8f*/ 0x00000142,
+/*0b90*/ 0x00000000,
+/*0b91*/ 0x000f1600,
+/*0b92*/ 0x0f160f16,
+/*0b93*/ 0x0f160f16,
+/*0b94*/ 0x00000003,
+/*0b95*/ 0x0002c000,
+/*0b96*/ 0x02c002c0,
+/*0b97*/ 0x000002c0,
+/*0b98*/ 0x01421142,
+/*0b99*/ 0x00000142,
+/*0b9a*/ 0x00000000,
+/*0b9b*/ 0x00000000,
+/*0b9c*/ 0x05020000,
+/*0b9d*/ 0x00000000,
+/*0b9e*/ 0x00027f6e,
+/*0b9f*/ 0x047f027f,
+/*0ba0*/ 0x00027f6e,
+/*0ba1*/ 0x00047f6e,
+/*0ba2*/ 0x0003554f,
+/*0ba3*/ 0x0001554f,
+/*0ba4*/ 0x0001554f,
+/*0ba5*/ 0x0001554f,
+/*0ba6*/ 0x0001554f,
+/*0ba7*/ 0x00003fee,
+/*0ba8*/ 0x0001554f,
+/*0ba9*/ 0x00003fee,
+/*0baa*/ 0x0001554f,
+/*0bab*/ 0x00027f6e,
+/*0bac*/ 0x0001554f,
+/*0bad*/ 0x00000000,
+/*0bae*/ 0x00000000,
+/*0baf*/ 0x00000000,
+/*0bb0*/ 0x65000000,
+/*0bb1*/ 0x00000000,
+/*0bb2*/ 0x00000000,
+/*0bb3*/ 0x00000201,
+/*0bb4*/ 0x00000000,
+/*0bb5*/ 0x00000000,
+/*0bb6*/ 0x00000000,
+/*0bb7*/ 0x00000000,
+/*0bb8*/ 0x00000000,
+/*0bb9*/ 0x00000000,
+/*0bba*/ 0x00000000,
+/*0bbb*/ 0x00000000,
+/*0bbc*/ 0x06e40000,
+/*0bbd*/ 0x00000000,
+/*0bbe*/ 0x00000000,
+/*0bbf*/ 0x00010000
+};
+
+static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00000000,
+/*0203*/ 0x0000ffff,
+/*0204*/ 0x00000000,
+/*0205*/ 0x0000ffff,
+/*0206*/ 0x00000000,
+/*0207*/ 0x304cffff,
+/*0208*/ 0x00000200,
+/*0209*/ 0x00000200,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x0000304c,
+/*020d*/ 0x00000200,
+/*020e*/ 0x00000200,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x0000304c,
+/*0212*/ 0x00000200,
+/*0213*/ 0x00000200,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00010000,
+/*0217*/ 0x00000003,
+/*0218*/ 0x01000001,
+/*0219*/ 0x00000000,
+/*021a*/ 0x00000000,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x0f000101,
+/*022a*/ 0x08492d25,
+/*022b*/ 0x0e0c0004,
+/*022c*/ 0x000e5000,
+/*022d*/ 0x00000250,
+/*022e*/ 0x00460003,
+/*022f*/ 0x182600cf,
+/*0230*/ 0x182600cf,
+/*0231*/ 0x00000005,
+/*0232*/ 0x00000000,
+/*0233*/ 0x00000000,
+/*0234*/ 0x00000000,
+/*0235*/ 0x00000000,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x00000000,
+/*0239*/ 0x01000000,
+/*023a*/ 0x00040404,
+/*023b*/ 0x01280a00,
+/*023c*/ 0x00000000,
+/*023d*/ 0x000f0000,
+/*023e*/ 0x00001803,
+/*023f*/ 0x00000000,
+/*0240*/ 0x00000000,
+/*0241*/ 0x00060002,
+/*0242*/ 0x00010001,
+/*0243*/ 0x01000101,
+/*0244*/ 0x04020201,
+/*0245*/ 0x00080804,
+/*0246*/ 0x00000000,
+/*0247*/ 0x08030000,
+/*0248*/ 0x15150408,
+/*0249*/ 0x00000000,
+/*024a*/ 0x00000000,
+/*024b*/ 0x00000000,
+/*024c*/ 0x000f0f00,
+/*024d*/ 0x0000001e,
+/*024e*/ 0x00000000,
+/*024f*/ 0x01000300,
+/*0250*/ 0x00000000,
+/*0251*/ 0x00000000,
+/*0252*/ 0x01000000,
+/*0253*/ 0x00010101,
+/*0254*/ 0x000e0e0e,
+/*0255*/ 0x000c0c0c,
+/*0256*/ 0x02060601,
+/*0257*/ 0x00000000,
+/*0258*/ 0x00000003,
+/*0259*/ 0x00181703,
+/*025a*/ 0x00280006,
+/*025b*/ 0x00280016,
+/*025c*/ 0x00000016,
+/*025d*/ 0x00000000,
+/*025e*/ 0x00000000,
+/*025f*/ 0x00000000,
+/*0260*/ 0x140a0000,
+/*0261*/ 0x0005010a,
+/*0262*/ 0x03018d03,
+/*0263*/ 0x000a018d,
+/*0264*/ 0x00060100,
+/*0265*/ 0x01000006,
+/*0266*/ 0x018e018e,
+/*0267*/ 0x018e0100,
+/*0268*/ 0x1111018e,
+/*0269*/ 0x10010204,
+/*026a*/ 0x09090650,
+/*026b*/ 0x20110202,
+/*026c*/ 0x00201000,
+/*026d*/ 0x00201000,
+/*026e*/ 0x04041000,
+/*026f*/ 0x18020100,
+/*0270*/ 0x00010118,
+/*0271*/ 0x004b004a,
+/*0272*/ 0x050f0000,
+/*0273*/ 0x0c01021e,
+/*0274*/ 0x34000000,
+/*0275*/ 0x00000000,
+/*0276*/ 0x00000000,
+/*0277*/ 0x00000000,
+/*0278*/ 0x0000d400,
+/*0279*/ 0x0031002e,
+/*027a*/ 0x00111136,
+/*027b*/ 0x002e00d4,
+/*027c*/ 0x11360031,
+/*027d*/ 0x0000d411,
+/*027e*/ 0x0031002e,
+/*027f*/ 0x00111136,
+/*0280*/ 0x002e00d4,
+/*0281*/ 0x11360031,
+/*0282*/ 0x0000d411,
+/*0283*/ 0x0031002e,
+/*0284*/ 0x00111136,
+/*0285*/ 0x002e00d4,
+/*0286*/ 0x11360031,
+/*0287*/ 0x00d40011,
+/*0288*/ 0x0031002e,
+/*0289*/ 0x00111136,
+/*028a*/ 0x002e00d4,
+/*028b*/ 0x11360031,
+/*028c*/ 0x0000d411,
+/*028d*/ 0x0031002e,
+/*028e*/ 0x00111136,
+/*028f*/ 0x002e00d4,
+/*0290*/ 0x11360031,
+/*0291*/ 0x0000d411,
+/*0292*/ 0x0031002e,
+/*0293*/ 0x00111136,
+/*0294*/ 0x002e00d4,
+/*0295*/ 0x11360031,
+/*0296*/ 0x02000011,
+/*0297*/ 0x018d018d,
+/*0298*/ 0x0c08018d,
+/*0299*/ 0x1f121d22,
+/*029a*/ 0x4301b344,
+/*029b*/ 0x10172006,
+/*029c*/ 0x1d220c10,
+/*029d*/ 0x00001f12,
+/*029e*/ 0x4301b344,
+/*029f*/ 0x10172006,
+/*02a0*/ 0x1d220c10,
+/*02a1*/ 0x00001f12,
+/*02a2*/ 0x4301b344,
+/*02a3*/ 0x10172006,
+/*02a4*/ 0x02000210,
+/*02a5*/ 0x02000200,
+/*02a6*/ 0x02000200,
+/*02a7*/ 0x02000200,
+/*02a8*/ 0x02000200,
+/*02a9*/ 0x00000000,
+/*02aa*/ 0x00000000,
+/*02ab*/ 0x00000000,
+/*02ac*/ 0x00000000,
+/*02ad*/ 0x00000000,
+/*02ae*/ 0x00000000,
+/*02af*/ 0x00000000,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000000,
+/*02b5*/ 0x00000400,
+/*02b6*/ 0x15141312,
+/*02b7*/ 0x11100f0e,
+/*02b8*/ 0x080b0c0d,
+/*02b9*/ 0x05040a09,
+/*02ba*/ 0x01000706,
+/*02bb*/ 0x00000302,
+/*02bc*/ 0x01030201,
+/*02bd*/ 0x00304c00,
+/*02be*/ 0x0001e2f8,
+/*02bf*/ 0x0000304c,
+/*02c0*/ 0x0001e2f8,
+/*02c1*/ 0x0000304c,
+/*02c2*/ 0x0001e2f8,
+/*02c3*/ 0x08000000,
+/*02c4*/ 0x00000100,
+/*02c5*/ 0x00000000,
+/*02c6*/ 0x00000000,
+/*02c7*/ 0x00000000,
+/*02c8*/ 0x00000000,
+/*02c9*/ 0x00000002
+};

drivers/staging/renesas/rcar/ddr/dram_sub_func.h

+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRAM_SUB_FUNC_H_
+#define DRAM_SUB_FUNC_H_
+
+#define DRAM_UPDATE_STATUS_ERR	(-1)
+#define DRAM_BOOT_STATUS_COLD	(0)
+#define DRAM_BOOT_STATUS_WARM	(1)
+
+int32_t rcar_dram_update_boot_status(uint32_t status);
+void rcar_dram_get_boot_status(uint32_t * status);
+
+#endif

drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h

+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_E3_H__
+#define PFC_INIT_E3_H__
+
+void pfc_init_e3(void);
+
+#endif /* PFC_INIT_E3_H__ */