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Unverified Commit 6ce30346 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1783 from thloh85-intel/integration_v2 

plat: intel: Add BL2 support for Stratix 10 SoC
parents c57abde6 9d82ef26
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plat/intel/soc/stratix10/soc/s10_handoff.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <drivers/arm/gicv2.h>
#include <assert.h>
#include <common/bl_common.h>
#include <lib/mmio.h>
#include <string.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include "s10_handoff.h"
#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \
(((x) & 0x0000FF00) << 8) | ((x) << 24))
int s10_get_handoff(handoff *reverse_hoff_ptr)
{
int i;
uint32_t *buffer;
handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET;
memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff));
buffer = (uint32_t *)reverse_hoff_ptr;
/* convert big indian to little indian */
for (i = 0; i < sizeof(handoff) / 4; i++)
buffer[i] = SWAP_UINT32(buffer[i]);
if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
return -1;
if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
return -1;
if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
return -1;
if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
return -1;
if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
return -1;
return 0;
}
plat/intel/soc/stratix10/soc/s10_memory_controller.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <errno.h>
#include <lib/mmio.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <string.h>
#include "s10_memory_controller.h"
#define ALT_CCU_NOC_DI_SET_MSK 0x10
#define DDR_READ_LATENCY_DELAY 40
#define MAX_MEM_CAL_RETRY 3
#define PRE_CALIBRATION_DELAY 1
#define POST_CALIBRATION_DELAY 1
#define TIMEOUT_EMIF_CALIBRATION 100
#define CLEAR_EMIF_DELAY 50000
#define CLEAR_EMIF_TIMEOUT 0x100000
#define TIMEOUT_INT_RESP 10000
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
/* tWR = Min. 15ns constant, see JEDEC standard eg. DDR4 is JESD79-4.pdf */
#define tWR_IN_NS 15
void configure_hmc_adaptor_regs(void);
void configure_ddr_sched_ctrl_regs(void);
/* The followring are the supported configurations */
uint32_t ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
DDR_CONFIG(0, 3, 10, 12),
DDR_CONFIG(0, 3, 9, 13),
DDR_CONFIG(0, 3, 10, 13),
DDR_CONFIG(0, 3, 9, 14),
DDR_CONFIG(0, 3, 10, 14),
DDR_CONFIG(0, 3, 10, 15),
DDR_CONFIG(0, 3, 11, 14),
DDR_CONFIG(0, 3, 11, 15),
DDR_CONFIG(0, 3, 10, 16),
DDR_CONFIG(0, 3, 11, 16),
DDR_CONFIG(0, 3, 12, 15), /* 0xa */
/* List for DDR4 only (pinout order > chip, bank, row, column) */
DDR_CONFIG(1, 3, 10, 14),
DDR_CONFIG(1, 4, 10, 14),
DDR_CONFIG(1, 3, 10, 15),
DDR_CONFIG(1, 4, 10, 15),
DDR_CONFIG(1, 3, 10, 16),
DDR_CONFIG(1, 4, 10, 16),
DDR_CONFIG(1, 3, 10, 17),
DDR_CONFIG(1, 4, 10, 17),
};
static int match_ddr_conf(uint32_t ddr_conf)
{
int i;
for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
if (ddr_conf == ddr_config[i])
return i;
}
return 0;
}
static int check_hmc_clk(void)
{
unsigned long timeout = 0;
uint32_t hmc_clk;
do {
hmc_clk = mmio_read_32(S10_SYSMGR_CORE_HMC_CLK);
if (hmc_clk & S10_SYSMGR_CORE_HMC_CLK_STATUS)
break;
udelay(1);
} while (++timeout < 1000);
if (timeout >= 1000)
return -ETIMEDOUT;
return 0;
}
static int clear_emif(void)
{
uint32_t data;
unsigned long timeout;
mmio_write_32(S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL, 0);
timeout = 0;
do {
data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT);
if ((data & S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0)
break;
udelay(CLEAR_EMIF_DELAY);
} while (++timeout < CLEAR_EMIF_TIMEOUT);
if (timeout >= CLEAR_EMIF_TIMEOUT)
return -ETIMEDOUT;
return 0;
}
static int mem_calibration(void)
{
int status = 0;
uint32_t data;
unsigned long timeout;
unsigned long retry = 0;
udelay(PRE_CALIBRATION_DELAY);
do {
if (retry != 0)
INFO("DDR: Retrying DRAM calibration\n");
timeout = 0;
do {
data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT);
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
break;
udelay(1);
} while (++timeout < TIMEOUT_EMIF_CALIBRATION);
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
status = clear_emif();
if (status)
ERROR("Failed to clear Emif\n");
} else {
break;
}
} while (++retry < MAX_MEM_CAL_RETRY);
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
ERROR("DDR: DRAM calibration failed.\n");
status = -EIO;
} else {
INFO("DDR: DRAM calibration success.\n");
status = 0;
}
udelay(POST_CALIBRATION_DELAY);
return status;
}
int init_hard_memory_controller(void)
{
int status;
mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, 0xFFFF0000);
mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1F);
mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, 0xFFFF0000);
mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT, 0x1F);
mmio_write_32(S10_SOC_NOC_FW_DDR_SCR_ENABLE, BIT(0) | BIT(8));
status = check_hmc_clk();
if (status) {
ERROR("DDR: Error, HMC clock not running\n");
return status;
}
mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH);
status = mem_calibration();
if (status) {
ERROR("DDR: Memory Calibration Failed\n");
return status;
}
configure_hmc_adaptor_regs();
configure_ddr_sched_ctrl_regs();
return 0;
}
void configure_ddr_sched_ctrl_regs(void)
{
uint32_t data, dram_addr_order, ddr_conf, bank, row, col,
rd_to_miss, wr_to_miss, burst_len, burst_len_ddr_clk,
burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio,
t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles,
bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw,
faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd;
INFO("Init HPS NOC's DDR Scheduler.\n");
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1);
dram_addr_order = S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(data);
data = mmio_read_32(S10_MPFE_IOHMC_DRAMADDRW);
col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data);
row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data);
bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) +
IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(data);
ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row));
if (ddr_conf) {
mmio_clrsetbits_32(
S10_MPFE_DDR_MAIN_SCHED_DDRCONF,
S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK,
S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf));
} else {
ERROR("DDR: Cannot find predefined ddrConf configuration.\n");
}
mmio_write_32(S10_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
data = mmio_read_32(S10_MPFE_IOHMC_DRAMTIMING0);
rd_latency = S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING0);
act_to_act = ACT_TO_ACT(data);
t_rcd = ACT_TO_RDWR(data);
act_to_act_bank = ACT_TO_ACT_DIFF_BANK(data);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING1);
rd_to_wr = RD_TO_WR(data);
bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data);
bus_rd_to_wr = RD_TO_WR_DIFF_CHIP(data);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING2);
t_rtp = RD_TO_PCH(data);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING3);
wr_to_rd = CALTIMING3_WR_TO_RD(data);
bus_wr_to_rd = CALTIMING3_WR_TO_RD_DIFF_CHIP(data);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING4);
t_rp = PCH_TO_VALID(data);
data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1);
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
burst_len = HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(data);
burst_len_ddr_clk = burst_len / 2;
burst_len_sched_clk = ((burst_len/2) / 2);
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
switch (S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(data)) {
case 1:
/* DDR4 - 1333MHz */
/* 20 (19.995) clock cycles = 15ns */
/* Calculate with rounding */
tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ?
((tWR_IN_NS * 1333) / 1000) + 1 :
((tWR_IN_NS * 1333) / 1000);
break;
default:
/* Others - 1066MHz or slower */
/* 16 (15.990) clock cycles = 15ns */
/* Calculate with rounding */
tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ?
((tWR_IN_NS * 1066) / 1000) + 1 :
((tWR_IN_NS * 1066) / 1000);
break;
}
rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk;
wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles)
/ 2) - rd_to_wr + t_rp + t_rcd;
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRTIMING,
bw_ratio << DDRTIMING_BWRATIO_OFST |
wr_to_rd << DDRTIMING_WRTORD_OFST|
rd_to_wr << DDRTIMING_RDTOWR_OFST |
burst_len_sched_clk << DDRTIMING_BURSTLEN_OFST |
wr_to_miss << DDRTIMING_WRTOMISS_OFST |
rd_to_miss << DDRTIMING_RDTOMISS_OFST |
act_to_act << DDRTIMING_ACTTOACT_OFST);
data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0);
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRMODE,
bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST |
auto_precharge << DDRMODE_AUTOPRECHARGE_OFST);
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_READLATENCY,
(rd_latency / 2) + DDR_READ_LATENCY_DELAY);
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING9);
faw = S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(data);
faw_bank = 1; // always 1 because we always have 4 bank DDR.
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_ACTIVATE,
faw_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST |
faw << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST |
act_to_act_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST);
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DEVTODEV,
bus_rd_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST |
bus_rd_to_wr << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST |
bus_wr_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST);
}
unsigned long get_physical_dram_size(void)
{
uint32_t data;
unsigned long ram_addr_width, ram_ext_if_io_width;
data = mmio_read_32(S10_MPFE_HMC_ADP_DDRIOCTRL);
switch (S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(data)) {
case 0:
ram_ext_if_io_width = 16;
break;
case 1:
ram_ext_if_io_width = 32;
break;
case 2:
ram_ext_if_io_width = 64;
break;
default:
ram_ext_if_io_width = 0;
break;
}
data = mmio_read_32(S10_MPFE_IOHMC_REG_DRAMADDRW);
ram_addr_width = IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(data) +
IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(data) +
IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(data) +
IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(data) +
IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(data);
return (1 << ram_addr_width) * (ram_ext_if_io_width / 8);
}
void configure_hmc_adaptor_regs(void)
{
uint32_t data;
uint32_t dram_io_width;
dram_io_width = S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(
mmio_read_32(S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST));
dram_io_width = (dram_io_width & 0xFF) >> 5;
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL,
S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK,
dram_io_width << S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST);
mmio_write_32(S10_MPFE_HMC_ADP_HPSINTFCSEL,
S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE);
data = mmio_read_32(S10_MPFE_IOHMC_REG_CTRLCFG1);
if (data & (1 << S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK);
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2,
S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK,
S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK);
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK);
} else {
INFO("ECC is disabled.\n");
}
}
plat/intel/soc/stratix10/soc/s10_pinmux.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include "s10_pinmux.h"
const uint32_t sysmgr_pinmux_array_sel[] = {
0x00000000, 0x00000001, /* usb */
0x00000004, 0x00000001,
0x00000008, 0x00000001,
0x0000000c, 0x00000001,
0x00000010, 0x00000001,
0x00000014, 0x00000001,
0x00000018, 0x00000001,
0x0000001c, 0x00000001,
0x00000020, 0x00000001,
0x00000024, 0x00000001,
0x00000028, 0x00000001,
0x0000002c, 0x00000001,
0x00000030, 0x00000000, /* emac0 */
0x00000034, 0x00000000,
0x00000038, 0x00000000,
0x0000003c, 0x00000000,
0x00000040, 0x00000000,
0x00000044, 0x00000000,
0x00000048, 0x00000000,
0x0000004c, 0x00000000,
0x00000050, 0x00000000,
0x00000054, 0x00000000,
0x00000058, 0x00000000,
0x0000005c, 0x00000000,
0x00000060, 0x00000008, /* gpio1 */
0x00000064, 0x00000008,
0x00000068, 0x00000005, /* uart0 tx */
0x0000006c, 0x00000005, /* uart 0 rx */
0x00000070, 0x00000008, /* gpio */
0x00000074, 0x00000008,
0x00000078, 0x00000004, /* i2c1 */
0x0000007c, 0x00000004,
0x00000080, 0x00000007, /* jtag */
0x00000084, 0x00000007,
0x00000088, 0x00000007,
0x0000008c, 0x00000007,
0x00000090, 0x00000001, /* sdmmc data0 */
0x00000094, 0x00000001,
0x00000098, 0x00000001,
0x0000009c, 0x00000001,
0x00000100, 0x00000001,
0x00000104, 0x00000001, /* sdmmc.data3 */
0x00000108, 0x00000008, /* loan */
0x0000010c, 0x00000008, /* gpio */
0x00000110, 0x00000008,
0x00000114, 0x00000008, /* gpio1.io21 */
0x00000118, 0x00000005, /* mdio0.mdio */
0x0000011c, 0x00000005 /* mdio0.mdc */
};
const uint32_t sysmgr_pinmux_array_ctrl[] = {
0x00000000, 0x00502c38, /* Q1_1 */
0x00000004, 0x00102c38,
0x00000008, 0x00502c38,
0x0000000c, 0x00502c38,
0x00000010, 0x00502c38,
0x00000014, 0x00502c38,
0x00000018, 0x00502c38,
0x0000001c, 0x00502c38,
0x00000020, 0x00502c38,
0x00000024, 0x00502c38,
0x00000028, 0x00502c38,
0x0000002c, 0x00502c38,
0x00000030, 0x00102c38, /* Q2_1 */
0x00000034, 0x00102c38,
0x00000038, 0x00502c38,
0x0000003c, 0x00502c38,
0x00000040, 0x00102c38,
0x00000044, 0x00102c38,
0x00000048, 0x00502c38,
0x0000004c, 0x00502c38,
0x00000050, 0x00102c38,
0x00000054, 0x00102c38,
0x00000058, 0x00502c38,
0x0000005c, 0x00502c38,
0x00000060, 0x00502c38, /* Q3_1 */
0x00000064, 0x00502c38,
0x00000068, 0x00102c38,
0x0000006c, 0x00502c38,
0x000000d0, 0x00502c38,
0x000000d4, 0x00502c38,
0x000000d8, 0x00542c38,
0x000000dc, 0x00542c38,
0x000000e0, 0x00502c38,
0x000000e4, 0x00502c38,
0x000000e8, 0x00102c38,
0x000000ec, 0x00502c38,
0x000000f0, 0x00502c38, /* Q4_1 */
0x000000f4, 0x00502c38,
0x000000f8, 0x00102c38,
0x000000fc, 0x00502c38,
0x00000100, 0x00502c38,
0x00000104, 0x00502c38,
0x00000108, 0x00102c38,
0x0000010c, 0x00502c38,
0x00000110, 0x00502c38,
0x00000114, 0x00502c38,
0x00000118, 0x00542c38,
0x0000011c, 0x00102c38
};
const uint32_t sysmgr_pinmux_array_fpga[] = {
0x00000000, 0x00000000,
0x00000004, 0x00000000,
0x00000008, 0x00000000,
0x0000000c, 0x00000000,
0x00000010, 0x00000000,
0x00000014, 0x00000000,
0x00000018, 0x00000000,
0x0000001c, 0x00000000,
0x00000020, 0x00000000,
0x00000028, 0x00000000,
0x0000002c, 0x00000000,
0x00000030, 0x00000000,
0x00000034, 0x00000000,
0x00000038, 0x00000000,
0x0000003c, 0x00000000,
0x00000040, 0x00000000,
0x00000044, 0x00000000,
0x00000048, 0x00000000,
0x00000050, 0x00000000,
0x00000054, 0x00000000,
0x00000058, 0x0000002a
};
const uint32_t sysmgr_pinmux_array_iodelay[] = {
0x00000000, 0x00000000,
0x00000004, 0x00000000,
0x00000008, 0x00000000,
0x0000000c, 0x00000000,
0x00000010, 0x00000000,
0x00000014, 0x00000000,
0x00000018, 0x00000000,
0x0000001c, 0x00000000,
0x00000020, 0x00000000,
0x00000024, 0x00000000,
0x00000028, 0x00000000,
0x0000002c, 0x00000000,
0x00000030, 0x00000000,
0x00000034, 0x00000000,
0x00000038, 0x00000000,
0x0000003c, 0x00000000,
0x00000040, 0x00000000,
0x00000044, 0x00000000,
0x00000048, 0x00000000,
0x0000004c, 0x00000000,
0x00000050, 0x00000000,
0x00000054, 0x00000000,
0x00000058, 0x00000000,
0x0000005c, 0x00000000,
0x00000060, 0x00000000,
0x00000064, 0x00000000,
0x00000068, 0x00000000,
0x0000006c, 0x00000000,
0x00000070, 0x00000000,
0x00000074, 0x00000000,
0x00000078, 0x00000000,
0x0000007c, 0x00000000,
0x00000080, 0x00000000,
0x00000084, 0x00000000,
0x00000088, 0x00000000,
0x0000008c, 0x00000000,
0x00000090, 0x00000000,
0x00000094, 0x00000000,
0x00000098, 0x00000000,
0x0000009c, 0x00000000,
0x00000100, 0x00000000,
0x00000104, 0x00000000,
0x00000108, 0x00000000,
0x0000010c, 0x00000000,
0x00000110, 0x00000000,
0x00000114, 0x00000000,
0x00000118, 0x00000000,
0x0000011c, 0x00000000
};
void config_pinmux(handoff *hoff_ptr)
{
unsigned int i;
for (i = 0; i < 96; i += 2) {
mmio_write_32(S10_PINMUX_PIN0SEL +
hoff_ptr->pinmux_sel_array[i],
hoff_ptr->pinmux_sel_array[i+1]);
}
for (i = 0; i < 96; i += 2) {
mmio_write_32(S10_PINMUX_IO0CTRL +
hoff_ptr->pinmux_io_array[i],
hoff_ptr->pinmux_io_array[i+1]);
}
for (i = 0; i < 42; i += 2) {
mmio_write_32(S10_PINMUX_PINMUX_EMAC0_USEFPGA +
hoff_ptr->pinmux_fpga_array[i],
hoff_ptr->pinmux_fpga_array[i+1]);
}
for (i = 0; i < 96; i += 2) {
mmio_write_32(S10_PINMUX_IO0_DELAY +
hoff_ptr->pinmux_iodelay_array[i],
hoff_ptr->pinmux_iodelay_array[i+1]);
}
}
plat/intel/soc/stratix10/soc/s10_reset_manager.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include "s10_reset_manager.h"
void deassert_peripheral_reset(void)
{
mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
S10_RSTMGR_PER1MODRST_WATCHDOG0 |
S10_RSTMGR_PER1MODRST_WATCHDOG1 |
S10_RSTMGR_PER1MODRST_WATCHDOG2 |
S10_RSTMGR_PER1MODRST_WATCHDOG3 |
S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
S10_RSTMGR_PER1MODRST_SPTIMER0 |
S10_RSTMGR_PER1MODRST_SPTIMER1 |
S10_RSTMGR_PER1MODRST_I2C0 |
S10_RSTMGR_PER1MODRST_I2C1 |
S10_RSTMGR_PER1MODRST_I2C2 |
S10_RSTMGR_PER1MODRST_I2C3 |
S10_RSTMGR_PER1MODRST_I2C4 |
S10_RSTMGR_PER1MODRST_UART0 |
S10_RSTMGR_PER1MODRST_UART1 |
S10_RSTMGR_PER1MODRST_GPIO0 |
S10_RSTMGR_PER1MODRST_GPIO1);
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
S10_RSTMGR_PER0MODRST_EMAC0OCP |
S10_RSTMGR_PER0MODRST_EMAC1OCP |
S10_RSTMGR_PER0MODRST_EMAC2OCP |
S10_RSTMGR_PER0MODRST_USB0OCP |
S10_RSTMGR_PER0MODRST_USB1OCP |
S10_RSTMGR_PER0MODRST_NANDOCP |
S10_RSTMGR_PER0MODRST_SDMMCOCP |
S10_RSTMGR_PER0MODRST_DMAOCP);
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
S10_RSTMGR_PER0MODRST_EMAC0 |
S10_RSTMGR_PER0MODRST_EMAC1 |
S10_RSTMGR_PER0MODRST_EMAC2 |
S10_RSTMGR_PER0MODRST_USB0 |
S10_RSTMGR_PER0MODRST_USB1 |
S10_RSTMGR_PER0MODRST_NAND |
S10_RSTMGR_PER0MODRST_SDMMC |
S10_RSTMGR_PER0MODRST_DMA |
S10_RSTMGR_PER0MODRST_SPIM0 |
S10_RSTMGR_PER0MODRST_SPIM1 |
S10_RSTMGR_PER0MODRST_SPIS0 |
S10_RSTMGR_PER0MODRST_SPIS1 |
S10_RSTMGR_PER0MODRST_EMACPTP |
S10_RSTMGR_PER0MODRST_DMAIF0 |
S10_RSTMGR_PER0MODRST_DMAIF1 |
S10_RSTMGR_PER0MODRST_DMAIF2 |
S10_RSTMGR_PER0MODRST_DMAIF3 |
S10_RSTMGR_PER0MODRST_DMAIF4 |
S10_RSTMGR_PER0MODRST_DMAIF5 |
S10_RSTMGR_PER0MODRST_DMAIF6 |
S10_RSTMGR_PER0MODRST_DMAIF7);
}
void config_hps_hs_before_warm_reset(void)
{
uint32_t or_mask = 0;
or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
}
plat/intel/soc/stratix10/soc/s10_system_manager.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include "s10_system_manager.h"
void enable_nonsecure_access(void)
{
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
}
plat/intel/soc/stratix10/stratix10_image_load.c 0 → 100644
View file @ 6ce30346
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/desc_image_load.h>
/*******************************************************************************
* This function flushes the data structures so that they are visible
* in memory for the next BL image.
******************************************************************************/
void plat_flush_next_bl_params(void)
{
flush_bl_params_desc();
}
/*******************************************************************************
* This function returns the list of loadable images.
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
return get_bl_load_info_from_mem_params_desc();
}
/*******************************************************************************
* This function returns the list of executable images.
******************************************************************************/
bl_params_t *plat_get_next_bl_params(void)
{
return get_next_bl_params_from_mem_params_desc();
}
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