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Commit 6dcb6045 authored by Sandrine Bailleux's avatar Sandrine Bailleux Committed by TrustedFirmware Code Review
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Merge changes I66dc6855,I2217a1ad into integration 

* changes:
  rockchip: Update BL31_BASE to 0x40000
  rockchip: Fix typo for TF content text
parents 6a7cbfd5 0aad563c
master v2.5 v2.5-rc1 v2.5-rc0 v2.4 v2.4-rc2 v2.4-rc1 v2.4-rc0 v2.3 v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.2 v2.2-rc2 v2.2-rc1 v2.2-rc0 arm_cca_v0.2 arm_cca_v0.1
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plat/rockchip/px30/include/platform_def.h
View file @ 6dcb6045
......@@ -69,7 +69,7 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 512KB */
/* TF text, ro, rw, Size: 512KB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x80000)
......@@ -79,7 +79,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_BASE (TZRAM_BASE + 0x40000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
......
plat/rockchip/rk3288/include/shared/bl32_param.h
View file @ 6dcb6045
......@@ -10,9 +10,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 2MB */
/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x200000)
#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL32 specific defines.
......@@ -20,7 +20,7 @@
/*
* Put BL32 at the top of the Trusted RAM
*/
#define BL32_BASE (TZRAM_BASE + 0x100000)
#define BL32_BASE (TZRAM_BASE + 0x40000)
#define BL32_LIMIT (TZRAM_BASE + TZRAM_SIZE)
#endif /* BL32_PARAM_H */
plat/rockchip/rk3328/include/platform_def.h
View file @ 6dcb6045
......@@ -66,7 +66,7 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 512KB */
/* TF text, ro, rw, Size: 512KB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x80000)
......@@ -76,7 +76,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_BASE (TZRAM_BASE + 0x40000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
......
plat/rockchip/rk3368/include/platform_def.h
View file @ 6dcb6045
......@@ -67,7 +67,7 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 512KB */
/* TF text, ro, rw, Size: 512KB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x80000)
......@@ -77,7 +77,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_BASE (TZRAM_BASE + 0x40000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
......
plat/rockchip/rk3399/include/shared/bl31_param.h
View file @ 6dcb6045
......@@ -20,7 +20,7 @@
/*
* Put BL31 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x1000)
#define BL31_BASE (TZRAM_BASE + 0x40000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
#endif /* BL31_PARAM_H */
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