Ensure proper ID register is checked for feature detection

SSBS support is determined by checking ID_AA64PFR1_EL1 and not
ID_AA64PFR0_EL1.

Fixes ARM-Software/tf-issues#679

Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

include/arch/aarch64/arch_helpers.h

@@ -208,6 +208,7 @@ DEFINE_SYSREG_RW_FUNCS(par_el1)
 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
+DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
 DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
 DEFINE_SYSREG_READ_FUNC(CurrentEl)

services/arm_arch_svc/arm_arch_svc_setup.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -41,7 +41,7 @@ static int32_t smccc_arch_features(u_register_t arg)
 		 * PE implements architectural Speculation Store Bypass Safe
 		 * (SSBS) feature.
 		 */
-		ssbs = (read_id_aa64pfr0_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
+		ssbs = (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
 			ID_AA64PFR1_EL1_SSBS_MASK;
 
 		/*