Commit 7060e0d8 authored by Samuel Holland's avatar Samuel Holland
Browse files

allwinner: Use RSB for the PMIC connection on H6



RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.

Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
parent 44702983
...@@ -125,11 +125,9 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) ...@@ -125,11 +125,9 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb)
device_bit = BIT(6); device_bit = BIT(6);
break; break;
case SUNXI_SOC_H6: case SUNXI_SOC_H6:
if (use_rsb) pin_func = use_rsb ? 0x22 : 0x33;
return -ENODEV;
pin_func = 0x33;
device_bit = BIT(16); device_bit = BIT(16);
reset_offset = 0x19c; reset_offset = use_rsb ? 0x1bc : 0x19c;
break; break;
case SUNXI_SOC_A64: case SUNXI_SOC_A64:
pin_func = use_rsb ? 0x22 : 0x33; pin_func = use_rsb ? 0x22 : 0x33;
...@@ -157,7 +155,7 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) ...@@ -157,7 +155,7 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb)
if (socid != SUNXI_SOC_H6) if (socid != SUNXI_SOC_H6)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else else
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
/* assert, then de-assert reset of I2C/RSB controller */ /* assert, then de-assert reset of I2C/RSB controller */
mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
......
...@@ -55,6 +55,7 @@ ...@@ -55,6 +55,7 @@
#define SUNXI_R_TWD_BASE 0x07020800 #define SUNXI_R_TWD_BASE 0x07020800
#define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_R_I2C_BASE 0x07081400 #define SUNXI_R_I2C_BASE 0x07081400
#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_PIO_BASE 0x07022000
......
...@@ -8,4 +8,4 @@ ...@@ -8,4 +8,4 @@
include plat/allwinner/common/allwinner-common.mk include plat/allwinner/common/allwinner-common.mk
BL31_SOURCES += drivers/allwinner/axp/axp805.c \ BL31_SOURCES += drivers/allwinner/axp/axp805.c \
drivers/mentor/i2c/mi2cv.c drivers/allwinner/sunxi_rsb.c
...@@ -6,20 +6,17 @@ ...@@ -6,20 +6,17 @@
*/ */
#include <errno.h> #include <errno.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/allwinner/axp.h> #include <drivers/allwinner/axp.h>
#include <drivers/delay_timer.h> #include <drivers/allwinner/sunxi_rsb.h>
#include <drivers/mentor/mi2cv.h>
#include <lib/mmio.h>
#include <sunxi_def.h> #include <sunxi_def.h>
#include <sunxi_mmap.h> #include <sunxi_mmap.h>
#include <sunxi_private.h> #include <sunxi_private.h>
#define AXP805_ADDR 0x36 #define AXP805_HW_ADDR 0x745
#define AXP805_RT_ADDR 0x3a
static enum pmic_type { static enum pmic_type {
UNKNOWN, UNKNOWN,
...@@ -28,67 +25,67 @@ static enum pmic_type { ...@@ -28,67 +25,67 @@ static enum pmic_type {
int axp_read(uint8_t reg) int axp_read(uint8_t reg)
{ {
uint8_t val; return rsb_read(AXP805_RT_ADDR, reg);
int ret;
ret = i2c_write(AXP805_ADDR, 0, 0, &reg, 1);
if (ret == 0)
ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1);
if (ret) {
ERROR("PMIC: Cannot read AXP805 register %02x\n", reg);
return ret;
}
return val;
} }
int axp_write(uint8_t reg, uint8_t val) int axp_write(uint8_t reg, uint8_t val)
{ {
int ret; return rsb_write(AXP805_RT_ADDR, reg, val);
ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1);
if (ret)
ERROR("PMIC: Cannot write AXP805 register %02x\n", reg);
return ret;
} }
static int axp805_probe(void) static int rsb_init(void)
{ {
int ret; int ret;
/* Switch the AXP805 to master/single-PMIC mode. */ ret = rsb_init_controller();
ret = axp_write(0xff, 0x0);
if (ret) if (ret)
return ret; return ret;
ret = axp_check_id(); /* Switch to the recommended 3 MHz bus clock. */
ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
if (ret) if (ret)
return ret; return ret;
return 0; /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
if (ret)
return ret;
/* Associate the 8-bit runtime address with the 12-bit bus address. */
ret = rsb_assign_runtime_address(AXP805_HW_ADDR, AXP805_RT_ADDR);
if (ret)
return ret;
return axp_check_id();
} }
int sunxi_pmic_setup(uint16_t socid, const void *fdt) int sunxi_pmic_setup(uint16_t socid, const void *fdt)
{ {
int ret; int ret;
INFO("PMIC: Probing AXP805 on I2C\n"); INFO("PMIC: Probing AXP805 on RSB\n");
ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); ret = sunxi_init_platform_r_twi(socid, true);
if (ret) if (ret)
return ret; return ret;
/* initialise mi2cv driver */ ret = rsb_init();
i2c_init((void *)SUNXI_R_I2C_BASE); if (ret)
return ret;
ret = axp805_probe(); /* Switch the AXP805 to master/single-PMIC mode. */
ret = axp_write(0xff, 0x0);
if (ret) if (ret)
return ret; return ret;
pmic = AXP805; pmic = AXP805;
axp_setup_regulators(fdt); axp_setup_regulators(fdt);
/* Switch the PMIC back to I2C mode. */
ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
if (ret)
return ret;
return 0; return 0;
} }
...@@ -96,10 +93,9 @@ void sunxi_power_down(void) ...@@ -96,10 +93,9 @@ void sunxi_power_down(void)
{ {
switch (pmic) { switch (pmic) {
case AXP805: case AXP805:
/* Re-initialise after rich OS might have used it. */ /* (Re-)init RSB in case the rich OS has disabled it. */
sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); sunxi_init_platform_r_twi(SUNXI_SOC_H6, true);
/* initialise mi2cv driver */ rsb_init();
i2c_init((void *)SUNXI_R_I2C_BASE);
axp_power_off(); axp_power_off();
break; break;
default: default:
......
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