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Commit 70cb692e authored by Varun Wadekar's avatar Varun Wadekar
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Tegra: add explicit casts for integer macros 



This patch adds explicit casts (U(x)) to integers in the tegra_def.h
headers, to make them compatible with whatever operation they're used
in [MISRA-C Rule 10.1]

Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent 030567e6
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plat/nvidia/tegra/include/platform_def.h
View file @ 70cb692e
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <arch.h> #include <arch.h>
#include <common_def.h> #include <common_def.h>
#include <tegra_def.h> #include <tegra_def.h>
#include <utils_def.h>
/******************************************************************************* /*******************************************************************************
* Generic platform constants * Generic platform constants
...@@ -17,10 +18,10 @@ ...@@ -17,10 +18,10 @@
/* Size of cacheable stacks */ /* Size of cacheable stacks */
#ifdef IMAGE_BL31 #ifdef IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x400 #define PLATFORM_STACK_SIZE U(0x400)
#endif #endif
#define TEGRA_PRIMARY_CPU 0x0 #define TEGRA_PRIMARY_CPU U(0x0)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
...@@ -31,20 +32,20 @@ ...@@ -31,20 +32,20 @@
/******************************************************************************* /*******************************************************************************
* Platform console related constants * Platform console related constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_CONSOLE_BAUDRATE 115200 #define TEGRA_CONSOLE_BAUDRATE U(115200)
#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 #define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000)
/******************************************************************************* /*******************************************************************************
* Platform memory map related constants * Platform memory map related constants
******************************************************************************/ ******************************************************************************/
/* Size of trusted dram */ /* Size of trusted dram */
#define TZDRAM_SIZE 0x00400000 #define TZDRAM_SIZE U(0x00400000)
#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
/******************************************************************************* /*******************************************************************************
* BL31 specific defines. * BL31 specific defines.
******************************************************************************/ ******************************************************************************/
#define BL31_SIZE 0x40000 #define BL31_SIZE U(0x40000)
#define BL31_BASE TZDRAM_BASE #define BL31_BASE TZDRAM_BASE
#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
...@@ -53,8 +54,8 @@ ...@@ -53,8 +54,8 @@
/******************************************************************************* /*******************************************************************************
* Platform specific page table and MMU setup constants * Platform specific page table and MMU setup constants
******************************************************************************/ ******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35) #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35) #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/******************************************************************************* /*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform. * Some data must be aligned on the biggest cache line size in the platform.
...@@ -62,6 +63,6 @@ ...@@ -62,6 +63,6 @@
* integrated and external caches. * integrated and external caches.
******************************************************************************/ ******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */ #endif /* __PLATFORM_DEF_H__ */
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 70cb692e
...@@ -7,11 +7,13 @@ ...@@ -7,11 +7,13 @@
#ifndef __TEGRA_DEF_H__ #ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__ #define __TEGRA_DEF_H__
#include <utils_def.h>
/******************************************************************************* /*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
* call as the `state-id` field in the 'power state' parameter. * call as the `state-id` field in the 'power state' parameter.
******************************************************************************/ ******************************************************************************/
#define PSTATE_ID_SOC_POWERDN 0xD #define PSTATE_ID_SOC_POWERDN U(0xD)
/******************************************************************************* /*******************************************************************************
* Platform power states (used by PSCI framework) * Platform power states (used by PSCI framework)
...@@ -19,80 +21,80 @@ ...@@ -19,80 +21,80 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/ ******************************************************************************/
#define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
******************************************************************************/ ******************************************************************************/
#define TEGRA_GICD_BASE 0x50041000 #define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE 0x50042000 #define TEGRA_GICC_BASE U(0x50042000)
/******************************************************************************* /*******************************************************************************
* Tegra micro-seconds timer constants * Tegra micro-seconds timer constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TMRUS_BASE 0x60005010 #define TEGRA_TMRUS_BASE U(0x60005010)
#define TEGRA_TMRUS_SIZE 0x1000 #define TEGRA_TMRUS_SIZE U(0x1000)
/******************************************************************************* /*******************************************************************************
* Tegra Clock and Reset Controller constants * Tegra Clock and Reset Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x60006000 #define TEGRA_CAR_RESET_BASE U(0x60006000)
/******************************************************************************* /*******************************************************************************
* Tegra Flow Controller constants * Tegra Flow Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_FLOWCTRL_BASE 0x60007000 #define TEGRA_FLOWCTRL_BASE U(0x60007000)
/******************************************************************************* /*******************************************************************************
* Tegra Secure Boot Controller constants * Tegra Secure Boot Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_SB_BASE 0x6000C200 #define TEGRA_SB_BASE U(0x6000C200)
/******************************************************************************* /*******************************************************************************
* Tegra Exception Vectors constants * Tegra Exception Vectors constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_EVP_BASE 0x6000F000 #define TEGRA_EVP_BASE U(0x6000F000)
/******************************************************************************* /*******************************************************************************
* Tegra Miscellaneous register constants * Tegra Miscellaneous register constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE 0x70000000 #define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET 0x804 #define HARDWARE_REVISION_OFFSET U(0x804)
/******************************************************************************* /*******************************************************************************
* Tegra UART controller base addresses * Tegra UART controller base addresses
******************************************************************************/ ******************************************************************************/
#define TEGRA_UARTA_BASE 0x70006000 #define TEGRA_UARTA_BASE U(0x70006000)
#define TEGRA_UARTB_BASE 0x70006040 #define TEGRA_UARTB_BASE U(0x70006040)
#define TEGRA_UARTC_BASE 0x70006200 #define TEGRA_UARTC_BASE U(0x70006200)
#define TEGRA_UARTD_BASE 0x70006300 #define TEGRA_UARTD_BASE U(0x70006300)
#define TEGRA_UARTE_BASE 0x70006400 #define TEGRA_UARTE_BASE U(0x70006400)
/******************************************************************************* /*******************************************************************************
* Tegra Power Mgmt Controller constants * Tegra Power Mgmt Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_PMC_BASE 0x7000E400 #define TEGRA_PMC_BASE U(0x7000E400)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Controller constants * Tegra Memory Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE U(0x70019000)
/* TZDRAM carveout configuration registers */ /* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 0x74 #define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 0x9BC #define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */ /* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978 #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO 0x648 #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000 #define TEGRA_TZRAM_BASE U(0x7C010000)
#define TEGRA_TZRAM_SIZE 0x10000 #define TEGRA_TZRAM_SIZE U(0x10000)
#endif /* __TEGRA_DEF_H__ */ #endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 70cb692e
...@@ -7,6 +7,8 @@ ...@@ -7,6 +7,8 @@
#ifndef __TEGRA_DEF_H__ #ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__ #define __TEGRA_DEF_H__
#include <utils_def.h>
/******************************************************************************* /*******************************************************************************
* MCE apertures used by the ARI interface * MCE apertures used by the ARI interface
* *
...@@ -17,34 +19,34 @@ ...@@ -17,34 +19,34 @@
* Aperture 4 - Cpu4 (Denver15) * Aperture 4 - Cpu4 (Denver15)
* Aperture 5 - Cpu5 (Denver15) * Aperture 5 - Cpu5 (Denver15)
******************************************************************************/ ******************************************************************************/
#define MCE_ARI_APERTURE_0_OFFSET 0x0 #define MCE_ARI_APERTURE_0_OFFSET U(0x0)
#define MCE_ARI_APERTURE_1_OFFSET 0x10000 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
#define MCE_ARI_APERTURE_2_OFFSET 0x20000 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
#define MCE_ARI_APERTURE_3_OFFSET 0x30000 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
#define MCE_ARI_APERTURE_4_OFFSET 0x40000 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
#define MCE_ARI_APERTURE_5_OFFSET 0x50000 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
/* number of apertures */ /* number of apertures */
#define MCE_ARI_APERTURES_MAX 6 #define MCE_ARI_APERTURES_MAX U(6)
/* each ARI aperture is 64KB */ /* each ARI aperture is 64KB */
#define MCE_ARI_APERTURE_SIZE 0x10000 #define MCE_ARI_APERTURE_SIZE U(0x10000)
/******************************************************************************* /*******************************************************************************
* CPU core id macros for the MCE_ONLINE_CORE ARI * CPU core id macros for the MCE_ONLINE_CORE ARI
******************************************************************************/ ******************************************************************************/
#define MCE_CORE_ID_MAX 8 #define MCE_CORE_ID_MAX U(8)
#define MCE_CORE_ID_MASK 0x7 #define MCE_CORE_ID_MASK U(0x7)
/******************************************************************************* /*******************************************************************************
* These values are used by the PSCI implementation during the `CPU_SUSPEND` * These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter. * parameter.
******************************************************************************/ ******************************************************************************/
#define PSTATE_ID_CORE_IDLE 6 #define PSTATE_ID_CORE_IDLE U(6)
#define PSTATE_ID_CORE_POWERDN 7 #define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_SOC_POWERDN 2 #define PSTATE_ID_SOC_POWERDN U(2)
/******************************************************************************* /*******************************************************************************
* Platform power states (used by PSCI framework) * Platform power states (used by PSCI framework)
...@@ -52,209 +54,195 @@ ...@@ -52,209 +54,195 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/ ******************************************************************************/
#define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE 8 #define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
* Implementation defined ACTLR_EL3 bit definitions
******************************************************************************/
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
/******************************************************************************* /*******************************************************************************
* Secure IRQ definitions * Secure IRQ definitions
******************************************************************************/ ******************************************************************************/
#define TEGRA186_TOP_WDT_IRQ 49 #define TEGRA186_TOP_WDT_IRQ U(49)
#define TEGRA186_AON_WDT_IRQ 50 #define TEGRA186_AON_WDT_IRQ U(50)
#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
/******************************************************************************* /*******************************************************************************
* Tegra Miscellanous register constants * Tegra Miscellanous register constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE 0x00100000 #define TEGRA_MISC_BASE U(0x00100000)
#define HARDWARE_REVISION_OFFSET 0x4 #define HARDWARE_REVISION_OFFSET U(0x4)
#define MISCREG_PFCFG 0x200C #define MISCREG_PFCFG U(0x200C)
/******************************************************************************* /*******************************************************************************
* Tegra TSA Controller constants * Tegra TSA Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TSA_BASE 0x02400000 #define TEGRA_TSA_BASE U(0x02400000)
/******************************************************************************* /*******************************************************************************
* TSA configuration registers * TSA configuration registers
******************************************************************************/ ******************************************************************************/
#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (U(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Controller constants * Tegra Memory Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_STREAMID_BASE U(0x02C00000)
#define TEGRA_MC_BASE 0x02C10000 #define TEGRA_MC_BASE U(0x02C10000)
/* General Security Carveout register macros */ /* General Security Carveout register macros */
#define MC_GSC_CONFIG_REGS_SIZE 0x40UL #define MC_GSC_CONFIG_REGS_SIZE U(0x40)
#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1) #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
#define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0) #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
#define MC_GSC_BASE_LO_SHIFT 12UL #define MC_GSC_BASE_LO_SHIFT U(12)
#define MC_GSC_BASE_LO_MASK 0xFFFFFUL #define MC_GSC_BASE_LO_MASK U(0xFFFFF)
#define MC_GSC_BASE_HI_SHIFT 0UL #define MC_GSC_BASE_HI_SHIFT U(0)
#define MC_GSC_BASE_HI_MASK 3UL #define MC_GSC_BASE_HI_MASK U(3)
/* TZDRAM carveout configuration registers */ /* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 0x74 #define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 0x9BC #define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */ /* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978 #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO 0x648 #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB 0x64C #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
/* /*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
* non-overlapping Video memory region * non-overlapping Video memory region
*/ */
#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
#define MC_TZRAM_CARVEOUT_CFG 0x2190 #define MC_TZRAM_CARVEOUT_CFG U(0x2190)
#define MC_TZRAM_BASE_LO 0x2194 #define MC_TZRAM_BASE_LO U(0x2194)
#define MC_TZRAM_BASE_HI 0x2198 #define MC_TZRAM_BASE_HI U(0x2198)
#define MC_TZRAM_SIZE 0x219C #define MC_TZRAM_SIZE U(0x219C)
#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 #define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0)
/******************************************************************************* /*******************************************************************************
* Tegra UART Controller constants * Tegra UART Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_UARTA_BASE 0x03100000 #define TEGRA_UARTA_BASE U(0x03100000)
#define TEGRA_UARTB_BASE 0x03110000 #define TEGRA_UARTB_BASE U(0x03110000)
#define TEGRA_UARTC_BASE 0x0C280000 #define TEGRA_UARTC_BASE U(0x0C280000)
#define TEGRA_UARTD_BASE 0x03130000 #define TEGRA_UARTD_BASE U(0x03130000)
#define TEGRA_UARTE_BASE 0x03140000 #define TEGRA_UARTE_BASE U(0x03140000)
#define TEGRA_UARTF_BASE 0x03150000 #define TEGRA_UARTF_BASE U(0x03150000)
#define TEGRA_UARTG_BASE 0x0C290000 #define TEGRA_UARTG_BASE U(0x0C290000)
/******************************************************************************* /*******************************************************************************
* Tegra Fuse Controller related constants * Tegra Fuse Controller related constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_FUSE_BASE 0x03820000 #define TEGRA_FUSE_BASE U(0x03820000)
#define OPT_SUBREVISION 0x248 #define OPT_SUBREVISION U(0x248)
#define SUBREVISION_MASK 0xFF #define SUBREVISION_MASK U(0xFF)
/******************************************************************************* /*******************************************************************************
* GICv2 & interrupt handling related constants * GICv2 & interrupt handling related constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_GICD_BASE 0x03881000 #define TEGRA_GICD_BASE U(0x03881000)
#define TEGRA_GICC_BASE 0x03882000 #define TEGRA_GICC_BASE U(0x03882000)
/******************************************************************************* /*******************************************************************************
* Security Engine related constants * Security Engine related constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_SE0_BASE 0x03AC0000 #define TEGRA_SE0_BASE U(0x03AC0000)
#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
#define TEGRA_PKA1_BASE 0x03AD0000 #define TEGRA_PKA1_BASE U(0x03AD0000)
#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
#define TEGRA_RNG1_BASE 0x03AE0000 #define TEGRA_RNG1_BASE U(0x03AE0000)
#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
/******************************************************************************* /*******************************************************************************
* Tegra Clock and Reset Controller constants * Tegra Clock and Reset Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x05000000 #define TEGRA_CAR_RESET_BASE U(0x05000000)
/******************************************************************************* /*******************************************************************************
* Tegra micro-seconds timer constants * Tegra micro-seconds timer constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TMRUS_BASE 0x0C2E0000 #define TEGRA_TMRUS_BASE U(0x0C2E0000)
#define TEGRA_TMRUS_SIZE 0x1000 #define TEGRA_TMRUS_SIZE U(0x1000)
/******************************************************************************* /*******************************************************************************
* Tegra Power Mgmt Controller constants * Tegra Power Mgmt Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_PMC_BASE 0x0C360000 #define TEGRA_PMC_BASE U(0x0C360000)
/******************************************************************************* /*******************************************************************************
* Tegra scratch registers constants * Tegra scratch registers constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_SCRATCH_BASE 0x0C390000 #define TEGRA_SCRATCH_BASE U(0x0C390000)
#define SECURE_SCRATCH_RSV1_LO 0x658 #define SECURE_SCRATCH_RSV1_LO U(0x658)
#define SECURE_SCRATCH_RSV1_HI 0x65C #define SECURE_SCRATCH_RSV1_HI U(0x65C)
#define SECURE_SCRATCH_RSV6 0x680 #define SECURE_SCRATCH_RSV6 U(0x680)
#define SECURE_SCRATCH_RSV11_LO 0x6A8 #define SECURE_SCRATCH_RSV11_LO U(0x6A8)
#define SECURE_SCRATCH_RSV11_HI 0x6AC #define SECURE_SCRATCH_RSV11_HI U(0x6AC)
#define SECURE_SCRATCH_RSV53_LO 0x7F8 #define SECURE_SCRATCH_RSV53_LO U(0x7F8)
#define SECURE_SCRATCH_RSV53_HI 0x7FC #define SECURE_SCRATCH_RSV53_HI U(0x7FC)
#define SECURE_SCRATCH_RSV54_HI 0x804 #define SECURE_SCRATCH_RSV54_HI U(0x804)
#define SECURE_SCRATCH_RSV55_LO 0x808 #define SECURE_SCRATCH_RSV55_LO U(0x808)
#define SECURE_SCRATCH_RSV55_HI 0x80C #define SECURE_SCRATCH_RSV55_HI U(0x80C)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Mapped Control Register Access constants * Tegra Memory Mapped Control Register Access constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000 #define TEGRA_MMCRAB_BASE U(0x0E000000)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Mapped Activity Monitor Register Access constants * Tegra Memory Mapped Activity Monitor Register Access constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
/******************************************************************************* /*******************************************************************************
* Tegra SMMU Controller constants * Tegra SMMU Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_SMMU0_BASE 0x12000000 #define TEGRA_SMMU0_BASE U(0x12000000)
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TZRAM_BASE 0x30000000 #define TEGRA_TZRAM_BASE U(0x30000000)
#define TEGRA_TZRAM_SIZE 0x40000 #define TEGRA_TZRAM_SIZE U(0x40000)
#endif /* __TEGRA_DEF_H__ */ #endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 70cb692e
...@@ -7,13 +7,15 @@ ...@@ -7,13 +7,15 @@
#ifndef __TEGRA_DEF_H__ #ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__ #define __TEGRA_DEF_H__
#include <utils_def.h>
/******************************************************************************* /*******************************************************************************
* Power down state IDs * Power down state IDs
******************************************************************************/ ******************************************************************************/
#define PSTATE_ID_CORE_POWERDN 7 #define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_CLUSTER_IDLE 16 #define PSTATE_ID_CLUSTER_IDLE U(16)
#define PSTATE_ID_CLUSTER_POWERDN 17 #define PSTATE_ID_CLUSTER_POWERDN U(17)
#define PSTATE_ID_SOC_POWERDN 27 #define PSTATE_ID_SOC_POWERDN U(27)
/******************************************************************************* /*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
...@@ -27,26 +29,26 @@ ...@@ -27,26 +29,26 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/ ******************************************************************************/
#define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
******************************************************************************/ ******************************************************************************/
#define TEGRA_GICD_BASE 0x50041000 #define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE 0x50042000 #define TEGRA_GICC_BASE U(0x50042000)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Select Switch Controller constants * Tegra Memory Select Switch Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MSELECT_BASE 0x50060000 #define TEGRA_MSELECT_BASE U(0x50060000)
#define MSELECT_CONFIG 0x0 #define MSELECT_CONFIG U(0x0)
#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
UNSUPPORTED_TX_ERR_MASTER1_BIT) UNSUPPORTED_TX_ERR_MASTER1_BIT)
#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
...@@ -56,68 +58,68 @@ ...@@ -56,68 +58,68 @@
/******************************************************************************* /*******************************************************************************
* Tegra micro-seconds timer constants * Tegra micro-seconds timer constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TMRUS_BASE 0x60005010 #define TEGRA_TMRUS_BASE U(0x60005010)
#define TEGRA_TMRUS_SIZE 0x1000 #define TEGRA_TMRUS_SIZE U(0x1000)
/******************************************************************************* /*******************************************************************************
* Tegra Clock and Reset Controller constants * Tegra Clock and Reset Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x60006000 #define TEGRA_CAR_RESET_BASE U(0x60006000)
/******************************************************************************* /*******************************************************************************
* Tegra Flow Controller constants * Tegra Flow Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_FLOWCTRL_BASE 0x60007000 #define TEGRA_FLOWCTRL_BASE U(0x60007000)
/******************************************************************************* /*******************************************************************************
* Tegra Secure Boot Controller constants * Tegra Secure Boot Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_SB_BASE 0x6000C200 #define TEGRA_SB_BASE U(0x6000C200)
/******************************************************************************* /*******************************************************************************
* Tegra Exception Vectors constants * Tegra Exception Vectors constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_EVP_BASE 0x6000F000 #define TEGRA_EVP_BASE U(0x6000F000)
/******************************************************************************* /*******************************************************************************
* Tegra Miscellaneous register constants * Tegra Miscellaneous register constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE 0x70000000 #define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET 0x804 #define HARDWARE_REVISION_OFFSET U(0x804)
/******************************************************************************* /*******************************************************************************
* Tegra UART controller base addresses * Tegra UART controller base addresses
******************************************************************************/ ******************************************************************************/
#define TEGRA_UARTA_BASE 0x70006000 #define TEGRA_UARTA_BASE U(0x70006000)
#define TEGRA_UARTB_BASE 0x70006040 #define TEGRA_UARTB_BASE U(0x70006040)
#define TEGRA_UARTC_BASE 0x70006200 #define TEGRA_UARTC_BASE U(0x70006200)
#define TEGRA_UARTD_BASE 0x70006300 #define TEGRA_UARTD_BASE U(0x70006300)
#define TEGRA_UARTE_BASE 0x70006400 #define TEGRA_UARTE_BASE U(0x70006400)
/******************************************************************************* /*******************************************************************************
* Tegra Power Mgmt Controller constants * Tegra Power Mgmt Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_PMC_BASE 0x7000E400 #define TEGRA_PMC_BASE U(0x7000E400)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Controller constants * Tegra Memory Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE U(0x70019000)
/* TZDRAM carveout configuration registers */ /* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 0x74 #define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 0x9BC #define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */ /* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978 #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO 0x648 #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000 #define TEGRA_TZRAM_BASE U(0x7C010000)
#define TEGRA_TZRAM_SIZE 0x10000 #define TEGRA_TZRAM_SIZE U(0x10000)
#endif /* __TEGRA_DEF_H__ */ #endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/tegra_private.h
View file @ 70cb692e
...@@ -15,8 +15,8 @@ ...@@ -15,8 +15,8 @@
/******************************************************************************* /*******************************************************************************
* Tegra DRAM memory base address * Tegra DRAM memory base address
******************************************************************************/ ******************************************************************************/
#define TEGRA_DRAM_BASE 0x80000000ULL #define TEGRA_DRAM_BASE ULL(0x80000000)
#define TEGRA_DRAM_END 0x27FFFFFFFULL #define TEGRA_DRAM_END ULL(0x27FFFFFFF)
/******************************************************************************* /*******************************************************************************
* Struct for parameters received from BL2 * Struct for parameters received from BL2
......
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