Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1

This patch fixes the following MISRA violations:

Rule 8.6: Externally-linked object or function has "no" definition(s).
Rule 11.1: A cast shall not convert a pointer to a function to
any other type.

Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/include/t186/tegra186_private.h

+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TEGRA186_PRIVATE_H
+#define TEGRA186_PRIVATE_H
+
+void tegra186_cpu_reset_handler(void);
+uint64_t tegra186_get_cpu_reset_handler_base(void);
+uint64_t tegra186_get_cpu_reset_handler_size(void);
+
+#endif /* TEGRA186_PRIVATE_H */

plat/nvidia/tegra/soc/t186/plat_secondary.c

@@ -11,6 +11,7 @@
 #include <lib/mmio.h>
 
 #include <mce.h>
+#include <tegra186_private.h>
 #include <tegra_def.h>
 #include <tegra_private.h>
 
@@ -24,9 +25,6 @@
 
 extern void memcpy16(void *dest, const void *src, unsigned int length);
 
-extern uint64_t tegra_bl31_phys_base;
-extern uint64_t __tegra186_cpu_reset_handler_end;
-
 /*******************************************************************************
  * Setup secondary CPU vectors
  ******************************************************************************/
@@ -34,29 +32,24 @@ void plat_secondary_setup(void)
 {
 	uint32_t addr_low, addr_high;
 	const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	uint64_t cpu_reset_handler_base;
+	uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
 
 	INFO("Setting up secondary CPU boot\n");
 
-	if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) &&
-	    (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) {
-
-		/*
-		 * The BL31 code resides in the TZSRAM which loses state
-		 * when we enter System Suspend. Copy the wakeup trampoline
-		 * code to TZDRAM to help us exit from System Suspend.
-		 */
-		cpu_reset_handler_base = params_from_bl2->tzdram_base;
-		memcpy16((void *)((uintptr_t)cpu_reset_handler_base),
-			 (void *)(uintptr_t)tegra186_cpu_reset_handler,
-			 (uintptr_t)&tegra186_cpu_reset_handler);
-
-	} else {
-		cpu_reset_handler_base = (uintptr_t)&tegra_secure_entrypoint;
-	}
-
-	addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
-	addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU);
+	/*
+	 * The BL31 code resides in the TZSRAM which loses state
+	 * when we enter System Suspend. Copy the wakeup trampoline
+	 * code to TZDRAM to help us exit from System Suspend.
+	 */
+	cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base();
+	cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size();
+	(void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base,
+			(const void *)(uintptr_t)cpu_reset_handler_base,
+			cpu_reset_handler_size);
+
+	/* TZDRAM base will be used as the "resume" address */
+	addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
+	addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
 
 	/* write lower 32 bits first, then the upper 11 bits */
 	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);

plat/nvidia/tegra/soc/t186/plat_trampoline.S

@@ -80,3 +80,20 @@ __tegra186_smmu_context:
 	.align 4
 	.globl	__tegra186_cpu_reset_handler_end
 __tegra186_cpu_reset_handler_end:
+
+	.globl tegra186_get_cpu_reset_handler_size
+	.globl tegra186_get_cpu_reset_handler_base
+
+/* return size of the CPU reset handler */
+func tegra186_get_cpu_reset_handler_size
+	adr	x0, __tegra186_cpu_reset_handler_end
+	adr	x1, tegra186_cpu_reset_handler
+	sub	x0, x0, x1
+	ret
+endfunc tegra186_get_cpu_reset_handler_size
+
+/* return the start address of the CPU reset handler */
+func tegra186_get_cpu_reset_handler_base
+	adr	x0, tegra186_cpu_reset_handler
+	ret
+endfunc tegra186_get_cpu_reset_handler_base