Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0

Arm/master/update rcar 2.0.0

drivers/renesas/rcar/auth/auth_mod.c

@@ -113,7 +113,7 @@ verify_image:
 	}
 #if RCAR_BL2_DCACHE == 1
 	/* clean and disable */
-	write_sctlr_el1(read_sctlr_el1() & ~SCTLR_C_BIT);
+	write_sctlr_el3(read_sctlr_el3() & ~SCTLR_C_BIT);
 	dcsw_op_all(DCCISW);
 #endif
 	ret = (mmio_read_32(RCAR_BOOT_KEY_CERT_NEW) == RCAR_CERT_MAGIC_NUM) ?
@@ -124,7 +124,7 @@ verify_image:
 
 #if RCAR_BL2_DCACHE == 1
 	/* enable */
-	write_sctlr_el1(read_sctlr_el1() | SCTLR_C_BIT);
+	write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
 #endif
 
 #endif

drivers/renesas/rcar/cpld/ulcb_cpld.c

@@ -5,6 +5,7 @@
  */
 
 #include <lib/mmio.h>
+#include "ulcb_cpld.h"
 
 #define SCLK			8	/* GP_6_8 */
 #define SSTBZ			3	/* GP_2_3 */

drivers/renesas/rcar/cpld/ulcb_cpld.h

+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_ULCB_CPLD_H__
+#define RCAR_ULCB_CPLD_H__
+
+extern void rcar_cpld_reset_cpu(void);
+
+#endif /* RCAR_ULCB_CPLD_H__ */

drivers/renesas/rcar/delay/micro_delay.S

-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include "micro_delay.h"
-
-#define CPG_BASE		(0xE6150000)
-#define CPG_SMSTPCR1		(0x0134)
-#define CPG_CPGWPR		(0x0900)
-
-/* Module bit for TMU ch3-5 */
-#define MSTPCR1_TMU1		(1 << 24)
-
-#define TMU3_BASE		(0xE6FC0000)
-#define TMU_TSTR		(0x0004)
-#define TMU_TCOR		(0x0008)
-#define TMU_TCNT		(0x000C)
-#define TMU_TCR		(0x0010)
-/* Start bit for TMU ch3 */
-#define TSTR1_TMU3		(1 << 0)
-
-#define MIDR_CA57		(0x0D07 << MIDR_PN_SHIFT)
-#define MIDR_CA53		(0x0D03 << MIDR_PN_SHIFT)
-
-	.globl	rcar_micro_delay
-#if (TMU3_MEASUREMENT == 1)
-	.globl	tmu3_init
-	.globl	tmu3_start
-	.globl	tmu3_stop
-	.globl	tcnt3_snapshot
-#endif
-	/* Aligned with the cache line */
-	.align	6
-
-func rcar_micro_delay
-	cbz	x0, micro_delay_e
-	mrs	x1, midr_el1
-	and	x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
-	mov	w2, #MIDR_CA53
-	cmp	w1, w2
-	b.eq	micro_delay_ca53
-	b	micro_delay_ca57
-micro_delay_e:
-	ret
-endfunc rcar_micro_delay
-
-func micro_delay_ca57
-ca57_loop_1:
-	mov	x1, #185
-ca57_loop_2:
-	subs	x1, x1, #1
-	b.ne	ca57_loop_2
-	subs	x0, x0, #1
-	b.ne	ca57_loop_1
-	ret
-endfunc micro_delay_ca57
-
-func micro_delay_ca53
-ca53_loop_1:
-	mov	x1, #134
-ca53_loop_2:
-	subs	x1, x1, #1
-	b.ne	ca53_loop_2
-	subs	x0, x0, #1
-	b.ne	ca53_loop_1
-	ret
-endfunc micro_delay_ca53
-
-#if (TMU3_MEASUREMENT == 1)
-func tmu3_init
-	ldr	x2, =CPG_BASE
-	ldr	w0, [x2, #CPG_SMSTPCR1]
-	ldr	w1, [x2, #CPG_MSTPSR1]
-	ldr	w2, #MSTPCR1_TMU1
-	bl	mstpcr_write
-	ret
-endfunc tmu3_init
-
-func tmu3_start
-	ldr	x0, =TMU3_BASE
-	mov	w1, #0xFFFFFFFF
-	str	w1, [x0, TMU_TCNT]
-
-	ldr	x0, =TMU3_BASE
-	ldrb	w1, [x0, TMU_TSTR]
-	orr	w1, w1, #TSTR1_TMU3
-	strb	w1, [x0, TMU_TSTR]
-	ret
-endfunc tmu3_start
-
-func tcnt3_snapshot
-	ldr	x0, =TMU3_BASE
-	ldr	w0, [x0, TMU_TCNT]
-	ret
-endfunc tcnt3_snapshot
-
-
-func tmu3_stop
-	ldr	x0, =TMU3_BASE
-	ldrb	w1, [x0, TMU_TSTR]
-	and	w1, w1, #~TSTR1_TMU3
-	strb	w1, [x0, TMU_TSTR]
-	ret
-endfunc tmu3_stop
-#endif

drivers/renesas/rcar/delay/micro_delay.c

+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include "micro_delay.h"
+
+#define RCAR_CONV_MICROSEC		1000000U
+
+void
+#if IMAGE_BL31
+	__attribute__ ((section (".system_ram")))
+#endif
+	rcar_micro_delay(uint64_t micro_sec)
+{
+	uint64_t freq;
+	uint64_t base_count;
+	uint64_t get_count;
+	uint64_t wait_time = 0U;
+
+	freq = read_cntfrq_el0();
+	base_count = read_cntpct_el0();
+	while (micro_sec > wait_time) {
+		get_count = read_cntpct_el0();
+		wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq;
+	}
+}

drivers/renesas/rcar/delay/micro_delay.h

@@ -7,20 +7,9 @@
 #ifndef MICRO_DELAY_H
 #define MICRO_DELAY_H
 
-#define TMU3_MEASUREMENT	(0)
-
 #ifndef __ASSEMBLY__
 #include <stdint.h>
-void rcar_micro_delay(uint32_t count_us);
-
-#if (TMU3_MEASUREMENT == 1)
-void tmu3_start(void);
-void tmu3_init(void);
-void tmu3_stop(void);
-
-uint32_t tcnt3_snapshot(void);
-#endif
-
+void rcar_micro_delay(uint64_t micro_sec);
 #endif
 
 #endif /* MICRO_DELAY_H */

drivers/renesas/rcar/pwrc/pwrc.c

@@ -17,6 +17,7 @@
 #include "iic_dvfs.h"
 #include "rcar_def.h"
 #include "rcar_private.h"
+#include "micro_delay.h"
 #include "pwrc.h"
 
 /*
@@ -122,7 +123,6 @@ RCAR_INSTANTIATE_LOCK
 #define	RST_BASE				(0xE6160000U)
 #define	RST_MODEMR				(RST_BASE + 0x0060U)
 #define	RST_MODEMR_BIT0				(0x00000001U)
-#define RCAR_CONV_MICROSEC			(1000000U)
 
 #if PMIC_ROHM_BD9571
 #define	BIT_BKUP_CTRL_OUT			((uint8_t)(1U << 4))
@@ -143,23 +143,6 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
 #endif
 
-#if RCAR_SYSTEM_SUSPEND
-static void __attribute__ ((section (".system_ram")))
-	rcar_pwrc_micro_delay(uint64_t micro_sec)
-{
-	uint64_t freq, base, val;
-	uint64_t wait_time = 0;
-
-	freq = read_cntfrq_el0();
-	base = read_cntpct_el0();
-
-	while (micro_sec > wait_time) {
-		val = read_cntpct_el0() - base;
-		wait_time = val * RCAR_CONV_MICROSEC / freq;
-	}
-}
-#endif
-
 uint32_t rcar_pwrc_status(uint64_t mpidr)
 {
 	uint32_t ret = 0;
@@ -414,7 +397,7 @@ self_refresh:
 	mmio_write_32(DBSC4_REG_DBACEN, 0);
 
 	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
-		rcar_pwrc_micro_delay(100);
+		rcar_micro_delay(100);
 	else if (product == RCAR_PRODUCT_H3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
@@ -465,7 +448,7 @@ self_refresh:
 
 	/* Set the auto-refresh enable register */
 	mmio_write_32(DBSC4_REG_DBRFEN, 0U);
-	rcar_pwrc_micro_delay(1U);
+	rcar_micro_delay(1U);
 
 	if (product == RCAR_PRODUCT_M3)
 		return;
@@ -650,7 +633,6 @@ void rcar_pwrc_set_suspend_to_ram(void)
 				       DEVICE_SRAM_STACK_SIZE);
 	uint32_t sctlr;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
 
 	/* disable MMU */
@@ -665,10 +647,7 @@ void rcar_pwrc_init_suspend_to_ram(void)
 {
 #if PMIC_ROHM_BD9571
 	uint8_t mode;
-#endif
-	rcar_pwrc_code_copy_to_system_ram();
 
-#if PMIC_ROHM_BD9571
 	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
 		panic();
 
@@ -683,7 +662,6 @@ void rcar_pwrc_suspend_to_ram(void)
 #if RCAR_SYSTEM_RESET_KEEPON_DDR
 	int32_t error;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
 	if (error) {
 		ERROR("Failed send KEEP10 init ret=%d \n", error);

drivers/renesas/rcar/scif/scif.S

@@ -75,6 +75,8 @@
 #if SCIF_CLK == SCIF_EXTARNAL_CLK
 #define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_BRG)
 #else
+#define	SCFSR_TEND_MASK		(1 << 6)
+#define	SCFSR_TEND_TRANS_END	(0x0040)
 #define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_INT)
 #endif
 #define	SCFSR_INIT_DATA		(0x0000)
@@ -281,6 +283,11 @@ func console_core_putc
 	bcs	2b
 	strb	w0, [x1, #SCIF_SCFTDR]
 
+	/* Clear TEND flag */
+	ldrh	w2, [x1, #SCIF_SCFSR]
+	and	w2, w2, #~SCFSR_TEND_MASK
+	strh	w2, [x1, #SCIF_SCFSR]
+
 	ret
 endfunc console_core_putc
 
@@ -309,16 +316,12 @@ endfunc console_getc
 func console_flush
 	ldr	x0, =SCIF2_BASE
 1:
-	ldrh	w1, [x0, #SCIF_SCFDR]
-	ubfx	w1, w1, #8, #5
-	cmp	w1, #0
+	/* Check TEND flag */
+	ldrh	w1, [x0, #SCIF_SCFSR]
+	and	w1, w1, #SCFSR_TEND_MASK
+	cmp	w1, #SCFSR_TEND_TRANS_END
 	bne	1b
 
-	mov x0, #100
-	mov x3, x30
-	bl rcar_micro_delay
-	mov x30, x3
-
 	ldr	x0, =SCIF2_BASE
 	ldrh	w1, [x0, #SCIF_SCSCR]
 	and	w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)

drivers/renesas/rcar/watchdog/swdt.c

@@ -133,7 +133,11 @@ void rcar_swdt_release(void)
 	    (ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
 	uint32_t i;
 
+	/* Disable FIQ interrupt */
 	write_daifset(DAIF_FIQ_BIT);
+	/* FIQ interrupts are not taken to EL3 */
+	write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT);
+
 	swdt_disable();
 	gicv2_cpuif_disable();
 

drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h

@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#define RCAR_E3_DDR_VERSION    "rev.0.09"
+#define RCAR_E3_DDR_VERSION    "rev.0.11"
 
 #ifdef ddr_qos_init_setting
    #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c

@@ -4,24 +4,33 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define BOARDNUM 16
+#define BOARDNUM 18
 #define BOARD_JUDGE_AUTO
 
+#ifdef BOARD_JUDGE_AUTO
 static uint32_t _board_judge(void);
 
 static uint32_t boardcnf_get_brd_type(void)
 {
 	return _board_judge();
 }
+#else
+static uint32_t boardcnf_get_brd_type(void)
+{
+	return (1);
+}
+#endif
+
+#define DDR_FAST_INIT
 
 struct _boardcnf_ch {
 	uint8_t ddr_density[CS_CNT];
-	uint32_t ca_swap;
+	uint64_t ca_swap;
 	uint16_t dqs_swap;
 	uint32_t dq_swap[SLICE_CNT];
 	uint8_t dm_swap[SLICE_CNT];
 	uint16_t wdqlvl_patt[16];
-	int8_t cacs_adj[10];
+	int8_t cacs_adj[16];
 	int8_t dm_adj_w[SLICE_CNT];
 	int8_t dq_adj_w[SLICE_CNT * 8];
 	int8_t dm_adj_r[SLICE_CNT];
@@ -876,7 +885,11 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0x0a0,
 	 {
 	  {
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+	   {0x04, 0x04},
+#else
 	   {0x02, 0x02},
+#endif
 	   0x00342501,
 	   0x3201,
 	   {0x10672534, 0x43257106, 0x34527601, 0x71605243},
@@ -1227,7 +1240,89 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   }
 	  }
+	 },
+/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x0320,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x04, 0x04},
+	    0x314250FFFF312405,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
+	{
+	 0x01,
+	 0x01,
+	 0x0300,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	  }
 	 }
+	}
 };
 
 void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@@ -1258,6 +1353,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
 			break;
 		}
 	}
+	(void)brd;
 }
 
 void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
@@ -1284,6 +1380,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
 		*div = 1;
 		break;
 	}
+	(void)brd;
 }
 
 #define _def_REFPERIOD  1890
@@ -1393,10 +1490,10 @@ static uint32_t opencheck_SSI_WS6(void)
 	if (down == up) {
 		/* Same = Connect */
 		return 0;
+	} else {
+		/* Diff = Open */
+		return 1;
 	}
-
-	/* Diff = Open */
-	return 1;
 }
 
 #endif
@@ -1431,6 +1528,7 @@ static uint32_t _board_judge(void)
 	usb2_ovc_open = opencheck_SSI_WS6();
 
 	/* RENESAS Eva-borad */
+	brd = 99;
 	if (Prr_Product == PRR_PRODUCT_V3H) {
 		/* RENESAS Condor board */
 		brd = 12;
@@ -1441,10 +1539,12 @@ static uint32_t _board_judge(void)
 		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS Kriek board with M3-W */
 			brd = 1;
-		} else if (Prr_Cut <= PRR_PRODUCT_11) {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut<=PRR_PRODUCT_11)) {
 			/* RENESAS Kriek board with PM3 */
 			brd = 13;
-		} else {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut > PRR_PRODUCT_20)) {
 			/* RENESAS Kriek board with H3N */
 			brd = 15;
 		}
@@ -1467,12 +1567,13 @@ static uint32_t _board_judge(void)
 		} else if (Prr_Product == PRR_PRODUCT_M3N) {
 			/* RENESAS SALVATOR-X (M3-N/SIP) */
 			brd = 11;
-		} else {
+		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS SALVATOR-X (M3-W/SIP) */
 			brd = 0;
 		}
 	}
 #endif
+
 	return brd;
 }
 #endif

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION        "rev.0.33"
+#define RCAR_DDR_VERSION        "rev.0.34"
 #define DRAM_CH_CNT		(0x04)
 #define SLICE_CNT		(0x04)
 #define CS_CNT			(0x02)

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h

@@ -267,7 +267,7 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
 /*0bb9*/ 0x00000000,
 /*0bba*/ 0x00000000,
 /*0bbb*/ 0x00000000,
-/*0bbc*/ 0x00000065,
+/*0bbc*/ 0x00000265,
 /*0bbd*/ 0x00000000,
 /*0bbe*/ 0x00040401,
 /*0bbf*/ 0x00000000,

drivers/staging/renesas/rcar/ddr/dram_sub_func.c

@@ -19,10 +19,11 @@
 #define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
 
 #if RCAR_SYSTEM_SUSPEND
-#include "iic_dvfs.h"
-
+/* Local defines */
 #define DRAM_BACKUP_GPIO_USE		(0)
+#include "iic_dvfs.h"
 #if PMIC_ROHM_BD9571
+#define	PMIC_SLAVE_ADDR			(0x30U)
 #define	PMIC_BKUP_MODE_CNT		(0x20U)
 #define	PMIC_QLLM_CNT			(0x27U)
 #define	BIT_BKUP_CTRL_OUT		((uint8_t)(1U << 4U))
@@ -52,40 +53,53 @@
 void rcar_dram_get_boot_status(uint32_t * status)
 {
 #if RCAR_SYSTEM_SUSPEND
-	uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
-	uint32_t gpio = GPIO_INDT1;
-	uint32_t reg, product;
 
-	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	uint32_t reg_data;
+	uint32_t product;
+	uint32_t shift;
+	uint32_t gpio;
 
+	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	if (product == PRR_PRODUCT_V3H) {
 		shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
 		gpio = GPIO_INDT3;
 	} else if (product == PRR_PRODUCT_E3) {
 		shift = GPIO_BKUP_TRG_SHIFT_EBISU;
 		gpio = GPIO_INDT6;
+	} else {
+		shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+		gpio = GPIO_INDT1;
 	}
 
-	reg = mmio_read_32(gpio) & (1U << shift);
-	*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
-#else
+	reg_data = mmio_read_32(gpio);
+	if (0U != (reg_data & ((uint32_t)1U << shift))) {
+		*status = DRAM_BOOT_STATUS_WARM;
+	} else {
+		*status = DRAM_BOOT_STATUS_COLD;
+	}
+#else	/* RCAR_SYSTEM_SUSPEND */
 	*status = DRAM_BOOT_STATUS_COLD;
-#endif
+#endif	/* RCAR_SYSTEM_SUSPEND */
 }
 
 int32_t rcar_dram_update_boot_status(uint32_t status)
 {
 	int32_t ret = 0;
 #if RCAR_SYSTEM_SUSPEND
+	uint32_t reg_data;
 #if PMIC_ROHM_BD9571
 #if DRAM_BACKUP_GPIO_USE == 0
-	uint8_t mode = 0U;
+	uint8_t bkup_mode_cnt = 0U;
 #else
 	uint32_t reqb, outd;
 #endif
-	uint8_t qllm = 0;
+	uint8_t qllm_cnt = 0U;
+	int32_t i2c_dvfs_ret = -1;
 #endif
-	uint32_t i, product, trg, gpio;
+	uint32_t loop_count;
+	uint32_t product;
+	uint32_t trg;
+	uint32_t gpio;
 
 	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	if (product == PRR_PRODUCT_V3H) {
@@ -111,50 +125,58 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
 		gpio = GPIO_INDT1;
 	}
 
-	if (status != DRAM_BOOT_STATUS_WARM)
-		goto cold;
-
+	if (status == DRAM_BOOT_STATUS_WARM) {
 #if DRAM_BACKUP_GPIO_USE==1
 	mmio_setbits_32(outd, 1U << reqb);
 #else
-
 #if PMIC_ROHM_BD9571
-	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
-		ERROR("BKUP mode cnt READ ERROR.\n");
-		return DRAM_UPDATE_STATUS_ERR;
-	}
-
-	mode &= ~BIT_BKUP_CTRL_OUT;
-	if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
-		ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
-		return DRAM_UPDATE_STATUS_ERR;
+		/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
+		i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
+				PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
+		if (0 != i2c_dvfs_ret) {
+			ERROR("BKUP mode cnt READ ERROR.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		} else {
+			bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
+			i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
+					PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
+			if (0 != i2c_dvfs_ret) {
+				ERROR("BKUP mode cnt WRITE ERROR. "
+					"value = %d\n", bkup_mode_cnt);
+				ret = DRAM_UPDATE_STATUS_ERR;
+			}
+		}
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* DRAM_BACKUP_GPIO_USE==1 */
+		/* Wait BKUP_TRG=Low */
+		loop_count = DRAM_BKUP_TRG_LOOP_CNT;
+		while (0U < loop_count) {
+			reg_data = mmio_read_32(gpio);
+			if ((reg_data &
+				((uint32_t)1U << trg)) == 0U) {
+				break;
+			}
+			loop_count--;
+		}
+		if (0U == loop_count) {
+			ERROR(	"\nWarm booting...\n" \
+				" The potential of BKUP_TRG did not switch " \
+				"to Low.\n If you expect the operation of " \
+				"cold boot,\n check the board configuration" \
+				" (ex, Dip-SW) and/or the H/W failure.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
-#endif
-#endif
-	for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
-		if (mmio_read_32(gpio) & (1U << trg))
-			continue;
-
-		goto cold;
-	}
-
-	ERROR("\nWarm booting Error...\n"
-	      " The potential of BKUP_TRG did not switch "
-	      "to Low.\n If you expect the operation of "
-	      "cold boot,\n check the board configuration"
-	      " (ex, Dip-SW) and/or the H/W failure.\n");
-
-	return DRAM_UPDATE_STATUS_ERR;
-
-cold:
 #if PMIC_ROHM_BD9571
-	if (ret)
-		return ret;
-
-	qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
-	if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
-		ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
-		ret = DRAM_UPDATE_STATUS_ERR;
+	if(0 == ret) {
+		qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+		i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
+				PMIC_QLLM_CNT, qllm_cnt);
+		if (0 != i2c_dvfs_ret) {
+			ERROR("QLLM cnt WRITE ERROR. "
+				"value = %d\n", qllm_cnt);
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
 #endif
 #endif

drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c

@@ -490,7 +490,8 @@ void pfc_init_e3(void)
 		      | MOD_SEL0_REMOCON_A
 		      | MOD_SEL0_SCIF_A
 		      | MOD_SEL0_SCIF0_A
-		      | MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
+		      | MOD_SEL0_SCIF2_A
+		      | MOD_SEL0_SPEED_PULSE_IF_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
 		      | MOD_SEL1_SSI2_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -507,135 +508,137 @@ void pfc_init_e3(void)
 		      | MOD_SEL1_SCIF4_A
 		      | MOD_SEL1_SCIF5_A
 		      | MOD_SEL1_VIN4_A
-		      | MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
+		      | MOD_SEL1_VIN5_A
+		      | MOD_SEL1_ADGC_A
+		      | MOD_SEL1_SSI9_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)	/* QSPI1_MISO/IO1 */
-		      |IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
-		      |IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
-		      |IPSR_16_FUNC(0)	/* QSPI0_IO3 */
-		      |IPSR_12_FUNC(0)	/* QSPI0_IO2 */
-		      |IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
-		      |IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
-		      |IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+		      | IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
+		      | IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
+		      | IPSR_16_FUNC(0)	/* QSPI0_IO3 */
+		      | IPSR_12_FUNC(0)	/* QSPI0_IO2 */
+		      | IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
+		      | IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
+		      | IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
 	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)	/* AVB_RD2 */
-		      |IPSR_24_FUNC(0)	/* AVB_RD1 */
-		      |IPSR_20_FUNC(0)	/* AVB_RD0 */
-		      |IPSR_16_FUNC(0)	/* RPC_RESET# */
-		      |IPSR_12_FUNC(0)	/* RPC_INT# */
-		      |IPSR_8_FUNC(0)	/* QSPI1_SSL */
-		      |IPSR_4_FUNC(0)	/* QSPI1_IO3 */
-		      |IPSR_0_FUNC(0));	/* QSPI1_IO2 */
+		      | IPSR_24_FUNC(0)	/* AVB_RD1 */
+		      | IPSR_20_FUNC(0)	/* AVB_RD0 */
+		      | IPSR_16_FUNC(0)	/* RPC_RESET# */
+		      | IPSR_12_FUNC(0)	/* RPC_INT# */
+		      | IPSR_8_FUNC(0)	/* QSPI1_SSL */
+		      | IPSR_4_FUNC(0)	/* QSPI1_IO3 */
+		      | IPSR_0_FUNC(0));	/* QSPI1_IO2 */
 	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)	/* IRQ0 */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(2)	/* AVB_LINK */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)	/* AVB_MDC */
-		      |IPSR_4_FUNC(0)	/* AVB_MDIO */
-		      |IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+		      | IPSR_4_FUNC(0)	/* AVB_MDIO */
+		      | IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
 	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)	/* DU_HSYNC */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(5)	/* DU_DG4 */
-		      |IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
-		      |IPSR_4_FUNC(5)	/* DU_DISP */
-		      |IPSR_0_FUNC(1));	/* IRQ1 */
+		      | IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
+		      | IPSR_4_FUNC(5)	/* DU_DISP */
+		      | IPSR_0_FUNC(1));	/* IRQ1 */
 	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)	/* DU_DB5 */
-		      |IPSR_24_FUNC(5)	/* DU_DB4 */
-		      |IPSR_20_FUNC(5)	/* DU_DB3 */
-		      |IPSR_16_FUNC(5)	/* DU_DB2 */
-		      |IPSR_12_FUNC(5)	/* DU_DG6 */
-		      |IPSR_8_FUNC(5)	/* DU_VSYNC */
-		      |IPSR_4_FUNC(5)	/* DU_DG5 */
-		      |IPSR_0_FUNC(5));	/* DU_DG7 */
+		      | IPSR_24_FUNC(5)	/* DU_DB4 */
+		      | IPSR_20_FUNC(5)	/* DU_DB3 */
+		      | IPSR_16_FUNC(5)	/* DU_DB2 */
+		      | IPSR_12_FUNC(5)	/* DU_DG6 */
+		      | IPSR_8_FUNC(5)	/* DU_VSYNC */
+		      | IPSR_4_FUNC(5)	/* DU_DG5 */
+		      | IPSR_0_FUNC(5));	/* DU_DG7 */
 	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)	/* DU_DR3 */
-		      |IPSR_24_FUNC(5)	/* DU_DB7 */
-		      |IPSR_20_FUNC(5)	/* DU_DR2 */
-		      |IPSR_16_FUNC(5)	/* DU_DR1 */
-		      |IPSR_12_FUNC(5)	/* DU_DR0 */
-		      |IPSR_8_FUNC(5)	/* DU_DB1 */
-		      |IPSR_4_FUNC(5)	/* DU_DB0 */
-		      |IPSR_0_FUNC(5));	/* DU_DB6 */
+		      | IPSR_24_FUNC(5)	/* DU_DB7 */
+		      | IPSR_20_FUNC(5)	/* DU_DR2 */
+		      | IPSR_16_FUNC(5)	/* DU_DR1 */
+		      | IPSR_12_FUNC(5)	/* DU_DR0 */
+		      | IPSR_8_FUNC(5)	/* DU_DB1 */
+		      | IPSR_4_FUNC(5)	/* DU_DB0 */
+		      | IPSR_0_FUNC(5));	/* DU_DB6 */
 	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)	/* DU_DG1 */
-		      |IPSR_24_FUNC(5)	/* DU_DG0 */
-		      |IPSR_20_FUNC(5)	/* DU_DR7 */
-		      |IPSR_16_FUNC(2)	/* IRQ5 */
-		      |IPSR_12_FUNC(5)	/* DU_DR6 */
-		      |IPSR_8_FUNC(5)	/* DU_DR5 */
-		      |IPSR_4_FUNC(0)
+		      | IPSR_24_FUNC(5)	/* DU_DG0 */
+		      | IPSR_20_FUNC(5)	/* DU_DR7 */
+		      | IPSR_16_FUNC(2)	/* IRQ5 */
+		      | IPSR_12_FUNC(5)	/* DU_DR6 */
+		      | IPSR_8_FUNC(5)	/* DU_DR5 */
+		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(5));	/* DU_DR4 */
 	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)	/* SD0_CLK */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(5)	/* DU_DOTCLKIN0 */
-		      |IPSR_16_FUNC(5)	/* DU_DG3 */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_16_FUNC(5)	/* DU_DG3 */
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(5));	/* DU_DG2 */
 	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)	/* SD1_DAT0 */
-		      |IPSR_24_FUNC(0)	/* SD1_CMD */
-		      |IPSR_20_FUNC(0)	/* SD1_CLK */
-		      |IPSR_16_FUNC(0)	/* SD0_DAT3 */
-		      |IPSR_12_FUNC(0)	/* SD0_DAT2 */
-		      |IPSR_8_FUNC(0)	/* SD0_DAT1 */
-		      |IPSR_4_FUNC(0)	/* SD0_DAT0 */
-		      |IPSR_0_FUNC(0));	/* SD0_CMD */
+		      | IPSR_24_FUNC(0)	/* SD1_CMD */
+		      | IPSR_20_FUNC(0)	/* SD1_CLK */
+		      | IPSR_16_FUNC(0)	/* SD0_DAT3 */
+		      | IPSR_12_FUNC(0)	/* SD0_DAT2 */
+		      | IPSR_8_FUNC(0)	/* SD0_DAT1 */
+		      | IPSR_4_FUNC(0)	/* SD0_DAT0 */
+		      | IPSR_0_FUNC(0));	/* SD0_CMD */
 	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)	/* SD3_DAT2 */
-		      |IPSR_24_FUNC(0)	/* SD3_DAT1 */
-		      |IPSR_20_FUNC(0)	/* SD3_DAT0 */
-		      |IPSR_16_FUNC(0)	/* SD3_CMD */
-		      |IPSR_12_FUNC(0)	/* SD3_CLK */
-		      |IPSR_8_FUNC(0)	/* SD1_DAT3 */
-		      |IPSR_4_FUNC(0)	/* SD1_DAT2 */
-		      |IPSR_0_FUNC(0));	/* SD1_DAT1 */
+		      | IPSR_24_FUNC(0)	/* SD3_DAT1 */
+		      | IPSR_20_FUNC(0)	/* SD3_DAT0 */
+		      | IPSR_16_FUNC(0)	/* SD3_CMD */
+		      | IPSR_12_FUNC(0)	/* SD3_CLK */
+		      | IPSR_8_FUNC(0)	/* SD1_DAT3 */
+		      | IPSR_4_FUNC(0)	/* SD1_DAT2 */
+		      | IPSR_0_FUNC(0));	/* SD1_DAT1 */
 	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)	/* SD0_WP */
-		      |IPSR_24_FUNC(0)	/* SD0_CD */
-		      |IPSR_20_FUNC(0)	/* SD3_DS */
-		      |IPSR_16_FUNC(0)	/* SD3_DAT7 */
-		      |IPSR_12_FUNC(0)	/* SD3_DAT6 */
-		      |IPSR_8_FUNC(0)	/* SD3_DAT5 */
-		      |IPSR_4_FUNC(0)	/* SD3_DAT4 */
-		      |IPSR_0_FUNC(0));	/* SD3_DAT3 */
+		      | IPSR_24_FUNC(0)	/* SD0_CD */
+		      | IPSR_20_FUNC(0)	/* SD3_DS */
+		      | IPSR_16_FUNC(0)	/* SD3_DAT7 */
+		      | IPSR_12_FUNC(0)	/* SD3_DAT6 */
+		      | IPSR_8_FUNC(0)	/* SD3_DAT5 */
+		      | IPSR_4_FUNC(0)	/* SD3_DAT4 */
+		      | IPSR_0_FUNC(0));	/* SD3_DAT3 */
 	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(2)	/* AUDIO_CLKOUT1_A */
-		      |IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)	/* SD1_WP */
-		      |IPSR_0_FUNC(0));	/* SD1_CD */
+		      | IPSR_0_FUNC(0));	/* SD1_CD */
 	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(0)	/* RX2_A */
-		      |IPSR_8_FUNC(0)	/* TX2_A */
-		      |IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
-		      |IPSR_0_FUNC(0));
+		      | IPSR_8_FUNC(0)	/* TX2_A */
+		      | IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
+		      | IPSR_0_FUNC(0));
 	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(2)	/* AUDIO_CLKC_A */
-		      |IPSR_4_FUNC(1)	/* HTX2_A */
-		      |IPSR_0_FUNC(1));	/* HRX2_A */
+		      | IPSR_4_FUNC(1)	/* HTX2_A */
+		      | IPSR_0_FUNC(1));	/* HRX2_A */
 	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)	/* USB0_PWEN_B */
-		      |IPSR_24_FUNC(0)	/* SSI_SDATA4 */
-		      |IPSR_20_FUNC(0)	/* SSI_SDATA3 */
-		      |IPSR_16_FUNC(0)	/* SSI_WS349 */
-		      |IPSR_12_FUNC(0)	/* SSI_SCK349 */
-		      |IPSR_8_FUNC(0)
+		      | IPSR_24_FUNC(0)	/* SSI_SDATA4 */
+		      | IPSR_20_FUNC(0)	/* SSI_SDATA3 */
+		      | IPSR_16_FUNC(0)	/* SSI_WS349 */
+		      | IPSR_12_FUNC(0)	/* SSI_SCK349 */
+		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)	/* SSI_SDATA1 */
-		      |IPSR_0_FUNC(0));	/* SSI_SDATA0 */
+		      | IPSR_0_FUNC(0));	/* SSI_SDATA0 */
 	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)	/* USB30_OVC */
-		      |IPSR_24_FUNC(0)	/* USB30_PWEN */
-		      |IPSR_20_FUNC(0)	/* AUDIO_CLKA */
-		      |IPSR_16_FUNC(1)	/* HRTS2#_A */
-		      |IPSR_12_FUNC(1)	/* HCTS2#_A */
-		      |IPSR_8_FUNC(0)
+		      | IPSR_24_FUNC(0)	/* USB30_PWEN */
+		      | IPSR_20_FUNC(0)	/* AUDIO_CLKA */
+		      | IPSR_16_FUNC(1)	/* HRTS2#_A */
+		      | IPSR_12_FUNC(1)	/* HCTS2#_A */
+		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(3));	/* USB0_OVC_B */
 
@@ -648,7 +651,11 @@ void pfc_init_e3(void)
 		      | GPSR0_D8
 		      | GPSR0_D7
 		      | GPSR0_D6
-		      | GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
+		      | GPSR0_D5
+		      | GPSR0_D3
+		      | GPSR0_D2
+		      | GPSR0_D1
+		      | GPSR0_D0);
 	pfc_reg_write(PFC_GPSR1, GPSR1_WE0
 		      | GPSR1_CS0
 		      | GPSR1_A19
@@ -663,7 +670,11 @@ void pfc_init_e3(void)
 		      | GPSR1_A10
 		      | GPSR1_A9
 		      | GPSR1_A8
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
 		      | GPSR2_BIT26_REVERCED
 		      | GPSR2_RD
@@ -687,7 +698,8 @@ void pfc_init_e3(void)
 		      | GPSR2_QSPI0_IO3
 		      | GPSR2_QSPI0_IO2
 		      | GPSR2_QSPI0_MISO_IO1
-		      | GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
+		      | GPSR2_QSPI0_MOSI_IO0
+		      | GPSR2_QSPI0_SPCLK);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
 		      | GPSR3_SD1_CD
 		      | GPSR3_SD0_WP
@@ -701,7 +713,9 @@ void pfc_init_e3(void)
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
 		      | GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
@@ -710,13 +724,17 @@ void pfc_init_e3(void)
 		      | GPSR4_SD3_DAT3
 		      | GPSR4_SD3_DAT2
 		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
 		      | GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_RX2_A
 		      | GPSR5_TX2_A
-		      | GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
+		      | GPSR5_SCK2_A
+		      | GPSR5_RTS0_TANS_A
+		      | GPSR5_CTS0_A);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
 		      | GPSR6_SSI_SDATA6
 		      | GPSR6_SSI_WS6
@@ -730,7 +748,8 @@ void pfc_init_e3(void)
 		      | GPSR6_SSI_SCK349
 		      | GPSR6_SSI_SDATA1
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
+		      | GPSR6_SSI_WS01239
+		      | GPSR6_SSI_SCK01239);
 
 	/* initialize POC control */
 	reg = mmio_read_32(PFC_IOCTRL30);
@@ -743,7 +762,9 @@ void pfc_init_e3(void)
 	       | POC_SD0_DAT3_33V
 	       | POC_SD0_DAT2_33V
 	       | POC_SD0_DAT1_33V
-	       | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+	       | POC_SD0_DAT0_33V
+	       | POC_SD0_CMD_33V
+	       | POC_SD0_CLK_33V);
 	pfc_reg_write(PFC_IOCTRL30, reg);
 	reg = mmio_read_32(PFC_IOCTRL32);
 	reg = (reg & IOCTRL32_MASK);

drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c

@@ -802,7 +802,9 @@ void pfc_init_h3_v1(void)
 		      | MOD_SEL0_DRIF2_A
 		      | MOD_SEL0_DRIF1_A
 		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A
+		      | MOD_SEL0_5LINE_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 		      | MOD_SEL1_TSIF0_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -822,9 +824,13 @@ void pfc_init_h3_v1(void)
 		      | MOD_SEL1_PWM6_A
 		      | MOD_SEL1_PWM5_A
 		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
 	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_VIN4_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -971,7 +977,10 @@ void pfc_init_h3_v1(void)
 		      | GPSR0_D14
 		      | GPSR0_D13
 		      | GPSR0_D12
-		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
 	pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
 		      | GPSR1_A19
 		      | GPSR1_A18
@@ -984,7 +993,11 @@ void pfc_init_h3_v1(void)
 		      | GPSR1_A7
 		      | GPSR1_A6
 		      | GPSR1_A5
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
 		      | GPSR2_AVB_AVTP_MATCH_A
 		      | GPSR2_AVB_LINK
@@ -994,7 +1007,10 @@ void pfc_init_h3_v1(void)
 		      | GPSR2_PWM1_A
 		      | GPSR2_IRQ5
 		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
 		      | GPSR3_SD0_CD
 		      | GPSR3_SD1_DAT3
@@ -1004,7 +1020,9 @@ void pfc_init_h3_v1(void)
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
 		      | GPSR4_SD3_DAT3
@@ -1017,7 +1035,9 @@ void pfc_init_h3_v1(void)
 		      | GPSR4_SD2_DAT3
 		      | GPSR4_SD2_DAT2
 		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_MSIOF0_SYNC
@@ -1032,7 +1052,9 @@ void pfc_init_h3_v1(void)
 		      | GPSR5_RTS1_TANS
 		      | GPSR5_CTS1
 		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
 		      | GPSR6_USB30_PWEN
 		      | GPSR6_USB1_OVC
@@ -1052,9 +1074,12 @@ void pfc_init_h3_v1(void)
 		      | GPSR6_SSI_SCK4
 		      | GPSR6_SSI_SDATA1_A
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
 	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
 
 	/* initialize POC control register */
 	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1071,7 +1096,9 @@ void pfc_init_h3_v1(void)
 		      | POC_SD0_DAT3_33V
 		      | POC_SD0_DAT2_33V
 		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
 
 	/* initialize DRV control register */
 	reg = mmio_read_32(PFC_DRVCTRL0);