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Commit 783c5304 authored by Chiaki Fujii's avatar Chiaki Fujii Committed by Marek Vasut
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rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N 



[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.36.
Signed-off-by: default avatarChiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia4fc9456876a14a9cf3ced93163477974f6cc8bf
parent 4b5c1f30
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drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View file @ 783c5304
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 20
#define BOARDNUM 22
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
......@@ -1425,6 +1425,108 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
}
}
},
/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0x04},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0xff},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0xff},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
......@@ -1522,10 +1624,10 @@ static const uint32_t TermcodeBySample[20][3] = {
#define GPIO_INDT5 0xE605500CU
#define GPIO_INDT6 0xE605540CU
#define BIT25 (1<<25)
#define BIT22 (1<<22)
#define BIT15 (1<<15)
#define BIT0 (1)
#define BIT25 BIT(25)
#define BIT22 BIT(22)
#define BIT15 BIT(15)
#define BIT0 BIT(0)
#define GPIO_GPSR6 (0xE6060118U)
#if (RCAR_GEN3_ULCB == 0)
......@@ -1673,7 +1775,7 @@ static uint32_t _board_judge(void)
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
/* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
brd = 19;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View file @ 783c5304
......@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.35"
#define RCAR_DDR_VERSION "rev.0.36"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
......@@ -144,11 +144,11 @@
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
#define DBSC_DBDFICUPDCNF 0xE679052CU
#define DBSC_INITCOMP(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_INITCOMP_0 0xE6790600U
#define DBSC_INITCOMP_1 0xE6790640U
#define DBSC_INITCOMP_2 0xE6790680U
#define DBSC_INITCOMP_3 0xE67906C0U
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_DBDFISTAT_0 0xE6790600U
#define DBSC_DBDFISTAT_1 0xE6790640U
#define DBSC_DBDFISTAT_2 0xE6790680U
#define DBSC_DBDFISTAT_3 0xE67906C0U
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
#define DBSC_DBDFICNT_0 0xE6790604U
......
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
View file @ 783c5304
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -1182,7 +1182,7 @@
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
const static uint32_t DDR_REGDEF_TBL[4][1173] = {
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
{
/*0000*/ 0xffffffffU,
/*0001*/ 0xffffffffU,
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
View file @ 783c5304
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......
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