Merge pull request #194 from danh-arm/sm/tf-issues#98

Implement the CPU Specific operations framework v3

Makefile

@@ -138,6 +138,10 @@ msg_start:
 
 include plat/${PLAT}/platform.mk
 
+# By default all CPU errata workarounds are disabled. This can be
+# overridden by the platform.
+include lib/cpus/cpu-errata.mk
+
 ifdef BL1_SOURCES
 NEED_BL1 := yes
 include bl1/bl1.mk
@@ -180,6 +184,7 @@ INCLUDES		+=	-Iinclude/bl31			\
 				-Iinclude/drivers/io		\
 				-Iinclude/lib			\
 				-Iinclude/lib/aarch64		\
+				-Iinclude/lib/cpus/aarch64	\
 				-Iinclude/plat/common		\
 				-Iinclude/stdlib		\
 				-Iinclude/stdlib/sys		\

bl1/aarch64/bl1_entrypoint.S

@@ -57,7 +57,7 @@ func bl1_entrypoint
 	 * reset e.g. cache, tlb invalidations etc.
 	 * ---------------------------------------------
 	 */
-	bl	cpu_reset_handler
+	bl	reset_handler
 
 	/* ---------------------------------------------
 	 * Enable the instruction cache, stack pointer

bl1/bl1.ld.S

@@ -50,10 +50,23 @@ SECTIONS
         *bl1_entrypoint.o(.text*)
         *(.text*)
         *(.rodata*)
+
+        /*
+         * Ensure 8-byte alignment for cpu_ops so that its fields are also
+         * aligned. Also ensure cpu_ops inclusion.
+         */
+        . = ALIGN(8);
+        __CPU_OPS_START__ = .;
+        KEEP(*(cpu_ops))
+        __CPU_OPS_END__ = .;
+
         *(.vectors)
         __RO_END__ = .;
     } >ROM
 
+    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
+           "cpu_ops not defined for this platform.")
+
     /*
      * The .data section gets copied from ROM to RAM at runtime.
      * Its LMA must be 16-byte aligned.

bl1/bl1.mk

@@ -32,6 +32,6 @@ BL1_SOURCES		+=	bl1/bl1_main.c				\
 				bl1/aarch64/bl1_arch_setup.c		\
 				bl1/aarch64/bl1_entrypoint.S		\
 				bl1/aarch64/bl1_exceptions.S		\
-				lib/aarch64/cpu_helpers.S
+				lib/cpus/aarch64/cpu_helpers.S
 
 BL1_LINKERFILE		:=	bl1/bl1.ld.S

bl31/aarch64/bl31_entrypoint.S

@@ -68,7 +68,7 @@ func bl31_entrypoint
 	 * Boot ROM(BL0) programming sequence
 	 * -----------------------------------------------------
 	 */
-	bl	cpu_reset_handler
+	bl	reset_handler
 #endif
 	/* ---------------------------------------------
 	 * Enable the instruction cache, stack pointer
@@ -153,6 +153,12 @@ func bl31_entrypoint
 	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
 	bl	zeromem16
 
+	/* ---------------------------------------------
+	 * Initialize the cpu_ops pointer.
+	 * ---------------------------------------------
+	 */
+	bl	init_cpu_ops
+
 	/* ---------------------------------------------
 	 * Use SP_EL0 for the C runtime stack.
 	 * ---------------------------------------------

bl31/aarch64/crash_reporting.S

@@ -52,9 +52,6 @@
 print_spacer:
 	.asciz	" =\t\t0x"
 
-cpu_ectlr_reg:
-	.asciz	"cpuectlr_el1 =\t\t0x"
-
 gp_regs:
 	.asciz	"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
 		"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\
@@ -337,21 +334,9 @@ func do_crash_reporting
 	mrs	x10, sp_el0
 	bl	str_in_crash_buf_print
 
-	/* Print the CPUECTLR_EL1 reg */
-	mrs	x0, midr_el1
-	lsr	x0, x0, #MIDR_PN_SHIFT
-	and	x0, x0, #MIDR_PN_MASK
-	cmp	x0, #MIDR_PN_A57
-	b.eq	1f
-	cmp	x0, #MIDR_PN_A53
-	b.ne	2f
-1:
-	adr	x4, cpu_ectlr_reg
-	bl	asm_print_str
-	mrs	x4, CPUECTLR_EL1
-	bl	asm_print_hex
-	bl	print_newline
-2:
+	/* Get the cpu specific registers to report */
+	bl	do_cpu_reg_dump
+	bl	str_in_crash_buf_print
 
 	/* Print the gic registers */
 	plat_print_gic_regs

bl31/bl31.ld.S

@@ -58,6 +58,15 @@ SECTIONS
         KEEP(*(rt_svc_descs))
         __RT_SVC_DESCS_END__ = .;
 
+        /*
+         * Ensure 8-byte alignment for cpu_ops so that its fields are also
+         * aligned. Also ensure cpu_ops inclusion.
+         */
+        . = ALIGN(8);
+        __CPU_OPS_START__ = .;
+        KEEP(*(cpu_ops))
+        __CPU_OPS_END__ = .;
+
         *(.vectors)
         __RO_END_UNALIGNED__ = .;
         /*
@@ -69,6 +78,9 @@ SECTIONS
         __RO_END__ = .;
     } >RAM
 
+    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
+           "cpu_ops not defined for this platform.")
+
     .data . : {
         __DATA_START__ = .;
         *(.data*)

bl31/bl31.mk

@@ -39,7 +39,7 @@ BL31_SOURCES		+=	bl31/bl31_main.c				\
 				bl31/aarch64/cpu_data.S				\
 				bl31/aarch64/runtime_exceptions.S		\
 				bl31/aarch64/crash_reporting.S			\
-				lib/aarch64/cpu_helpers.S			\
+				lib/cpus/aarch64/cpu_helpers.S			\
 				lib/locks/bakery/bakery_lock.c			\
 				lib/locks/exclusive/spinlock.S			\
 				services/std_svc/std_svc_setup.c		\

common/aarch64/debug.S

@@ -58,13 +58,13 @@ assert_msg2:
 	.macro asm_print_line_dec
 	mov	x6, #10		/* Divide by 10 after every loop iteration */
 	mov	x5, #MAX_DEC_DIVISOR
-1:
+dec_print_loop:
 	udiv	x0, x4, x5		/* Get the quotient */
 	msub	x4, x0, x5, x4		/* Find the remainder */
 	add	x0, x0, #ASCII_OFFSET_NUM		/* Convert to ascii */
 	bl	plat_crash_console_putc
 	udiv	x5, x5, x6		/* Reduce divisor */
-	cbnz	x5, 1b
+	cbnz	x5, dec_print_loop
 	.endm
 
 

docs/cpu-errata-workarounds.md

+ARM CPU Errata Workarounds
+==========================
+
+ARM Trusted Firmware exports a series of build flags which controls the
+errata workarounds that are applied to each CPU by the reset handler. The
+errata details can be found in the CPU specifc errata documents published
+by ARM. The errata workarounds are implemented for a particular revision
+or a set of processor revisions. This check is done in the debug build.
+Each errata workaround is identified by its `ID` as specified in the processor's
+errata notice document. The format of the define used to enable/disable the
+errata is `ERRATA_<Processor name>_<ID>` where the `Processor name`
+is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU.
+
+All workarounds are disabled by default. The platform is reponsible for
+enabling these workarounds according to its requirement by defining the
+errata workaround build flags in the platform specific makefile.
+
+In the current implementation, a platform which has more than 1 variant
+with different revisions of a processor has no runtime mechanism available
+for it to specify which errata workarounds should be enabled or not.
+
+The value of the build flags are 0 by default, that is disabled. Any other
+value will enable it.
+
+For Cortex A57, following errata build flags are defined :
+
+*   `ERRATA_A57_806969`: This applies errata 806969 workaround to cortex a57
+     CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+*   `ERRATA_A57_813420`: This applies errata 813420 workaround to cortex a57
+     CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._

docs/firmware-design.md

@@ -9,10 +9,11 @@ Contents :
 4.  Power State Coordination Interface
 5.  Secure-EL1 Payloads and Dispatchers
 6.  Crash Reporting in BL3-1
-7.  Memory layout on FVP platforms
-8.  Firmware Image Package (FIP)
-9.  Code Structure
-10.  References
+7.  CPU specific operations framework
+8.  Memory layout on FVP platforms
+9.  Firmware Image Package (FIP)
+10.  Code Structure
+11.  References
 
 
 1.  Introduction
@@ -302,8 +303,8 @@ far as system register settings are concerned. Since BL1 code resides in ROM,
 architectural initialization in BL3-1 allows override of any previous
 initialization done by BL1. BL3-1 creates page tables to address the first
 4GB of physical address space and initializes the MMU accordingly. It initializes
-a buffer of frequently used pointers, called per-cpu pointer cache, in memory for
-faster access. Currently the per-cpu pointer cache contains only the pointer
+a buffer of frequently used pointers, called per-CPU pointer cache, in memory for
+faster access. Currently the per-CPU pointer cache contains only the pointer
 to crash stack. It then replaces the exception vectors populated by BL1 with its
 own. BL3-1 exception vectors implement more elaborate support for
 handling SMCs since this is the only mechanism to access the runtime services
@@ -845,8 +846,8 @@ exception is encountered. The reporting mechanism attempts to preserve all the
 register contents and report it via the default serial output. The general purpose
 registers, EL3, Secure EL1 and some EL2 state registers are reported.
 
-A dedicated per-cpu crash stack is maintained by BL3-1 and this is retrieved via
-the per-cpu pointer cache. The implementation attempts to minimise the memory
+A dedicated per-CPU crash stack is maintained by BL3-1 and this is retrieved via
+the per-CPU pointer cache. The implementation attempts to minimise the memory
 required for this feature. The file `crash_reporting.S` contains the
 implementation for crash reporting.
 
@@ -931,8 +932,100 @@ The sample crash output is shown below.
     fpexc32_el2	:0x0000000004000700
     sp_el0	:0x0000000004010780
 
+7.  CPU specific operations framework
+-----------------------------
 
-7.  Memory layout on FVP platforms
+Certain aspects of the ARMv8 architecture are implementation defined,
+that is, certain behaviours are not architecturally defined, but must be defined
+and documented by individual processor implementations. The ARM Trusted
+Firmware implements a framework which categorises the common implementation
+defined behaviours and allows a processor to export its implementation of that
+behaviour. The categories are:
+
+1.  Processor specific reset sequence.
+
+2.  Processor specific power down sequences.
+
+3.  Processor specific register dumping as a part of crash reporting.
+
+Each of the above categories fulfils a different requirement.
+
+1.  allows any processor specific initialization before the caches and MMU
+    are turned on, like implementation of errata workarounds, entry into
+    the intra-cluster coherency domain etc.
+
+2.  allows each processor to implement the power down sequence mandated in
+    its Technical Reference Manual (TRM).
+
+3.  allows a processor to provide additional information to the developer
+    in the event of a crash, for example Cortex-A53 has registers which
+    can expose the data cache contents.
+
+Please note that only 2. is mandated by the TRM.
+
+The CPU specific operations framework scales to accommodate a large number of
+different CPUs during power down and reset handling. The platform can specify
+the CPU errata workarounds to be applied for each CPU type during reset
+handling by defining CPU errata compile time macros. Details on these macros
+can be found in the [cpu-errata-workarounds.md][ERRW] file.
+
+The CPU specific operations framework depends on the `cpu_ops` structure which
+needs to be exported for each type of CPU in the platform. It is defined in
+`include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`,
+`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`.
+
+The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with
+suitable handlers for that CPU.  For example, `lib/cpus/cortex_a53.S` exports
+the `cpu_ops` for Cortex-A53 CPU. According to the platform configuration,
+these CPU specific files must must be included in the build by the platform
+makefile. The generic CPU specific operations framework code exists in
+`lib/cpus/aarch64/cpu_helpers.S`.
+
+### CPU specific Reset Handling
+
+After a reset, the state of the CPU when it calls generic reset handler is:
+MMU turned off, both instruction and data caches turned off and not part
+of any coherency domain.
+
+The BL entrypoint code first invokes the `plat_reset_handler()` to allow
+the platform to perform any system initialization required and any system
+errata wrokarounds that needs to be applied. The `get_cpu_ops_ptr()` reads
+the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops`
+array and returns it. Note that only the part number and implementator fields
+in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in
+the returned `cpu_ops` is then invoked which executes the required reset
+handling for that CPU and also any errata workarounds enabled by the platform.
+
+### CPU specific power down sequence
+
+During the BL3-1 initialization sequence, the pointer to the matching `cpu_ops`
+entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly
+retrieved during power down sequences.
+
+The PSCI service, upon receiving a power down request, determines the highest
+affinity level at which to execute power down sequence for a particular CPU and
+invokes the corresponding 'prepare' power down handler in the CPU specific
+operations framework. For example, when a CPU executes a power down for affinity
+level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the
+per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when
+a CPU executes power down at affinity level 1, the `prepare_cluster_pwr_dwn()`
+retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is
+invoked.
+
+At runtime the platform hooks for power down are invoked by the PSCI service to
+perform platform specific operations during a power down sequence, for example
+turning off CCI coherency during a cluster power down.
+
+### CPU specific register reporting during crash
+
+If the crash reporting is enabled in BL3-1, when a crash occurs, the crash
+reporting framework calls `do_cpu_reg_dump` which retrieves the matching
+`cpu_ops` using `get_cpu_ops_ptr()` function. The `cpu_reg_dump()` in
+`cpu_ops` is invoked, which then returns the CPU specific register values to
+be reported and a pointer to the ASCII list of register names in a format
+expected by the crash reporting framework.
+
+8.  Memory layout on FVP platforms
 ----------------------------------
 
 Each bootloader image can be divided in 2 parts:
@@ -1189,7 +1282,7 @@ Additionally, if the platform memory layout implies some image overlaying like
 on FVP, BL3-1 and TSP need to know the limit address that their PROGBITS
 sections must not overstep. The platform code must provide those.
 
-8.  Firmware Image Package (FIP)
+9.  Firmware Image Package (FIP)
 --------------------------------
 
 Using a Firmware Image Package (FIP) allows for packing bootloader images (and
@@ -1267,7 +1360,7 @@ Currently the FVP's policy only allows loading of a known set of images. The
 platform policy can be modified to allow additional images.
 
 
-9.  Code Structure
+10.  Code Structure
 ------------------
 
 Trusted Firmware code is logically divided between the three boot loader
@@ -1312,7 +1405,7 @@ FDTs provide a description of the hardware platform and are used by the Linux
 kernel at boot time. These can be found in the `fdts` directory.
 
 
-10.  References
+11.  References
 --------------
 
 1.  Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
@@ -1324,7 +1417,6 @@ kernel at boot time. These can be found in the `fdts` directory.
 
 4.  [ARM Trusted Firmware Interrupt Management Design guide][INTRG].
 
-
 - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
@@ -1335,3 +1427,4 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
 [UUID]:             https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace"
 [User Guide]:       ./user-guide.md
 [INTRG]:            ./interrupt-framework-design.md
+[ERRW]:             ./cpu-errata-workarounds.md

docs/porting-guide.md

@@ -460,6 +460,32 @@ that these constants are not related to any architectural exception code; they
 are just an ARM Trusted Firmware convention.
 
 
+### Function : plat_reset_handler()
+
+    Argument : void
+    Return   : void
+
+A platform may need to do additional initialization after reset. This function
+allows the platform to do the platform specific intializations. Platform
+specific errata workarounds could also be implemented here. The api should
+preserve the value in x10 register as it is used by the caller to store the
+return address.
+
+The default implementation doesn't do anything.
+
+### Function : plat_disable_acp()
+
+    Argument : void
+    Return   : void
+
+This api allows a platform to disable the Accelerator Coherency Port (if
+present) during a cluster power down sequence. The default weak implementation
+doesn't do anything. Since this api is called during the power down sequence,
+it has restrictions for stack usage and it can use the registers x0 - x17 as
+scratch registers. It should preserve the value in x18 register as it is used
+by the caller to store the return address.
+
+
 3.  Modifications specific to a Boot Loader stage
 -------------------------------------------------
 

include/bl31/cpu_data.h

@@ -32,18 +32,21 @@
 #define __CPU_DATA_H__
 
 /* Offsets for the cpu_data structure */
-#define CPU_DATA_CRASH_BUF_OFFSET	0x10
+#define CPU_DATA_CRASH_BUF_OFFSET	0x20
 #if CRASH_REPORTING
 #define CPU_DATA_LOG2SIZE		7
 #else
 #define CPU_DATA_LOG2SIZE		6
 #endif
 /* need enough space in crash buffer to save 8 registers */
-#define CPU_DATA_CRASH_BUF_SIZE	64
+#define CPU_DATA_CRASH_BUF_SIZE		64
+#define CPU_DATA_CPU_OPS_PTR		0x10
+
 #ifndef __ASSEMBLY__
 
 #include <arch_helpers.h>
 #include <platform_def.h>
+#include <psci.h>
 #include <stdint.h>
 
 /*******************************************************************************
@@ -63,9 +66,10 @@
  * by components that have per-cpu members. The member access macros should be
  * used for this.
  ******************************************************************************/
-
 typedef struct cpu_data {
 	void *cpu_context[2];
+	uint64_t cpu_ops_ptr;
+	struct psci_cpu_data psci_svc_cpu_data;
 #if CRASH_REPORTING
 	uint64_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
 #endif
@@ -81,6 +85,10 @@ CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
 CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t),
 	assert_cpu_data_log2size_mismatch);
 
+CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
+		(cpu_data_t, cpu_ops_ptr),
+		assert_cpu_data_cpu_ops_ptr_offset_mismatch);
+
 struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
 struct cpu_data *_cpu_data_by_mpidr(uint64_t mpidr);
 
@@ -104,6 +112,10 @@ void init_cpu_data_ptr(void);
 #define get_cpu_data_by_mpidr(_id, _m)	   _cpu_data_by_mpidr(_id)->_m
 #define set_cpu_data_by_mpidr(_id, _m, _v) _cpu_data_by_mpidr(_id)->_m = _v
 
+#define flush_cpu_data(_m)	   flush_dcache_range((uint64_t) 	  \
+						      &(_cpu_data()->_m), \
+						      sizeof(_cpu_data()->_m))
+
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CPU_DATA_H__ */

include/bl31/services/psci.h

@@ -131,6 +131,16 @@
 
 #include <stdint.h>
 
+/*******************************************************************************
+ * Structure used to store per-cpu information relevant to the PSCI service.
+ * It is populated in the per-cpu data array. In return we get a guarantee that
+ * this information will not reside on a cache line shared with another cpu.
+ ******************************************************************************/
+typedef struct psci_cpu_data {
+	uint32_t power_state;
+	uint32_t max_phys_off_afflvl;	/* Highest affinity level in physically
+					   powered off state */
+} psci_cpu_data_t;
 
 /*******************************************************************************
  * Structure populated by platform specific code to export routines which
@@ -179,8 +189,6 @@ typedef struct spd_pm_ops {
  * Function & Data prototypes
  ******************************************************************************/
 unsigned int psci_version(void);
-int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long);
-int __psci_cpu_off(void);
 int psci_affinity_info(unsigned long, unsigned int);
 int psci_migrate(unsigned int);
 unsigned int psci_migrate_info_type(void);
@@ -192,8 +200,10 @@ void __dead2 psci_power_down_wfi(void);
 void psci_aff_on_finish_entry(void);
 void psci_aff_suspend_finish_entry(void);
 void psci_register_spd_pm_hook(const spd_pm_ops_t *);
-int psci_get_suspend_stateid(unsigned long mpidr);
-int psci_get_suspend_afflvl(unsigned long mpidr);
+int psci_get_suspend_stateid_by_mpidr(unsigned long);
+int psci_get_suspend_stateid(void);
+int psci_get_suspend_afflvl(void);
+uint32_t psci_get_max_phys_off_afflvl(void);
 
 uint64_t psci_smc_handler(uint32_t smc_fid,
 			  uint64_t x1,

include/common/assert_macros.S

@@ -30,7 +30,10 @@
 
 	/*
 	 * Assembler macro to enable asm_assert. Use this macro wherever
-	 * assert is required in assembly.
+	 * assert is required in assembly. Please note that the macro makes
+	 * use of label '300' to provide the logic and the caller
+	 * should make sure that this label is not used to branch prior
+	 * to calling this macro.
 	 */
 #define ASM_ASSERT(_cc) \
 .ifndef .L_assert_filename ;\
@@ -39,8 +42,8 @@
 			.string	__FILE__ ;\
 	.popsection ;\
 .endif ;\
-	b._cc	1f ;\
+	b._cc	300f ;\
 	adr	x0, .L_assert_filename ;\
 	mov	x1, __LINE__ ;\
 	b	asm_assert ;\
-1:
+300:

include/lib/aarch64/arch.h

@@ -35,11 +35,12 @@
 /*******************************************************************************
  * MIDR bit definitions
  ******************************************************************************/
+#define MIDR_IMPL_MASK		0xff
+#define MIDR_IMPL_SHIFT		0x18
+#define MIDR_VAR_SHIFT		20
+#define MIDR_REV_SHIFT		0
 #define MIDR_PN_MASK		0xfff
 #define MIDR_PN_SHIFT		0x4
-#define MIDR_PN_AEM		0xd0f
-#define MIDR_PN_A57		0xd07
-#define MIDR_PN_A53		0xd03
 
 /*******************************************************************************
  * MPIDR macros
@@ -74,11 +75,6 @@
 #define ICC_CTLR_EL3    S3_6_C12_C12_4
 #define ICC_PMR_EL1     S3_0_C4_C6_0
 
-/*******************************************************************************
- * Implementation defined sysreg encodings
- ******************************************************************************/
-#define CPUECTLR_EL1	S3_1_C15_C2_1
-
 /*******************************************************************************
  * Generic timer memory mapped registers & offsets
  ******************************************************************************/
@@ -133,9 +129,6 @@
 #define SCTLR_WXN_BIT		(1 << 19)
 #define SCTLR_EE_BIT		(1 << 25)
 
-/* CPUECTLR definitions */
-#define CPUECTLR_SMP_BIT	(1 << 6)
-
 /* CPACR_El1 definitions */
 #define CPACR_EL1_FPEN(x)	(x << 20)
 #define CPACR_EL1_FP_TRAP_EL0	0x1

include/lib/aarch64/arch_helpers.h

@@ -265,10 +265,6 @@ DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
 
-/* Implementation specific registers */
-
-DEFINE_RENAME_SYSREG_RW_FUNCS(cpuectlr_el1, CPUECTLR_EL1)
-
 /* GICv3 System Registers */
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
@@ -299,9 +295,6 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
 #define read_hcr()		read_hcr_el2()
 #define write_hcr(_v)		write_hcr_el2(_v)
 
-#define read_cpuectlr()		read_cpuectlr_el1()
-#define write_cpuectlr(_v)	write_cpuectlr_el1(_v)
-
 #define read_cpacr()		read_cpacr_el1()
 #define write_cpacr(_v)		write_cpacr_el1(_v)
 

lib/aarch64/cpu_helpers.S → include/lib/cpus/aarch64/aem_generic.h

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,28 +28,14 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch.h>
-#include <asm_macros.S>
+#ifndef __AEM_GENERIC_H__
+#define __AEM_GENERIC_H__
 
-	.weak	cpu_reset_handler
+/* BASE AEM midr for revision 0 */
+#define BASE_AEM_MIDR 0x410FD0F0
 
+/* Foundation AEM midr for revision 0 */
+#define FOUNDATION_AEM_MIDR  0x410FD000
 
-func cpu_reset_handler
-	/* ---------------------------------------------
-	 * As a bare minimal enable the SMP bit.
-	 * ---------------------------------------------
-	 */
-	mrs	x0, midr_el1
-	lsr	x0, x0, #MIDR_PN_SHIFT
-	and	x0, x0, #MIDR_PN_MASK
-	cmp	x0, #MIDR_PN_A57
-	b.eq	smp_setup_begin
-	cmp	x0, #MIDR_PN_A53
-	b.ne	smp_setup_end
-smp_setup_begin:
-	mrs	x0, CPUECTLR_EL1
-	orr	x0, x0, #CPUECTLR_SMP_BIT
-	msr	CPUECTLR_EL1, x0
-	isb
-smp_setup_end:
-	ret
+
+#endif /* __AEM_GENERIC_H__ */

include/lib/cpus/aarch64/cortex_a53.h

+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CORTEX_A53_H__
+#define __CORTEX_A53_H__
+
+/* Cortex-A53 midr for revision 0 */
+#define CORTEX_A53_MIDR 0x410FD030
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CPUECTLR_EL1			S3_1_C15_C2_1	/* Instruction def. */
+
+#define CPUECTLR_SMP_BIT		(1 << 6)
+
+#endif /* __CORTEX_A53_H__ */

include/lib/cpus/aarch64/cortex_a57.h

+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CORTEX_A57_H__
+#define __CORTEX_A57_H__
+
+/* Cortex-A57 midr for revision 0 */
+#define CORTEX_A57_MIDR 0x410FD070
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CPUECTLR_EL1			S3_1_C15_C2_1	/* Instruction def. */
+
+#define CPUECTLR_SMP_BIT		(1 << 6)
+#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT	(1 << 38)
+#define CPUECTLR_L2_IPFTCH_DIST_MASK	(0x3 << 35)
+#define CPUECTLR_L2_DPFTCH_DIST_MASK	(0x3 << 32)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CPUACTLR_EL1			S3_1_C15_C2_0	/* Instruction def. */
+
+#define CPUACTLR_NO_ALLOC_WBWA         (1 << 49)
+#define CPUACTLR_DCC_AS_DCCI           (1 << 44)
+
+#endif /* __CORTEX_A57_H__ */