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Commit 79ca7807 authored by Justin Chadwell's avatar Justin Chadwell
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Update rockchip platform to not rely on undefined overflow behaviour 



This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168
Signed-off-by: default avatarJustin Chadwell <justin.chadwell@arm.com>
parent 673406b5
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Inline Side-by-side
plat/rockchip/rk3328/drivers/pmu/pmu.c
View file @ 79ca7807
......@@ -284,7 +284,7 @@ static inline void pm_pll_wait_lock(uint32_t pll_id)
static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd)
{
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
if (pd)
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
BITS_WITH_WMASK(1, 1, 14));
......@@ -305,7 +305,7 @@ static __sramfunc void dpll_suspend(void)
sram_data.dpll_con_save[i] =
mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 14));
}
......@@ -315,7 +315,7 @@ static __sramfunc void dpll_resume(void)
uint32_t delay = PLL_LOCKED_TIMEOUT;
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(0, 1, 14));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
......@@ -402,7 +402,7 @@ static void pm_plls_suspend(void)
/* clk_rtc32k */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
BITS_WITH_WMASK(767, 0x3fff, 0) |
BITS_WITH_WMASK(2, 0x3, 14));
BITS_WITH_WMASK(2U, 0x3u, 14));
}
static void pm_plls_resume(void)
......@@ -411,7 +411,7 @@ static void pm_plls_resume(void)
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
ddr_data.clk_sel38 |
BITS_WMSK(0x3fff, 0) |
BITS_WMSK(0x3, 14));
BITS_WMSK(0x3u, 14));
/* uart2 */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18),
......@@ -483,7 +483,7 @@ __sramfunc void rk3328_pmic_resume(void)
mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]);
mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]);
mmio_write_32(GRF_BASE + PMIC_SLEEP_REG,
sram_data.pmic_sleep_save | BITS_WMSK(0xffff, 0));
sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0));
/* Resuming volt need a lot of time */
sram_udelay(100);
}
......
plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
View file @ 79ca7807
......@@ -400,7 +400,7 @@ void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 0))
& 0xffff) |
(0xFFFF << 16);
(0xFFFFu << 16);
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 1))
& 0xffff);
......@@ -410,7 +410,7 @@ void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 3))
& 0xffff) |
(0xFFFF << 16);
(0xFFFFu << 16);
} else {
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
}
......
plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h
View file @ 79ca7807
......@@ -222,7 +222,7 @@
#define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0))
/* CRU_DPLL_CON2 */
#define DPLL_STATUS_LOCK (1 << 31)
#define DPLL_STATUS_LOCK (1U << 31)
/* CRU_DPLL_CON3 */
#define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1))
......@@ -237,7 +237,7 @@
#define DDR_PLL_SRC_MASK 0x13
/* DDR_PCTL_TREFI */
#define DDR_UPD_REF_ENABLE (0X1 << 31)
#define DDR_UPD_REF_ENABLE (0X1u << 31)
uint32_t ddr_get_resume_code_size(void);
uint32_t ddr_get_resume_data_size(void);
......
plat/rockchip/rk3368/drivers/soc/soc.h
View file @ 79ca7807
......@@ -50,7 +50,7 @@ enum plls_id {
#define PMUSRAM_S 1
#define STIMER_S_SHIFT 6
#define STIMER_S 1
#define SGRF_SOC_CON7_BITS ((0xffff << 16) | \
#define SGRF_SOC_CON7_BITS ((0xffffu << 16) | \
(PMUSRAM_S << PMUSRAM_S_SHIFT) | \
(STIMER_S << STIMER_S_SHIFT))
......
plat/rockchip/rk3399/drivers/dram/dfs.c
View file @ 79ca7807
......@@ -504,7 +504,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->tmod << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
......@@ -513,7 +513,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
......@@ -521,7 +521,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
......@@ -531,7 +531,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24),
(pdram_timing->cwl << 24));
mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16,
(pdram_timing->trc << 24) |
(pdram_timing->trrd << 16));
mmio_write_32(CTL_REG(i, 27),
......@@ -540,7 +540,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->twtr << 8) |
pdram_timing->tras_min);
mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24,
max(4, pdram_timing->trtp) << 24);
mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
pdram_timing->tras_max);
......@@ -560,7 +560,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16,
pdram_timing->txpdll << 16);
mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24,
pdram_timing->tcscke << 24);
......@@ -571,7 +571,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->tckehcs << 8) |
pdram_timing->tckelcs);
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 63),
......@@ -601,7 +601,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff,
pdram_timing->mr[3]);
mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24,
pdram_timing->mr11 << 24);
mmio_write_32(CTL_REG(i, 147),
(pdram_timing->mr[1] << 16) |
......@@ -610,20 +610,20 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff,
pdram_timing->mr[3]);
mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24,
pdram_timing->mr11 << 24);
if (timing_config->dram_type == LPDDR4) {
mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16,
pdram_timing->mr12 << 16);
mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16,
pdram_timing->mr14 << 16);
mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16,
pdram_timing->mr22 << 16);
mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16,
pdram_timing->mr12 << 16);
mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16,
pdram_timing->mr14 << 16);
mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16,
pdram_timing->mr22 << 16);
}
mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8,
......@@ -655,7 +655,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
<< 8) | get_rdlat_adj(timing_config->dram_type,
pdram_timing->cl);
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16,
(4 * pdram_timing->trefi) << 16);
mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff,
......@@ -748,13 +748,13 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
pdram_timing->tmod + pdram_timing->tzqinit;
mmio_write_32(CTL_REG(i, 9), tmp);
mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16,
pdram_timing->tdllk << 16);
mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00,
(pdram_timing->tmod << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
......@@ -764,7 +764,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
......@@ -773,7 +773,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
......@@ -796,7 +796,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tras_max);
mmio_clrsetbits_32(CTL_REG(i, 36), 0xff,
max(1, pdram_timing->tckesr));
mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24),
mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24),
(pdram_timing->trcd << 24));
mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24,
......@@ -809,7 +809,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_write_32(CTL_REG(i, 49),
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16,
pdram_timing->txp << 16);
mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff,
pdram_timing->txpdll);
......@@ -821,7 +821,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tcscke);
mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
......@@ -831,7 +831,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff,
(pdram_timing->tcmdcke << 8) |
pdram_timing->tcsckeh);
mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24),
mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24),
(pdram_timing->tcksre << 24));
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff,
pdram_timing->tcksrx);
......@@ -845,18 +845,18 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tfc_long);
mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff,
pdram_timing->tvref_long);
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
if (timing_config->dram_type == LPDDR4) {
......@@ -907,7 +907,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff,
(4 * pdram_timing->trefi) & 0xffff);
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
if ((timing_config->dram_type == LPDDR3) ||
......@@ -936,12 +936,12 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16,
(tmp & 0x3f) << 16);
mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24,
(get_pi_tdfi_phy_rdlat(pdram_timing,
timing_config) &
0xff) << 24);
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff,
......@@ -973,7 +973,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
tmp = tmp1 - 2;
}
mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24);
/* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
......@@ -1036,7 +1036,7 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
tmp = 2 * pdram_timing->trefi;
mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
/* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16);
mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16);
/* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
if (timing_config->dram_type == LPDDR4)
......@@ -1060,14 +1060,14 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16,
(pdram_timing->cl * 2) << 16);
/* PI_46 PI_TREF_F0:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_46 PI_TRFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
/* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
if (timing_config->dram_type == LPDDR3) {
tmp = get_pi_todtoff_max(pdram_timing, timing_config);
mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24,
tmp << 24);
}
/* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
......@@ -1148,19 +1148,19 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
/* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
/* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16,
pdram_timing->mr[1] << 16);
/* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
/* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
/* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
/* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_156 PI_TFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff,
......@@ -1177,10 +1177,10 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
/* PI_158 PI_TRP_F0:RW:0:8 */
mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
/* PI_157 PI_TRTP_F0:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24,
pdram_timing->trtp << 24);
/* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
tmp = pdram_timing->tras_max * 99 / 100;
......@@ -1237,7 +1237,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
(pdram_timing->cl * 2) << 8);
/* PI_47 PI_TREF_F1:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_47 PI_TRFC_F1:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
......@@ -1278,10 +1278,10 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
/*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_rdlat_adj(pdram_timing);
mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24);
/* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24);
/* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
tmp1 = tmp;
if (tmp1 == 0)
......@@ -1290,7 +1290,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
tmp = tmp1 - 1;
else
tmp = tmp1 - 5;
mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24);
/*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
/* tadr=20ns */
tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
......@@ -1333,12 +1333,12 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8,
pdram_timing->mr[1] << 8);
/* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
/* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
......@@ -1351,7 +1351,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
/* PI_162 PI_TWTR_F1:RW:0:6 */
mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
/* PI_161 PI_TRCD_F1:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24,
pdram_timing->trcd << 24);
/* PI_161 PI_TRP_F1:RW:16:8 */
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16,
......@@ -1360,7 +1360,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8,
pdram_timing->trtp << 8);
/* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff,
......@@ -1765,7 +1765,7 @@ uint32_t exit_low_power(void)
0x40) {
while (mmio_read_32(CTL_REG(i, 200)) & 0x1)
;
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24,
0x69 << 24);
while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) !=
0x40)
......
plat/rockchip/rk3399/drivers/dram/suspend.c
View file @ 79ca7807
......@@ -172,7 +172,7 @@ static __pmusramfunc void override_write_leveling_value(uint32_t ch)
mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16,
1 << 16);
mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)),
0xffff << 16,
0xffffu << 16,
0x200 << 16);
}
......@@ -656,7 +656,7 @@ __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src)
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
(1 << 31)) == 0x0)
(1U << 31)) == 0x0)
;
}
......
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
View file @ 79ca7807
......@@ -45,10 +45,10 @@ void m0_configure_execute_addr(uintptr_t addr)
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((addr >> 12) & 0xffff,
0xffff, 0));
0xffffu, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((addr >> 28) & 0xf,
0xf, 0));
0xfu, 0));
}
void m0_start(void)
......
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