Merge changes from topic "tegra-downstream-01082020" into integration

* changes:
  Tegra194: platform handler for entering CPU standby state
  Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
  Tegra194: memctrl: fix bug in client order id reg value generation
  Tegra194: memctrl: enable mc coalescer
  Tegra194: update scratch registers used to read boot parameters
  Tegra194: implement system shutdown/reset handlers
  Tegra194: mce: support for shutdown and reboot
  Tegra194: request CG7 before checking if SC7 is allowed
  Tegra194: config to enable/disable strict checking mode
  Tegra194: remove unused platform configs
  Tegra194: restore XUSB stream IDs on System Resume

plat/nvidia/tegra/include/t194/tegra_def.h

@@ -172,16 +172,16 @@
  * Tegra scratch registers constants
  ******************************************************************************/
 #define TEGRA_SCRATCH_BASE		U(0x0C390000)
-#define  SECURE_SCRATCH_RSV44_LO	U(0x1C4)
-#define  SECURE_SCRATCH_RSV44_HI	U(0x1C8)
+#define  SECURE_SCRATCH_RSV81_LO	U(0x2EC)
+#define  SECURE_SCRATCH_RSV81_HI	U(0x2F0)
 #define  SECURE_SCRATCH_RSV97		U(0x36C)
 #define  SECURE_SCRATCH_RSV99_LO	U(0x37C)
 #define  SECURE_SCRATCH_RSV99_HI	U(0x380)
 #define  SECURE_SCRATCH_RSV109_LO	U(0x3CC)
 #define  SECURE_SCRATCH_RSV109_HI	U(0x3D0)
 
-#define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV44_LO
-#define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV44_HI
+#define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV81_LO
+#define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV81_HI
 #define SCRATCH_SECURE_BOOTP_FCFG	SECURE_SCRATCH_RSV97
 #define SCRATCH_SMMU_TABLE_ADDR_LO	SECURE_SCRATCH_RSV99_LO
 #define SCRATCH_SMMU_TABLE_ADDR_HI	SECURE_SCRATCH_RSV99_HI

plat/nvidia/tegra/include/t194/tegra_mc_def.h

@@ -27,8 +27,8 @@
 #define  MC_CLIENT_ORDER_ID_28_PCIE5W_MASK		(0x3U << 12)
 #define  MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID		(2U << 12)
 
-#define mc_client_order_id(id, client) \
-	(~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \
+#define mc_client_order_id(val, id, client) \
+	((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \
 	MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID)
 
 /*******************************************************************************
@@ -53,8 +53,8 @@
 #define  MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK		(0x3U << 28)
 #define  MC_HUB_PC_VC_ID_4_NIC_VC_ID			(VC_NISO << 28)
 
-#define mc_hub_vc_id(id, client) \
-	(~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \
+#define mc_hub_vc_id(val, id, client) \
+	((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \
 	MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
 
 /*******************************************************************************
@@ -530,6 +530,9 @@
 #define  MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB		(1U << 25)
 #define MC_CLIENT_HOTRESET_STATUS2				0x1898U
 
+#define MC_COALESCE_CTRL					0x2930U
+#define  MC_COALESCE_CTRL_COALESCER_ENABLE			(1U << 31)
+
 /*******************************************************************************
  * Tegra TSA Controller constants
  ******************************************************************************/

plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h

@@ -7,6 +7,7 @@
 #ifndef MCE_PRIVATE_H
 #define MCE_PRIVATE_H
 
+#include <stdbool.h>
 #include <tegra_def.h>
 
 /*******************************************************************************
@@ -67,8 +68,12 @@ uint64_t nvg_cache_clean(void);
 uint64_t nvg_cache_clean_inval(void);
 uint64_t nvg_cache_inval_all(void);
 void nvg_enable_strict_checking_mode(void);
+void nvg_system_shutdown(void);
+void nvg_system_reboot(void);
 
 /* MCE helper functions */
 void mce_enable_strict_checking(void);
+void mce_system_shutdown(void);
+void mce_system_reboot(void);
 
 #endif /* MCE_PRIVATE_H */

plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -128,6 +128,11 @@ typedef enum {
 	TEGRA_NVG_SYSTEM_SC8 = 8
 } tegra_nvg_system_sleep_state_t;
 
+typedef enum {
+    TEGRA_NVG_SHUTDOWN = 0U,
+    TEGRA_NVG_REBOOT = 1U,
+} tegra_nvg_shutdown_reboot_state_t;
+
 // ---------------------------------------------------------------------------
 // NVG Data subformats
 // ---------------------------------------------------------------------------

plat/nvidia/tegra/soc/t194/drivers/mce/mce.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -186,6 +186,7 @@ void mce_verify_firmware_version(void)
 	}
 }
 
+#if ENABLE_STRICT_CHECKING_MODE
 /*******************************************************************************
  * Handler to enable the strict checking mode
  ******************************************************************************/
@@ -235,3 +236,20 @@ void mce_enable_strict_checking(void)
 		nvg_enable_strict_checking_mode();
 	}
 }
+#endif
+
+/*******************************************************************************
+ * Handler to power down the entire system
+ ******************************************************************************/
+void mce_system_shutdown(void)
+{
+	nvg_system_shutdown();
+}
+
+/*******************************************************************************
+ * Handler to reboot the entire system
+ ******************************************************************************/
+void mce_system_reboot(void)
+{
+	nvg_system_reboot();
+}

plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c

@@ -288,6 +288,7 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
 	return ret;
 }
 
+#if ENABLE_STRICT_CHECKING_MODE
 /*
  * Enable strict checking mode
  *
@@ -300,3 +301,26 @@ void nvg_enable_strict_checking_mode(void)
 
 	nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
 }
+#endif
+
+/*
+ * Request a reboot
+ *
+ * NVGDATA[0]: reboot command
+ */
+void nvg_system_reboot(void)
+{
+	/* issue command for reboot */
+	nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_REBOOT);
+}
+
+/*
+ * Request a shutdown
+ *
+ * NVGDATA[0]: shutdown command
+ */
+void nvg_system_shutdown(void)
+{
+	/* issue command for shutdown */
+	nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_SHUTDOWN);
+}

plat/nvidia/tegra/soc/t194/plat_memctrl.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -478,8 +478,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void)
 	mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
 	mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
 	mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
-	mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
-	mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+	mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+	mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
 	mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
 	mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
 			     FORCE_COHERENT_SNOOP);
@@ -577,36 +578,29 @@ static void tegra194_memctrl_reconfig_mss_clients(void)
 	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
 
 	/* Set Order Id only for the clients having non zero order id */
-	reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL &
-		mc_client_order_id(9, XUSB_HOSTW);
+	reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW);
 	tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
 
-	reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL &
-		mc_client_order_id(27, PCIE0W);
+	reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W);
 	tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
 
-	reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL &
-		mc_client_order_id(28, PCIE4W) &
-		mc_client_order_id(28, PCIE5W);
+	reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W);
+	reg_val = mc_client_order_id(reg_val, 28, PCIE5W);
 	tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
 
-	/* Set VC Id only for the clients having different reset values */
-	reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL &
-		/*
-		 * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB,
-		 * TSECSWR and TSECSWRB clients
-		 */
-		mc_hub_vc_id(0, APB);
+	/*
+	 * Set VC Id only for the clients having different reset values like
+	 * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and
+	 * TSECSWRB clients
+	 */
+	reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB);
 	tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
 
-	reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL &
 	/* SDMMCRAB and SDMMCWAB clients */
-		mc_hub_vc_id(2, SD);
+	reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD);
 	tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
 
-	reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL &
-	 /* AXIR and AXIW clients */
-		mc_hub_vc_id(4, NIC);
+	reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC);
 	tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
 
 	wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
@@ -617,6 +611,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void)
 
 	wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
 	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+
+	reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
+	tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
 }
 
 /*******************************************************************************

plat/nvidia/tegra/soc/t194/plat_psci_handlers.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -77,6 +77,12 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
 	/* Sanity check the requested state id */
 	switch (state_id) {
 	case PSTATE_ID_CORE_IDLE:
+
+		/* Core idle request */
+		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
+		req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
+		break;
+
 	case PSTATE_ID_CORE_POWERDN:
 
 		/* Core powerdown request */
@@ -94,6 +100,25 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
 	return ret;
 }
 
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
+{
+	uint32_t cpu = plat_my_core_pos();
+	mce_cstate_info_t cstate_info = { 0 };
+
+	/* Program default wake mask */
+	cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
+	cstate_info.update_wake_mask = 1;
+	mce_update_cstate_info(&cstate_info);
+
+	/* Enter CPU idle */
+	(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
+				  (uint64_t)TEGRA_NVG_CORE_C6,
+				  t19x_percpu_data[cpu].wake_time,
+				  0U);
+
+	return PSCI_E_SUCCESS;
+}
+
 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	const plat_local_state_t *pwr_domain_state;
@@ -103,6 +128,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 	uint32_t val;
 	mce_cstate_info_t sc7_cstate_info = {
 		.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
+		.ccplex = (uint32_t)TEGRA_NVG_CG_CG7,
 		.system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
 		.system_state_force = 1U,
 		.update_wake_mask = 1U,
@@ -117,15 +143,13 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 	stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
 		TEGRA194_STATE_ID_MASK;
 
-	if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
-	    (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
+	if ((stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
 
-		/* Enter CPU idle/powerdown */
-		val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
-			(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
-		ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
-				t19x_percpu_data[cpu].wake_time, 0);
-		assert(ret == 0);
+		/* Enter CPU powerdown */
+		(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
+					  (uint64_t)TEGRA_NVG_CORE_C7,
+					  t19x_percpu_data[cpu].wake_time,
+					  0U);
 
 	} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
@@ -357,11 +381,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	 */
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
+#if ENABLE_STRICT_CHECKING_MODE
 		/*
 		 * Enable strict checking after programming the GSC for
 		 * enabling TZSRAM and TZDRAM
 		 */
 		mce_enable_strict_checking();
+#endif
 
 		/* Init SMMU */
 		tegra_smmu_init();
@@ -369,6 +395,52 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 		/* Resume SE, RNG1 and PKA1 */
 		tegra_se_resume();
 
+		/*
+		 * Program XUSB STREAMIDs
+		 * ======================
+		 * T19x XUSB has support for XUSB virtualization. It will
+		 * have one physical function (PF) and four Virtual functions
+		 * (VF)
+		 *
+		 * There were below two SIDs for XUSB until T186.
+		 * 1) #define TEGRA_SID_XUSB_HOST    0x1bU
+		 * 2) #define TEGRA_SID_XUSB_DEV    0x1cU
+		 *
+		 * We have below four new SIDs added for VF(s)
+		 * 3) #define TEGRA_SID_XUSB_VF0    0x5dU
+		 * 4) #define TEGRA_SID_XUSB_VF1    0x5eU
+		 * 5) #define TEGRA_SID_XUSB_VF2    0x5fU
+		 * 6) #define TEGRA_SID_XUSB_VF3    0x60U
+		 *
+		 * When virtualization is enabled then we have to disable SID
+		 * override and program above SIDs in below newly added SID
+		 * registers in XUSB PADCTL MMIO space. These registers are
+		 * TZ protected and so need to be done in ATF.
+		 *
+		 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
+		 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
+		 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
+		 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
+		 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
+		 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
+		 *
+		 * This change disables SID override and programs XUSB SIDs
+		 * in above registers to support both virtualization and
+		 * non-virtualization platforms
+		 */
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+
 		/*
 		 * Reset power state info for the last core doing SC7
 		 * entry and exit, we set deepest power state as CC7
@@ -403,8 +475,7 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 __dead2 void tegra_soc_prepare_system_off(void)
 {
 	/* System power off */
-
-	/* SC8 */
+	mce_system_shutdown();
 
 	wfi();
 
@@ -416,5 +487,8 @@ __dead2 void tegra_soc_prepare_system_off(void)
 
 int32_t tegra_soc_prepare_system_reset(void)
 {
+	/* System reboot */
+	mce_system_reboot();
+
 	return PSCI_E_SUCCESS;
 }

plat/nvidia/tegra/soc/t194/plat_setup.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -197,12 +197,13 @@ void plat_enable_console(int32_t id)
  ******************************************************************************/
 void plat_early_platform_setup(void)
 {
-
 	/* sanity check MCE firmware compatibility */
 	mce_verify_firmware_version();
 
-	/* Program XUSB STREAMIDs
-	 * Xavier XUSB has support for XUSB virtualization. It will have one
+	/*
+	 * Program XUSB STREAMIDs
+	 * ======================
+	 * T19x XUSB has support for XUSB virtualization. It will have one
 	 * physical function (PF) and four Virtual function (VF)
 	 *
 	 * There were below two SIDs for XUSB until T186.
@@ -227,14 +228,8 @@ void plat_early_platform_setup(void)
 	 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
 	 *
 	 * This change disables SID override and programs XUSB SIDs in
-	 * above registers to support both virtualization and non-virtualization
-	 *
-	 * Known Limitations:
-	 * If xusb interface disables SMMU in XUSB DT in non-virtualization
-	 * setup then there will be SMMU fault. We need to use WAR at
-	 * https:\\git-master.nvidia.com/r/1529227/ to the issue.
-	 *
-	 * More details can be found in the bug 1971161
+	 * above registers to support both virtualization and
+	 * non-virtualization platforms
 	 */
 	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
 		XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
@@ -298,9 +293,11 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
 
 void plat_late_platform_setup(void)
 {
+#if ENABLE_STRICT_CHECKING_MODE
 	/*
 	 * Enable strict checking after programming the GSC for
 	 * enabling TZSRAM and TZDRAM
 	 */
 	mce_enable_strict_checking();
+#endif
 }

plat/nvidia/tegra/soc/t194/platform_t194.mk

 #
-# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,17 +8,8 @@
 ENABLE_CONSOLE_SPE			:= 0
 $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
-ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS	:= 0
-$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
-
-RELOCATE_TO_BL31_BASE			:= 1
-$(eval $(call add_define,RELOCATE_TO_BL31_BASE))
-
-ENABLE_CHIP_VERIFICATION_HARNESS	:= 0
-$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
-
-ENABLE_SMMU_DEVICE			:= 1
-$(eval $(call add_define,ENABLE_SMMU_DEVICE))
+ENABLE_STRICT_CHECKING_MODE	:= 1
+$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
 
 RESET_TO_BL31				:= 1