Merge changes from topic "fdt_wrappers_rework" into integration

* changes:
  arm_fpga: Read UART address from DT
  arm_fpga: Read GICD and GICR base addresses from DT
  arm_fpga: Read generic timer counter frequency from DT
  arm_fpga: Use Generic UART

plat/arm/board/arm_fpga/aarch64/fpga_helpers.S

@@ -108,8 +108,6 @@ endfunc plat_fpga_calc_core_pos
 
 func plat_crash_console_init
 	mov_imm	x0, PLAT_FPGA_CRASH_UART_BASE
-	mov_imm	x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ
-	mov_imm	x2, PLAT_FPGA_CONSOLE_BAUDRATE
 	b	console_pl011_core_init
 endfunc plat_crash_console_init
 

plat/arm/board/arm_fpga/fpga_bl31_setup.c

@@ -5,8 +5,11 @@
  */
 
 #include <assert.h>
-#include <lib/mmio.h>
+
+#include <common/fdt_wrappers.h>
 #include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <libfdt.h>
 
 #include <plat/common/platform.h>
 #include <platform_def.h>
@@ -76,7 +79,16 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 
 unsigned int plat_get_syscnt_freq2(void)
 {
-	return FPGA_TIMER_FREQUENCY;
+	const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+	int node;
+
+	node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer");
+	if (node < 0) {
+		return FPGA_DEFAULT_TIMER_FREQUENCY;
+	}
+
+	return fdt_read_uint32_default(fdt, node, "clock-frequency",
+				       FPGA_DEFAULT_TIMER_FREQUENCY);
 }
 
 void bl31_plat_enable_mmu(uint32_t flags)

plat/arm/board/arm_fpga/fpga_console.c

@@ -4,8 +4,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <drivers/console.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <common/fdt_wrappers.h>
 #include <drivers/arm/pl011.h>
+#include <drivers/console.h>
 
 #include <platform_def.h>
 
@@ -13,10 +17,21 @@ static console_t console;
 
 void fpga_console_init(void)
 {
-	(void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE,
-		PLAT_FPGA_BOOT_UART_CLK_IN_HZ,
-		PLAT_FPGA_CONSOLE_BAUDRATE,
-		&console);
+	const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+	uintptr_t base_addr = PLAT_FPGA_CRASH_UART_BASE;
+	int node;
+
+	/*
+	 * Try to read the UART base address from the DT, by chasing the
+	 * stdout-path property of the chosen node.
+	 * If this does not work, use the crash console address as a fallback.
+	 */
+	node = fdt_get_stdout_node_offset(fdt);
+	if (node >= 0) {
+		fdt_get_reg_props_by_index(fdt, node, 0, &base_addr, NULL);
+	}
+
+	(void)console_pl011_register(base_addr, 0, 0, &console);
 
 	console_set_scope(&console, CONSOLE_FLAG_BOOT |
 		CONSOLE_FLAG_RUNTIME);

plat/arm/board/arm_fpga/fpga_def.h

@@ -23,18 +23,16 @@
 #define FPGA_MAX_PE_PER_CPU			4
 
 #define FPGA_PRIMARY_CPU			0x0
-
 /*******************************************************************************
  * FPGA image memory map related constants
  ******************************************************************************/
 
-/* UART base address and clock frequency, as configured by the image */
-#define PLAT_FPGA_BOOT_UART_BASE 		0x7ff80000
-#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 		10000000
-
-#define PLAT_FPGA_CRASH_UART_BASE		PLAT_FPGA_BOOT_UART_BASE
-#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ		PLAT_FPGA_BOOT_UART_CLK_IN_HZ
+/*
+ * UART base address, just for the crash console, as a fallback.
+ * The actual console UART address is taken from the DT.
+ */
+#define PLAT_FPGA_CRASH_UART_BASE		0x7ff80000
 
-#define FPGA_TIMER_FREQUENCY			10000000
+#define FPGA_DEFAULT_TIMER_FREQUENCY		10000000
 
 #endif

plat/arm/board/arm_fpga/fpga_gicv3.c

@@ -4,9 +4,13 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
 #include <drivers/arm/gicv3.h>
 #include <drivers/arm/gic_common.h>
+#include <libfdt.h>
 
+#include <platform_def.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
 
@@ -22,9 +26,7 @@ static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
 	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
 }
 
-static const gicv3_driver_data_t fpga_gicv3_driver_data = {
-	.gicd_base = GICD_BASE,
-	.gicr_base = GICR_BASE,
+static gicv3_driver_data_t fpga_gicv3_driver_data = {
 	.interrupt_props = fpga_interrupt_props,
 	.interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
 	.rdistif_num = PLATFORM_CORE_COUNT,
@@ -34,6 +36,30 @@ static const gicv3_driver_data_t fpga_gicv3_driver_data = {
 
 void plat_fpga_gic_init(void)
 {
+	const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
+	if (node < 0) {
+		WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
+		return;
+	}
+
+	/* TODO: Assuming only empty "ranges;" properties up the bus path. */
+	ret = fdt_get_reg_props_by_index(fdt, node, 0,
+				 &fpga_gicv3_driver_data.gicd_base, NULL);
+	if (ret < 0) {
+		WARN("Could not read GIC distributor address from DT.\n");
+		return;
+	}
+
+	ret = fdt_get_reg_props_by_index(fdt, node, 1,
+				 &fpga_gicv3_driver_data.gicr_base, NULL);
+	if (ret < 0) {
+		WARN("Could not read GIC redistributor address from DT.\n");
+		return;
+	}
+
 	gicv3_driver_init(&fpga_gicv3_driver_data);
 	gicv3_distif_init();
 	gicv3_rdistif_init(plat_my_core_pos());

plat/arm/board/arm_fpga/include/platform_def.h

@@ -35,9 +35,6 @@
 #define BL31_LIMIT			UL(0x01000000)
 #endif
 
-#define GICD_BASE			0x30000000
-#define GICR_BASE			0x30040000
-
 #define PLAT_SDEI_NORMAL_PRI		0x70
 
 #define ARM_IRQ_SEC_PHY_TIMER		29
@@ -87,6 +84,4 @@
 #define PLAT_FPGA_HOLD_STATE_WAIT	0
 #define PLAT_FPGA_HOLD_STATE_GO		1
 
-#define PLAT_FPGA_CONSOLE_BAUDRATE	38400
-
 #endif

plat/arm/board/arm_fpga/platform.mk

@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+include lib/libfdt/libfdt.mk
+
 RESET_TO_BL31 := 1
 ifeq (${RESET_TO_BL31}, 0)
 $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
@@ -38,6 +40,8 @@ USE_COHERENT_MEM	:=	0
 # This can be overridden depending on CPU(s) used in the FPGA image
 HW_ASSISTED_COHERENCY	:=	1
 
+PL011_GENERIC_UART	:=	1
+
 FPGA_CPU_LIBS	:=	lib/cpus/${ARCH}/aem_generic.S
 
 # select a different set of CPU files, depending on whether we compile for
@@ -80,7 +84,8 @@ PLAT_INCLUDES		:=	-Iplat/arm/board/arm_fpga/include
 
 PLAT_BL_COMMON_SOURCES	:=	plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
 
-BL31_SOURCES		+=	drivers/delay_timer/delay_timer.c		\
+BL31_SOURCES		+=	common/fdt_wrappers.c				\
+				drivers/delay_timer/delay_timer.c		\
 				drivers/delay_timer/generic_delay_timer.c	\
 				drivers/arm/pl011/${ARCH}/pl011_console.S	\
 				plat/common/plat_psci_common.c			\