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Commit 7e532c4b authored by Jorge Ramirez-Ortiz's avatar Jorge Ramirez-Ortiz Committed by ldts
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rcar-gen3: initial commit for the rcar-gen3 boards 

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power manage...
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plat/renesas/rcar/include/registers/lifec_registers.h 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef LIFEC_REGISTER_H__
#define LIFEC_REGISTER_H__
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif
plat/renesas/rcar/plat_image_load.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
extern void bl2_plat_flush_bl31_params(void);
/*******************************************************************************
* This function flushes the data structures so that they are visible
* in memory for the next BL image.
******************************************************************************/
void plat_flush_next_bl_params(void)
{
#if IMAGE_BL2
bl2_plat_flush_bl31_params();
#endif
}
/*******************************************************************************
* This function returns the list of loadable images.
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
return get_bl_load_info_from_mem_params_desc();
}
/*******************************************************************************
* This function returns the list of executable images.
******************************************************************************/
bl_params_t *plat_get_next_bl_params(void)
{
return get_next_bl_params_from_mem_params_desc();
}
plat/renesas/rcar/plat_pm.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <bakery_lock.h>
#include <bl_common.h>
#include <cci.h>
#include <debug.h>
#include <errno.h>
#include <gicv2.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
#include "iic_dvfs.h"
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
#define DVFS_SET_VID_0V (0x00)
#define P_ALL_OFF (0x80)
#define KEEPON_DDR1C (0x08)
#define KEEPON_DDR0C (0x04)
#define KEEPON_DDR1 (0x02)
#define KEEPON_DDR0 (0x01)
#define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
#define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data")));
extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
extern u_register_t rcar_boot_mpidr;
#if (RCAR_GEN3_ULCB == 1)
extern void rcar_cpld_reset_cpu(void);
#endif
static uintptr_t rcar_sec_entrypoint;
static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
{
mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
uint64_t linear_id = plat_core_pos_by_mpidr(mpidr);
unsigned long range;
rcar_mboxes[linear_id].value = address;
range = (unsigned long)&rcar_mboxes[linear_id];
flush_dcache_range(range, sizeof(range));
}
static void rcar_cpu_standby(plat_local_state_t cpu_state)
{
uint32_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_IRQ_BIT);
dsb();
wfi();
write_scr_el3(scr_el3);
}
static int rcar_pwr_domain_on(u_register_t mpidr)
{
rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
rcar_pwrc_cpuon(mpidr);
return PSCI_E_SUCCESS;
}
static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
uint32_t cluster_type = rcar_pwrc_get_cluster();
unsigned long mpidr = read_mpidr_el1();
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_enable();
rcar_pwrc_disable_interrupt_wakeup(mpidr);
rcar_program_mailbox(mpidr, 0);
gicv2_cpuif_enable();
gicv2_pcpu_distif_init();
}
static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
{
uint32_t cluster_type = rcar_pwrc_get_cluster();
unsigned long mpidr = read_mpidr_el1();
gicv2_cpuif_disable();
rcar_pwrc_cpuoff(mpidr);
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_disable();
rcar_pwrc_clusteroff(mpidr);
}
}
static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
{
uint32_t cluster_type = rcar_pwrc_get_cluster();
unsigned long mpidr = read_mpidr_el1();
if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
return;
rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
rcar_pwrc_enable_interrupt_wakeup(mpidr);
gicv2_cpuif_disable();
rcar_pwrc_cpuoff(mpidr);
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_disable();
rcar_pwrc_clusteroff(mpidr);
}
#if RCAR_SYSTEM_SUSPEND
if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
rcar_pwrc_suspend_to_ram();
#endif
}
static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
*target_state)
{
uint32_t cluster_type = rcar_pwrc_get_cluster();
if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
goto finish;
plat_rcar_gic_driver_init();
plat_rcar_gic_init();
if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_init();
rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer);
/* start generic timer */
write_cntfrq_el0(plat_get_syscnt_freq2());
mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
rcar_pwrc_setup();
#if RCAR_SYSTEM_SUSPEND
rcar_pwrc_init_suspend_to_ram();
#endif
finish:
rcar_pwr_domain_on_finish(target_state);
}
static void __dead2 rcar_system_off(void)
{
#if PMIC_ROHM_BD9571
#if PMIC_LEVEL_MODE
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
#else
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
#endif
#else
uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
int32_t rtn_on;
rtn_on = cpu_on_check(cpu);
if (cpu == rcar_boot_mpidr)
panic();
if (rtn_on)
panic();
rcar_pwrc_cpuoff(cpu);
rcar_pwrc_clusteroff(cpu);
#endif /* PMIC_ROHM_BD9571 */
wfi();
ERROR("RCAR System Off: operation not handled.\n");
panic();
}
static void __dead2 rcar_system_reset(void)
{
#if PMIC_ROHM_BD9571
#if PMIC_LEVEL_MODE
#if RCAR_SYSTEM_RESET_KEEPON_DDR
uint8_t mode;
int32_t error;
rcar_pwrc_code_copy_to_system_ram();
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
if (error) {
ERROR("Failed send KEEP10 magic ret=%d \n", error);
goto done;
}
error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
if (error) {
ERROR("Failed recieve BKUP_Mode_Cnt ret=%d \n", error);
goto done;
}
mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
if (error) {
ERROR("Failed send KEEPON_DDRx ret=%d \n", error);
goto done;
}
rcar_pwrc_set_suspend_to_ram();
done:
#else
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
#endif
#else
#if (RCAR_GEN3_ULCB == 1)
rcar_cpld_reset_cpu();
#endif
#endif
#else
rcar_pwrc_system_reset();
#endif
wfi();
ERROR("RCAR System Reset: operation not handled.\n");
panic();
}
static int rcar_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
unsigned int pstate = psci_get_pstate_type(power_state);
uint32_t i;
if (pstate == PSTATE_TYPE_STANDBY) {
if (pwr_lvl != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
} else {
for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
}
if (psci_get_pstate_id(power_state))
return PSCI_E_INVALID_PARAMS;
return PSCI_E_SUCCESS;
}
#if RCAR_SYSTEM_SUSPEND
static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU;
int i;
if (mpidr != rcar_boot_mpidr)
goto deny;
for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
return;
deny:
/* deny system suspend entry */
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN;
for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
}
#endif
static const plat_psci_ops_t rcar_plat_psci_ops = {
.cpu_standby = rcar_cpu_standby,
.pwr_domain_on = rcar_pwr_domain_on,
.pwr_domain_off = rcar_pwr_domain_off,
.pwr_domain_suspend = rcar_pwr_domain_suspend,
.pwr_domain_on_finish = rcar_pwr_domain_on_finish,
.pwr_domain_suspend_finish = rcar_pwr_domain_suspend_finish,
.system_off = rcar_system_off,
.system_reset = rcar_system_reset,
.validate_power_state = rcar_validate_power_state,
#if RCAR_SYSTEM_SUSPEND
.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
#endif
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops)
{
*psci_ops = &rcar_plat_psci_ops;
rcar_sec_entrypoint = sec_entrypoint;
#if RCAR_SYSTEM_SUSPEND
rcar_pwrc_init_suspend_to_ram();
#endif
return 0;
}
plat/renesas/rcar/plat_storage.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <debug.h>
#include <io_driver.h>
#include <io_storage.h>
#include <io_semihosting.h>
#include <platform_def.h>
#include <string.h>
#include "io_common.h"
#include "io_rcar.h"
#include "io_memdrv.h"
#include "io_emmcdrv.h"
#include "io_private.h"
static uintptr_t emmcdrv_dev_handle;
static uintptr_t memdrv_dev_handle;
static uintptr_t rcar_dev_handle;
static uintptr_t boot_io_drv_id;
static const io_block_spec_t rcar_block_spec = {
.offset = FLASH0_BASE,
.length = FLASH0_SIZE
};
static const io_block_spec_t bl2_file_spec = {
.offset = BL2_IMAGE_ID,
};
static const io_block_spec_t bl31_file_spec = {
.offset = BL31_IMAGE_ID,
};
static const io_block_spec_t bl32_file_spec = {
.offset = BL32_IMAGE_ID,
};
static const io_block_spec_t bl33_file_spec = {
.offset = BL33_IMAGE_ID,
};
static const io_block_spec_t bl332_file_spec = {
.offset = BL332_IMAGE_ID,
};
static const io_block_spec_t bl333_file_spec = {
.offset = BL333_IMAGE_ID,
};
static const io_block_spec_t bl334_file_spec = {
.offset = BL334_IMAGE_ID,
};
static const io_block_spec_t bl335_file_spec = {
.offset = BL335_IMAGE_ID,
};
static const io_block_spec_t bl336_file_spec = {
.offset = BL336_IMAGE_ID,
};
static const io_block_spec_t bl337_file_spec = {
.offset = BL337_IMAGE_ID,
};
static const io_block_spec_t bl338_file_spec = {
.offset = BL338_IMAGE_ID,
};
#if TRUSTED_BOARD_BOOT
static const io_block_spec_t trusted_key_cert_file_spec = {
.offset = TRUSTED_KEY_CERT_ID,
};
static const io_block_spec_t bl31_key_cert_file_spec = {
.offset = SOC_FW_KEY_CERT_ID,
};
static const io_block_spec_t bl32_key_cert_file_spec = {
.offset = TRUSTED_OS_FW_KEY_CERT_ID,
};
static const io_block_spec_t bl33_key_cert_file_spec = {
.offset = NON_TRUSTED_FW_KEY_CERT_ID,
};
static const io_block_spec_t bl332_key_cert_file_spec = {
.offset = BL332_KEY_CERT_ID,
};
static const io_block_spec_t bl333_key_cert_file_spec = {
.offset = BL333_KEY_CERT_ID,
};
static const io_block_spec_t bl334_key_cert_file_spec = {
.offset = BL334_KEY_CERT_ID,
};
static const io_block_spec_t bl335_key_cert_file_spec = {
.offset = BL335_KEY_CERT_ID,
};
static const io_block_spec_t bl336_key_cert_file_spec = {
.offset = BL336_KEY_CERT_ID,
};
static const io_block_spec_t bl337_key_cert_file_spec = {
.offset = BL337_KEY_CERT_ID,
};
static const io_block_spec_t bl338_key_cert_file_spec = {
.offset = BL338_KEY_CERT_ID,
};
static const io_block_spec_t bl31_cert_file_spec = {
.offset = SOC_FW_CONTENT_CERT_ID,
};
static const io_block_spec_t bl32_cert_file_spec = {
.offset = TRUSTED_OS_FW_CONTENT_CERT_ID,
};
static const io_block_spec_t bl33_cert_file_spec = {
.offset = NON_TRUSTED_FW_CONTENT_CERT_ID,
};
static const io_block_spec_t bl332_cert_file_spec = {
.offset = BL332_CERT_ID,
};
static const io_block_spec_t bl333_cert_file_spec = {
.offset = BL333_CERT_ID,
};
static const io_block_spec_t bl334_cert_file_spec = {
.offset = BL334_CERT_ID,
};
static const io_block_spec_t bl335_cert_file_spec = {
.offset = BL335_CERT_ID,
};
static const io_block_spec_t bl336_cert_file_spec = {
.offset = BL336_CERT_ID,
};
static const io_block_spec_t bl337_cert_file_spec = {
.offset = BL337_CERT_ID,
};
static const io_block_spec_t bl338_cert_file_spec = {
.offset = BL338_CERT_ID,
};
#endif
static int32_t open_emmcdrv(const uintptr_t spec);
static int32_t open_memmap(const uintptr_t spec);
static int32_t open_rcar(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int32_t(*check) (const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
[FIP_IMAGE_ID] = {
&memdrv_dev_handle,
(uintptr_t) &rcar_block_spec,
&open_memmap},
[BL2_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl2_file_spec,
&open_rcar},
[BL31_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl31_file_spec,
&open_rcar},
[BL32_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl32_file_spec,
&open_rcar},
[BL33_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl33_file_spec,
&open_rcar},
[BL332_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl332_file_spec,
&open_rcar},
[BL333_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl333_file_spec,
&open_rcar},
[BL334_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl334_file_spec,
&open_rcar},
[BL335_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl335_file_spec,
&open_rcar},
[BL336_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl336_file_spec,
&open_rcar},
[BL337_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl337_file_spec,
&open_rcar},
[BL338_IMAGE_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl338_file_spec,
&open_rcar},
#if TRUSTED_BOARD_BOOT
[TRUSTED_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &trusted_key_cert_file_spec,
&open_rcar},
[SOC_FW_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl31_key_cert_file_spec,
&open_rcar},
[TRUSTED_OS_FW_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl32_key_cert_file_spec,
&open_rcar},
[NON_TRUSTED_FW_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl33_key_cert_file_spec,
&open_rcar},
[BL332_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl332_key_cert_file_spec,
&open_rcar},
[BL333_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl333_key_cert_file_spec,
&open_rcar},
[BL334_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl334_key_cert_file_spec,
&open_rcar},
[BL335_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl335_key_cert_file_spec,
&open_rcar},
[BL336_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl336_key_cert_file_spec,
&open_rcar},
[BL337_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl337_key_cert_file_spec,
&open_rcar},
[BL338_KEY_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl338_key_cert_file_spec,
&open_rcar},
[SOC_FW_CONTENT_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl31_cert_file_spec,
&open_rcar},
[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl32_cert_file_spec,
&open_rcar},
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl33_cert_file_spec,
&open_rcar},
[BL332_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl332_cert_file_spec,
&open_rcar},
[BL333_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl333_cert_file_spec,
&open_rcar},
[BL334_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl334_cert_file_spec,
&open_rcar},
[BL335_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl335_cert_file_spec,
&open_rcar},
[BL336_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl336_cert_file_spec,
&open_rcar},
[BL337_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl337_cert_file_spec,
&open_rcar},
[BL338_CERT_ID] = {
&rcar_dev_handle,
(uintptr_t) &bl338_cert_file_spec,
&open_rcar}, {
#else
{
#endif
0, 0, 0}
};
static io_drv_spec_t io_drv_spec_memdrv = {
FLASH0_BASE,
FLASH0_SIZE,
0,
};
static io_drv_spec_t io_drv_spec_emmcdrv = {
0,
0,
0,
};
static struct plat_io_policy drv_policies[]
__attribute__ ((section(".data"))) = {
/* FLASH_DEV_ID */
{
&memdrv_dev_handle,
(uintptr_t) &io_drv_spec_memdrv, &open_memmap,},
/* EMMC_DEV_ID */
{
&emmcdrv_dev_handle,
(uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv,}
};
static int32_t open_rcar(const uintptr_t spec)
{
return io_dev_init(rcar_dev_handle, boot_io_drv_id);
}
static int32_t open_memmap(const uintptr_t spec)
{
uintptr_t handle;
int32_t result;
result = io_dev_init(memdrv_dev_handle, 0);
if (result != IO_SUCCESS)
return result;
result = io_open(memdrv_dev_handle, spec, &handle);
if (result == IO_SUCCESS)
io_close(handle);
return result;
}
static int32_t open_emmcdrv(const uintptr_t spec)
{
return io_dev_init(emmcdrv_dev_handle, 0);
}
void rcar_io_setup(void)
{
const io_dev_connector_t *memmap;
const io_dev_connector_t *rcar;
boot_io_drv_id = FLASH_DEV_ID;
rcar_register_io_dev(&rcar);
rcar_register_io_dev_memdrv(&memmap);
io_dev_open(rcar, 0, &rcar_dev_handle);
io_dev_open(memmap, 0, &memdrv_dev_handle);
}
void rcar_io_emmc_setup(void)
{
const io_dev_connector_t *rcar;
const io_dev_connector_t *emmc;
boot_io_drv_id = EMMC_DEV_ID;
rcar_register_io_dev(&rcar);
rcar_register_io_dev_emmcdrv(&emmc);
io_dev_open(rcar, 0, &rcar_dev_handle);
io_dev_open(emmc, 0, &emmcdrv_dev_handle);
}
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
const struct plat_io_policy *policy;
int result;
policy = &policies[image_id];
result = policy->check(policy->image_spec);
if (result != IO_SUCCESS)
return result;
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
return IO_SUCCESS;
}
int32_t plat_get_drv_source(uint32_t io_drv_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
const struct plat_io_policy *policy;
int32_t result;
policy = &drv_policies[io_drv_id];
result = policy->check(policy->image_spec);
if (result != IO_SUCCESS)
return result;
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
return IO_SUCCESS;
}
plat/renesas/rcar/plat_topology.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <debug.h>
#include <platform_def.h>
#include <psci.h>
static const unsigned char rcar_power_domain_tree_desc[] = {
1,
PLATFORM_CLUSTER_COUNT,
PLATFORM_CLUSTER0_CORE_COUNT,
PLATFORM_CLUSTER1_CORE_COUNT
};
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return rcar_power_domain_tree_desc;
}
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
unsigned int cluster_id, cpu_id;
mpidr &= MPIDR_AFFINITY_MASK;
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
return -1;
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
return -1;
if (cluster_id == 0 && cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT)
return -1;
if (cluster_id == 1 && cpu_id >= PLATFORM_CLUSTER1_CORE_COUNT)
return -1;
return (cpu_id + cluster_id * PLATFORM_CLUSTER0_CORE_COUNT);
}
plat/renesas/rcar/platform.mk 0 → 100644
View file @ 7e532c4b
This diff is collapsed.
tools/renesas/rcar_layout_create/makefile 0 → 100644
View file @ 7e532c4b
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
###################################################
# makefile
###################################################
#output file name
FILE_NAME_SA0 = bootparam_sa0
FILE_NAME_SA6 = cert_header_sa6
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf
#object file name
OBJ_FILE_SA0 = sa0.o
OBJ_FILE_SA6 = sa6.o
#linker script name
MEMORY_DEF_SA0 = sa0.ld.S
MEMORY_DEF_SA6 = sa6.ld.S
###################################################
# Convenience function for adding build definitions
# $(eval $(call add_define,FOO)) will have:
# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
# Process RCAR_SA0_SIZE flag
ifndef RCAR_SA0_SIZE
RCAR_SA0_SIZE := 1
else
ifeq (${RCAR_SA0_SIZE},0)
RCAR_SA0_SIZE := 0
else
RCAR_SA0_SIZE := 1
endif
endif
$(eval $(call add_define,RCAR_SA0_SIZE))
# Process RCAR_SA6_TYPE flag
ifndef RCAR_SA6_TYPE
RCAR_SA6_TYPE := 0
else
ifeq (${RCAR_SA6_TYPE},0)
RCAR_SA6_TYPE := 0
else
RCAR_SA6_TYPE := 1
endif
endif
$(eval $(call add_define,RCAR_SA6_TYPE))
###################################################
#c compiler
CC = $(CROSS_COMPILE)gcc
CFLAGS += ${DEFINES}
CFLAGS += -I../../include/lib/stdlib
#Linker
LD = $(CROSS_COMPILE)ld
#objcopy
objcopy = $(CROSS_COMPILE)objcopy
#clean
CL = rm -f
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
###################################################
# Linker
###################################################
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
$(LD) $(OBJ_FILE_SA0) \
-T $(MEMORY_DEF_SA0) \
-o $(OUTPUT_FILE_SA0) \
-Map $(FILE_NAME_SA0).map \
$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
$(LD) $(OBJ_FILE_SA6) \
-T $(MEMORY_DEF_SA6) \
-o $(OUTPUT_FILE_SA6) \
-Map $(FILE_NAME_SA6).map \
$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
###################################################
# Compile
###################################################
%.o:../%.c
$(CC) -c -I $< -o $@
.PHONY: clean
clean:
$(CL) *.bin *.map *.srec *.elf *.o
tools/renesas/rcar_layout_create/sa0.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_SA0_SIZE_SMALL (0) /* for E3 */
#define RCAR_SA0_SIZE_NORMAL (1) /* for H3/M3/M3N */
#define BL2_ADDRESS (0xE6304000) /* BL2 start address */
#if (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL)
#define BL2_SIZE (80*1024/4) /* BL2 size is 80KB(0x00005000) */
#else /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
#define BL2_SIZE (170*1024/4) /* BL2 size is 170KB(0x0000AA00) */
#endif /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
/* SA0 */
/* 0x00000000 */
const unsigned int __attribute__ ((section (".sa0_bootrom"))) bootrom_paramA = 0x00000100;
/* 0x00000080 (Map Type 3 for eMMC Boot)*/
/* 0x000001D4 */
const unsigned int __attribute__ ((section (".sa0_bl2dst_addr3"))) bl2dst_addr3 = BL2_ADDRESS;
/* 0x000002E4 */
const unsigned int __attribute__ ((section (".sa0_bl2dst_size3"))) bl2dst_size3 = BL2_SIZE;
/* 0x00000C00 (Map Type 1 for HyperFlash/QSPI Flash Boot)*/
/* 0x00000D54 */
const unsigned int __attribute__ ((section (".sa0_bl2dst_addr1"))) bl2dst_addr1 = BL2_ADDRESS;
/* 0x00000E64 */
const unsigned int __attribute__ ((section (".sa0_bl2dst_size1"))) bl2dst_size1 = BL2_SIZE;
tools/renesas/rcar_layout_create/sa0.ld.S 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
SECTIONS
{
. = 0x00000000;
.rodata : {
KEEP(*(.sa0_bootrom))
/* Map Type 3 for eMMC Boot */
/* A-side IPL content cert "Start Address" */
. = 0x000001D4; /* H'00000080 + H'00000154 */
KEEP(*(.sa0_bl2dst_addr3))
/* A-side IPL content cert "Size" */
. = 0x000002E4; /* H'00000080 + H'00000264 */
KEEP(*(.sa0_bl2dst_size3))
/* Map Type 1 for HyperFlash/QSPI Flash Boot */
/* A-side IPL content cert "Start Address" */
. = 0x00000D54; /* H'00000C00 + H'00000154 */
KEEP(*(.sa0_bl2dst_addr1))
/* A-side IPL content cert "Size" */
. = 0x00000E64; /* H'00000C00 + H'00000264 */
KEEP(*(.sa0_bl2dst_size1))
}
}
tools/renesas/rcar_layout_create/sa6.c 0 → 100644
View file @ 7e532c4b
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#define RCAR_SA6_TYPE_HYPERFLASH (0)
#define RCAR_SA6_TYPE_EMMC (1)
#if (RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH)
/* Number of content cert for Non-secure Target Program(BL33x) */
#define RCAR_IMAGE_NUM (0x00000001U)
/* Source address on flash for BL31 */
#define RCAR_BL31SRC_ADDRESS (0x001C0000U)
/* Reserved */
#define RCAR_BL31_PARTITION (0x00000000U)
/* Source address on flash for BL32 */
#define RCAR_BL32SRC_ADDRESS (0x00200000U)
/* Reserved */
#define RCAR_BL32_PARTITION (0x00000000U)
/* Source address on flash for BL33 */
#define RCAR_BL33SRC_ADDRESS (0x00640000U)
/* Reserved */
#define RCAR_BL33_PARTITION (0x00000000U)
#define RCAR_BL332SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL332_PARTITION (0x00000000U)
#define RCAR_BL333SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL333_PARTITION (0x00000000U)
#define RCAR_BL334SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL334_PARTITION (0x00000000U)
#define RCAR_BL335SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL335_PARTITION (0x00000000U)
#define RCAR_BL336SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL336_PARTITION (0x00000000U)
#define RCAR_BL337SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL337_PARTITION (0x00000000U)
#define RCAR_BL338SRC_ADDRESS (0x00000000U)
/* Reserved */
#define RCAR_BL338_PARTITION (0x00000000U)
#else /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */
/* Number of content cert for Non-secure Target Program(BL33x) */
#define RCAR_IMAGE_NUM (0x00000001U)
/* Source address on eMMC for BL31 */
#define RCAR_BL31SRC_ADDRESS (0x00040000U)
/* Source partition on eMMC for BL31 */
#define RCAR_BL31_PARTITION (0x00000001U)
/* Source address on eMMC for BL32 */
#define RCAR_BL32SRC_ADDRESS (0x00200000U)
/* Source partition on eMMC for BL32 */
#define RCAR_BL32_PARTITION (0x00000001U)
/* Source address on eMMC for BL33 */
#define RCAR_BL33SRC_ADDRESS (0x00000000U)
/* Source partition on eMMC for BL33 */
#define RCAR_BL33_PARTITION (0x00000002U)
/* Reserved */
#define RCAR_BL332SRC_ADDRESS (0x00000000U)
#define RCAR_BL332_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL333SRC_ADDRESS (0x00000000U)
#define RCAR_BL333_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL334SRC_ADDRESS (0x00000000U)
#define RCAR_BL334_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL335SRC_ADDRESS (0x00000000U)
#define RCAR_BL335_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL336SRC_ADDRESS (0x00000000U)
#define RCAR_BL336_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL337SRC_ADDRESS (0x00000000U)
#define RCAR_BL337_PARTITION (0x00000000U)
/* Reserved */
#define RCAR_BL338SRC_ADDRESS (0x00000000U)
#define RCAR_BL338_PARTITION (0x00000000U)
#endif /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */
/* Destination address for BL31 */
#define RCAR_BL31DST_ADDRESS (0x44000000U)
#define RCAR_BL31DST_ADDRESSH (0x00000000U)
/* Destination size for BL31 */
#define RCAR_BL31DST_SIZE (0x00004000U)
/* Destination address for BL32 */
#define RCAR_BL32DST_ADDRESS (0x44100000U)
#define RCAR_BL32DST_ADDRESSH (0x00000000U)
/* Destination size for BL32 */
#define RCAR_BL32DST_SIZE (0x00040000U)
/* Destination address for BL33 */
#define RCAR_BL33DST_ADDRESS (0x50000000U)
#define RCAR_BL33DST_ADDRESSH (0x00000000U)
/* Destination size for BL33 */
#define RCAR_BL33DST_SIZE (0x00040000U)
/* Reserved */
#define RCAR_BL332DST_ADDRESS (0x00000000U)
#define RCAR_BL332DST_ADDRESSH (0x00000000U)
#define RCAR_BL332DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL333DST_ADDRESS (0x00000000U)
#define RCAR_BL333DST_ADDRESSH (0x00000000U)
#define RCAR_BL333DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL334DST_ADDRESS (0x00000000U)
#define RCAR_BL334DST_ADDRESSH (0x00000000U)
#define RCAR_BL334DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL335DST_ADDRESS (0x00000000U)
#define RCAR_BL335DST_ADDRESSH (0x00000000U)
#define RCAR_BL335DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL336DST_ADDRESS (0x00000000U)
#define RCAR_BL336DST_ADDRESSH (0x00000000U)
#define RCAR_BL336DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL337DST_ADDRESS (0x00000000U)
#define RCAR_BL337DST_ADDRESSH (0x00000000U)
#define RCAR_BL337DST_SIZE (0x00000000U)
/* Reserved */
#define RCAR_BL338DST_ADDRESS (0x00000000U)
#define RCAR_BL338DST_ADDRESSH (0x00000000U)
#define RCAR_BL338DST_SIZE (0x00000000U)
/* SA6 */
const uint64_t __attribute__ ((section (".sa6_image_num"))) image_num = RCAR_IMAGE_NUM;
const uint64_t __attribute__ ((section (".sa6_bl31src_addr"))) bl31src_addr = RCAR_BL31SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl31partition"))) bl31partition = RCAR_BL31_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl32src_addr"))) bl32src_addr = RCAR_BL32SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl32partition"))) bl32partition = RCAR_BL32_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl33src_addr"))) bl33src_addr = RCAR_BL33SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl33partition"))) bl33partition = RCAR_BL33_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl332src_addr"))) bl332src_addr = RCAR_BL332SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl332partition")))bl332partition = RCAR_BL332_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl333src_addr"))) bl333src_addr = RCAR_BL333SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl333partition")))bl333partition = RCAR_BL333_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl334src_addr"))) bl334src_addr = RCAR_BL334SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl334partition")))bl334partition = RCAR_BL334_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl335src_addr"))) bl335src_addr = RCAR_BL335SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl335partition")))bl335partition = RCAR_BL335_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl336src_addr"))) bl336src_addr = RCAR_BL336SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl336partition")))bl336partition = RCAR_BL336_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl337src_addr"))) bl337src_addr = RCAR_BL337SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl337partition")))bl337partition = RCAR_BL337_PARTITION;
const uint64_t __attribute__ ((section (".sa6_bl338src_addr"))) bl338src_addr = RCAR_BL338SRC_ADDRESS;
const uint64_t __attribute__ ((section (".sa6_bl338partition")))bl338partition = RCAR_BL338_PARTITION;
const uint32_t __attribute__ ((section (".sa6_bl31dst_addr"))) bl31dst_addr = RCAR_BL31DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl31dst_addrh"))) bl31dst_addrh = RCAR_BL31DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl31dst_size"))) bl31dst_size = RCAR_BL31DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl32dst_addr"))) bl32dst_addr = RCAR_BL32DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl32dst_addrh"))) bl32dst_addrh = RCAR_BL32DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl32dst_size"))) bl32dst_size = RCAR_BL32DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl33dst_addr"))) bl33dst_addr = RCAR_BL33DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl33dst_addrh"))) bl33dst_addrh = RCAR_BL33DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl33dst_size"))) bl33dst_size = RCAR_BL33DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl332dst_addr"))) bl332dst_addr = RCAR_BL332DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl332dst_addrh")))bl332dst_addrh = RCAR_BL332DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl332dst_size"))) bl332dst_size = RCAR_BL332DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl333dst_addr"))) bl333dst_addr = RCAR_BL333DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl333dst_addrh")))bl333dst_addrh = RCAR_BL333DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl333dst_size"))) bl333dst_size = RCAR_BL333DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl334dst_addr"))) bl334dst_addr = RCAR_BL334DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl334dst_addrh")))bl334dst_addrh = RCAR_BL334DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl334dst_size"))) bl334dst_size = RCAR_BL334DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl335dst_addr"))) bl335dst_addr = RCAR_BL335DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl335dst_addrh")))bl335dst_addrh = RCAR_BL335DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl335dst_size"))) bl335dst_size = RCAR_BL335DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl336dst_addr"))) bl336dst_addr = RCAR_BL336DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl336dst_addrh")))bl336dst_addrh = RCAR_BL336DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl336dst_size"))) bl336dst_size = RCAR_BL336DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl337dst_addr"))) bl337dst_addr = RCAR_BL337DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl337dst_addrh")))bl337dst_addrh = RCAR_BL337DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl337dst_size"))) bl337dst_size = RCAR_BL337DST_SIZE;
const uint32_t __attribute__ ((section (".sa6_bl338dst_addr"))) bl338dst_addr = RCAR_BL338DST_ADDRESS;
const uint32_t __attribute__ ((section (".sa6_bl338dst_addrh")))bl338dst_addrh = RCAR_BL338DST_ADDRESSH;
const uint32_t __attribute__ ((section (".sa6_bl338dst_size"))) bl338dst_size = RCAR_BL338DST_SIZE;
tools/renesas/rcar_layout_create/sa6.ld.S 0 → 100644
View file @ 7e532c4b
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