stm32mp1: dynamically map DDR later and non-cacheable during its test

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

drivers/st/ddr/stm32mp1_ram.c

 /*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -250,8 +250,9 @@ static int stm32mp1_ddr_setup(void)
 	VERBOSE("%s : ram size(%x, %x)\n", __func__,
 		(uint32_t)priv->info.base, (uint32_t)priv->info.size);
 
-	write_sctlr(read_sctlr() & ~SCTLR_C_BIT);
-	dcsw_op_all(DC_OP_CISW);
+	if (stm32mp_map_ddr_non_cacheable() != 0) {
+		panic();
+	}
 
 	uret = ddr_test_data_bus();
 	if (uret != 0U) {
@@ -274,7 +275,9 @@ static int stm32mp1_ddr_setup(void)
 		panic();
 	}
 
-	write_sctlr(read_sctlr() | SCTLR_C_BIT);
+	if (stm32mp_unmap_ddr() != 0) {
+		panic();
+	}
 
 	return 0;
 }

plat/st/common/include/stm32mp_common.h

 /*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -87,4 +87,8 @@ void stm32mp_io_setup(void);
  */
 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
 
+/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
+int stm32mp_map_ddr_non_cacheable(void);
+int stm32mp_unmap_ddr(void);
+
 #endif /* STM32MP_COMMON_H */

plat/st/common/stm32mp_common.c

 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +12,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
 uintptr_t plat_get_ns_image_entrypoint(void)
@@ -151,3 +152,16 @@ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
 
 	return 0;
 }
+
+int stm32mp_map_ddr_non_cacheable(void)
+{
+	return  mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+					STM32MP_DDR_MAX_SIZE,
+					MT_NON_CACHEABLE | MT_RW | MT_NS);
+}
+
+int stm32mp_unmap_ddr(void)
+{
+	return  mmap_remove_dynamic_region(STM32MP_DDR_BASE,
+					   STM32MP_DDR_MAX_SIZE);
+}

plat/st/stm32mp1/bl2_plat_setup.c

 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -130,6 +130,7 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
 void bl2_platform_setup(void)
 {
 	int ret;
+	uint32_t ddr_ns_size;
 
 	if (dt_pmic_status() > 0) {
 		initialize_pmic();
@@ -141,8 +142,24 @@ void bl2_platform_setup(void)
 		panic();
 	}
 
+	ddr_ns_size = stm32mp_get_ddr_ns_size();
+	assert(ddr_ns_size > 0U);
+
+	/* Map non secure DDR for BL33 load, now with cacheable attribute */
+	ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+				      ddr_ns_size, MT_MEMORY | MT_RW | MT_NS);
+	assert(ret == 0);
+
 #ifdef AARCH32_SP_OPTEE
 	INFO("BL2 runs OP-TEE setup\n");
+
+	/* Map secure DDR for OP-TEE paged area */
+	ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size,
+				      STM32MP_DDR_BASE + ddr_ns_size,
+				      STM32MP_DDR_S_SIZE,
+				      MT_MEMORY | MT_RW | MT_SECURE);
+	assert(ret == 0);
+
 	/* Initialize tzc400 after DDR initialization */
 	stm32mp1_security_setup();
 #else
@@ -166,14 +183,6 @@ void bl2_el3_plat_arch_setup(void)
 			MT_CODE | MT_SECURE);
 
 #ifdef AARCH32_SP_OPTEE
-	/* OP-TEE image needs post load processing: keep RAM read/write */
-	mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
-			STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
-			STM32MP_DDR_BASE + dt_get_ddr_size() -
-			STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
-			STM32MP_DDR_S_SIZE,
-			MT_MEMORY | MT_RW | MT_SECURE);
-
 	mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
 			STM32MP_OPTEE_SIZE,
 			MT_MEMORY | MT_RW | MT_SECURE);
@@ -182,14 +191,7 @@ void bl2_el3_plat_arch_setup(void)
 	mmap_add_region(BL32_BASE, BL32_BASE,
 			BL32_LIMIT - BL32_BASE,
 			MT_MEMORY | MT_RO | MT_SECURE);
-
 #endif
-	/* Map non secure DDR for BL33 load and DDR training area restore */
-	mmap_add_region(STM32MP_DDR_BASE,
-			STM32MP_DDR_BASE,
-			STM32MP_DDR_MAX_SIZE,
-			MT_MEMORY | MT_RW | MT_NS);
-
 	/* Prevent corruption of preloaded Device Tree */
 	mmap_add_region(DTB_BASE, DTB_BASE,
 			DTB_LIMIT - DTB_BASE,

plat/st/stm32mp1/plat_image_load.c

 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <platform_def.h>
+
 #include <common/desc_image_load.h>
 #include <plat/common/platform.h>
 
@@ -21,6 +23,13 @@ void plat_flush_next_bl_params(void)
  ******************************************************************************/
 bl_load_info_t *plat_get_bl_image_load_info(void)
 {
+	bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
+	uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
+
+	/* Max size is non-secure DDR end address minus image_base */
+	bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
+					  bl33->image_info.image_base;
+
 	return get_bl_load_info_from_mem_params_desc();
 }
 

plat/st/stm32mp1/platform.mk

@@ -11,6 +11,11 @@ USE_COHERENT_MEM	:=	0
 
 STM32_TF_VERSION	?=	0
 
+# Enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC :=	1
+$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC))
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
 # Not needed for Cortex-A7
 WORKAROUND_CVE_2017_5715:=	0
 
@@ -152,8 +157,6 @@ STM32_TF_ELF_LDFLAGS	:=	--hash-style=gnu --as-needed
 STM32_TF_STM32		:=	$(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
 STM32_TF_LINKERFILE	:=	${BUILD_PLAT}/stm32mp1.ld
 
-BL2_CFLAGS	+=	-DPLAT_XLAT_TABLES_DYNAMIC=1
-
 # Variables for use with stm32image
 STM32IMAGEPATH		?= tools/stm32image
 STM32IMAGE		?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}