Move GIC setup to a separate file

GIC setup code which used to be in bl31_plat_setup.c is now in fvp_gic.c
to simplify future changes to other bootloader stages.  This patch moves
code from bl31_plat_setup.c to fvp_gic.c, simplifies the include file
list for bl31_plat_setup.c, moves GIC declarations from the bl31.h header
file into the platform.h, and reworks files according to coding style
guide.

Change-Id: I48d82a4ba33e7114dcc88f9ca98767a06cf8f417

bl31/bl31.mk

@@ -43,7 +43,7 @@ BL31_ASM_OBJS		:=	bl31_entrypoint.o runtime_exceptions.o psci_entry.o		\
 BL31_C_OBJS		:=	bl31_main.o bl31_plat_setup.o bl31_arch_setup.o	\
 				exception_handlers.o bakery_lock.o cci400.o 	\
 				fvp_common.o fvp_pm.o fvp_pwrc.o fvp_topology.o	\
-				runtime_svc.o gic_v2.o psci_setup.o		\
+				runtime_svc.o fvp_gic.o gic_v2.o psci_setup.o	\
 				psci_common.o psci_afflvl_on.o psci_main.o	\
 				psci_afflvl_off.o psci_afflvl_suspend.o
 

include/bl31.h

@@ -44,8 +44,4 @@ extern unsigned long bl31_entrypoint;
 extern void bl31_platform_setup(void);
 extern meminfo *bl31_plat_sec_mem_layout(void);
 extern el_change_info* bl31_get_next_image_info(void);
-extern void gic_cpuif_deactivate(unsigned int);
-extern void gic_cpuif_setup(unsigned int);
-extern void gic_pcpu_distif_setup(unsigned int);
-extern void gic_setup(void);
 #endif /* __BL31_H__ */

plat/fvp/aarch64/fvp_common.c

@@ -589,6 +589,7 @@ int platform_config_setup(void)
 	return 0;
 }
 
-unsigned long plat_get_ns_image_entrypoint(void) {
+unsigned long plat_get_ns_image_entrypoint(void)
+{
 	return NS_IMAGE_OFFSET;
 }

plat/fvp/bl1_plat_setup.c

@@ -139,8 +139,8 @@ void bl1_plat_arch_setup(void)
 	}
 
 	configure_mmu(&bl1_tzram_layout,
-	              TZROM_BASE,
-	              TZROM_BASE + TZROM_SIZE,
-	              BL1_COHERENT_RAM_BASE,
-	              BL1_COHERENT_RAM_LIMIT);
+			TZROM_BASE,
+			TZROM_BASE + TZROM_SIZE,
+			BL1_COHERENT_RAM_BASE,
+			BL1_COHERENT_RAM_LIMIT);
 }

plat/fvp/bl31_plat_setup.c

@@ -28,16 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <string.h>
-#include <assert.h>
-#include <arch_helpers.h>
 #include <platform.h>
-#include <bl31.h>
-#include <bl_common.h>
-#include <pl011.h>
-#include <bakery_lock.h>
-#include <cci400.h>
-#include <gic.h>
 #include <fvp_pwrc.h>
 
 /*******************************************************************************
@@ -137,8 +128,8 @@ void bl31_platform_setup()
 {
 	unsigned int reg_val;
 
-        /* Initialize the gic cpu and distributor interfaces */
-        gic_setup();
+	/* Initialize the gic cpu and distributor interfaces */
+	gic_setup();
 
 	/*
 	 * TODO: Configure the CLCD before handing control to
@@ -162,7 +153,7 @@ void bl31_platform_setup()
 	/* Intialize the power controller */
 	fvp_pwrc_setup();
 
-        /* Topologies are best known to the platform. */
+	/* Topologies are best known to the platform. */
 	plat_setup_topology();
 }
 
@@ -178,245 +169,3 @@ void bl31_plat_arch_setup()
 		      BL31_COHERENT_RAM_BASE,
 		      BL31_COHERENT_RAM_LIMIT);
 }
-
-/*******************************************************************************
- * TODO: Move GIC setup to a separate file in case it is needed by other BL
- * stages or ELs
- * TODO: Revisit if priorities are being set such that no non-secure interrupt
- * can have a higher priority than a secure one as recommended in the GICv2 spec
- *******************************************************************************/
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration. The Firmware itself does
- * not fully support GICv3 at this time and relies on GICv2 emulation as
- * provided by GICv3. This function allows software (like Linux) in later stages
- * to use full GICv3 features.
- *******************************************************************************/
-void gicv3_cpuif_setup(void)
-{
-	unsigned int scr_val, val, base;
-
-	/*
-	 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
-	 * bit set. In order to allow interrupts to get routed to the CPU we
-	 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
-	 * to clear (GICv3 Architecture specification 5.4.23).
-	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
-	 * per CPU.
-	 *
-	 * TODO:
-	 * For GICv4 we also need to adjust the Base address based on
-	 * GICR_TYPER.VLPIS
-	 */
-	base = BASE_GICR_BASE +
-		(platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT);
-	val = gicr_read_waker(base);
-
-	val &= ~WAKER_PS;
-	gicr_write_waker(base, val);
-	dsb();
-
-	/* We need to wait for ChildrenAsleep to clear. */
-	val = gicr_read_waker(base);
-	while (val & WAKER_CA) {
-		val = gicr_read_waker(base);
-	}
-
-	/*
-	 * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
-	 * Restore SCR_EL3.NS again before exit.
-	 */
-	scr_val = read_scr();
-	write_scr(scr_val | SCR_NS_BIT);
-
-	/*
-	 * By default EL2 and NS-EL1 software should be able to enable GICv3
-	 * System register access without any configuration at EL3. But it turns
-	 * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
-	 * we need to set it here again. In order to do that we need to enable
-	 * register access. We leave it enabled as it should be fine and might
-	 * prevent problems with later software trying to access GIC System
-	 * Registers.
-	 */
-	val = read_icc_sre_el3();
-	write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
-
-	val = read_icc_sre_el2();
-	write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
-
-	write_icc_pmr_el1(MAX_PRI_VAL);
-
-	/* Restore SCR_EL3 */
-	write_scr(scr_val);
-}
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration when cores go
- * down.
- *******************************************************************************/
-void gicv3_cpuif_deactivate(void)
-{
-	unsigned int val, base;
-
-	/*
-	 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
-	 * wait for GICR_WAKER.ChildrenAsleep to get set.
-	 * (GICv3 Architecture specification 5.4.23).
-	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
-	 * per CPU.
-	 *
-	 * TODO:
-	 * For GICv4 we also need to adjust the Base address based on
-	 * GICR_TYPER.VLPIS
-	 */
-	base = BASE_GICR_BASE +
-		(platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT);
-	val = gicr_read_waker(base);
-	val |= WAKER_PS;
-	gicr_write_waker(base, val);
-	dsb();
-
-	/* We need to wait for ChildrenAsleep to set. */
-	val = gicr_read_waker(base);
-	while ((val & WAKER_CA) == 0) {
-		val = gicr_read_waker(base);
-	}
-}
-
-
-/*******************************************************************************
- * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
- * and set the priority mask register to allow all interrupts to trickle in.
- ******************************************************************************/
-void gic_cpuif_setup(unsigned int gicc_base)
-{
-	unsigned int val;
-
-	val = gicc_read_iidr(gicc_base);
-
-	/*
-	 * If GICv3 we need to do a bit of additional setup. We want to
-	 * allow default GICv2 behaviour but allow the next stage to
-	 * enable full gicv3 features.
-	 */
-	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
-		gicv3_cpuif_setup();
-	}
-
-	val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
-	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-
-	gicc_write_pmr(gicc_base, MAX_PRI_VAL);
-	gicc_write_ctlr(gicc_base, val);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void gic_cpuif_deactivate(unsigned int gicc_base)
-{
-	unsigned int val;
-
-	/* Disable secure, non-secure interrupts and disable their bypass */
-	val = gicc_read_ctlr(gicc_base);
-	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
-	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(gicc_base, val);
-
-	val = gicc_read_iidr(gicc_base);
-
-	/*
-	 * If GICv3 we need to do a bit of additional setup. Make sure the
-	 * RDIST is put to sleep.
-	 */
-	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
-		gicv3_cpuif_deactivate();
-	}
-}
-
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-void gic_pcpu_distif_setup(unsigned int gicd_base)
-{
-	gicd_write_igroupr(gicd_base, 0, ~0);
-
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
-	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
-
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, MAX_PRI_VAL);
-	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, MAX_PRI_VAL);
-
-	gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
-	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
- * then enables the secure GIC distributor interface.
- ******************************************************************************/
-void gic_distif_setup(unsigned int gicd_base)
-{
-	unsigned int ctr, num_ints, ctlr;
-
-	/* Disable the distributor before going further */
-	ctlr = gicd_read_ctlr(gicd_base);
-	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	gicd_write_ctlr(gicd_base, ctlr);
-
-	/*
-	 * Mark out non-secure interrupts. Calculate number of
-	 * IGROUPR registers to consider. Will be equal to the
-	 * number of IT_LINES
-	 */
-	num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
-	num_ints++;
-	for (ctr = 0; ctr < num_ints; ctr++)
-		gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
-
-	/* Configure secure interrupts now */
-	gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
-	gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, MAX_PRI_VAL);
-	gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
-			   platform_get_core_pos(read_mpidr()));
-	gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
-	gic_pcpu_distif_setup(gicd_base);
-
-	gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
-}
-
-void gic_setup(void)
-{
-	unsigned int gicd_base, gicc_base;
-
-	gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
-	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
-
-	gic_cpuif_setup(gicc_base);
-	gic_distif_setup(gicd_base);
-}

plat/fvp/fvp_gic.c

+/*
+ * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch_helpers.h>
+#include <platform.h>
+#include <gic.h>
+
+
+/*******************************************************************************
+ * TODO: Revisit if priorities are being set such that no non-secure interrupt
+ * can have a higher priority than a secure one as recommended in the GICv2 spec
+ ******************************************************************************/
+
+/*******************************************************************************
+ * This function does some minimal GICv3 configuration. The Firmware itself does
+ * not fully support GICv3 at this time and relies on GICv2 emulation as
+ * provided by GICv3. This function allows software (like Linux) in later stages
+ * to use full GICv3 features.
+ ******************************************************************************/
+void gicv3_cpuif_setup(void)
+{
+	unsigned int scr_val, val, base;
+
+	/*
+	 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
+	 * bit set. In order to allow interrupts to get routed to the CPU we
+	 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
+	 * to clear (GICv3 Architecture specification 5.4.23).
+	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
+	 * per CPU.
+	 *
+	 * TODO:
+	 * For GICv4 we also need to adjust the Base address based on
+	 * GICR_TYPER.VLPIS
+	 */
+	base = BASE_GICR_BASE +
+		(platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT);
+	val = gicr_read_waker(base);
+
+	val &= ~WAKER_PS;
+	gicr_write_waker(base, val);
+	dsb();
+
+	/* We need to wait for ChildrenAsleep to clear. */
+	val = gicr_read_waker(base);
+	while (val & WAKER_CA) {
+		val = gicr_read_waker(base);
+	}
+
+	/*
+	 * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
+	 * Restore SCR_EL3.NS again before exit.
+	 */
+	scr_val = read_scr();
+	write_scr(scr_val | SCR_NS_BIT);
+
+	/*
+	 * By default EL2 and NS-EL1 software should be able to enable GICv3
+	 * System register access without any configuration at EL3. But it turns
+	 * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
+	 * we need to set it here again. In order to do that we need to enable
+	 * register access. We leave it enabled as it should be fine and might
+	 * prevent problems with later software trying to access GIC System
+	 * Registers.
+	 */
+	val = read_icc_sre_el3();
+	write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
+
+	val = read_icc_sre_el2();
+	write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
+
+	write_icc_pmr_el1(MAX_PRI_VAL);
+
+	/* Restore SCR_EL3 */
+	write_scr(scr_val);
+}
+
+/*******************************************************************************
+ * This function does some minimal GICv3 configuration when cores go
+ * down.
+ ******************************************************************************/
+void gicv3_cpuif_deactivate(void)
+{
+	unsigned int val, base;
+
+	/*
+	 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
+	 * wait for GICR_WAKER.ChildrenAsleep to get set.
+	 * (GICv3 Architecture specification 5.4.23).
+	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
+	 * per CPU.
+	 *
+	 * TODO:
+	 * For GICv4 we also need to adjust the Base address based on
+	 * GICR_TYPER.VLPIS
+	 */
+	base = BASE_GICR_BASE +
+		(platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT);
+	val = gicr_read_waker(base);
+	val |= WAKER_PS;
+	gicr_write_waker(base, val);
+	dsb();
+
+	/* We need to wait for ChildrenAsleep to set. */
+	val = gicr_read_waker(base);
+	while ((val & WAKER_CA) == 0) {
+		val = gicr_read_waker(base);
+	}
+}
+
+
+/*******************************************************************************
+ * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
+ * and set the priority mask register to allow all interrupts to trickle in.
+ ******************************************************************************/
+void gic_cpuif_setup(unsigned int gicc_base)
+{
+	unsigned int val;
+
+	val = gicc_read_iidr(gicc_base);
+
+	/*
+	 * If GICv3 we need to do a bit of additional setup. We want to
+	 * allow default GICv2 behaviour but allow the next stage to
+	 * enable full gicv3 features.
+	 */
+	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
+		gicv3_cpuif_setup();
+	}
+
+	val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
+	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
+
+	gicc_write_pmr(gicc_base, MAX_PRI_VAL);
+	gicc_write_ctlr(gicc_base, val);
+}
+
+/*******************************************************************************
+ * Place the cpu interface in a state where it can never make a cpu exit wfi as
+ * as result of an asserted interrupt. This is critical for powering down a cpu
+ ******************************************************************************/
+void gic_cpuif_deactivate(unsigned int gicc_base)
+{
+	unsigned int val;
+
+	/* Disable secure, non-secure interrupts and disable their bypass */
+	val = gicc_read_ctlr(gicc_base);
+	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
+	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
+	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
+	gicc_write_ctlr(gicc_base, val);
+
+	val = gicc_read_iidr(gicc_base);
+
+	/*
+	 * If GICv3 we need to do a bit of additional setup. Make sure the
+	 * RDIST is put to sleep.
+	 */
+	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
+		gicv3_cpuif_deactivate();
+	}
+}
+
+/*******************************************************************************
+ * Per cpu gic distributor setup which will be done by all cpus after a cold
+ * boot/hotplug. This marks out the secure interrupts & enables them.
+ ******************************************************************************/
+void gic_pcpu_distif_setup(unsigned int gicd_base)
+{
+	gicd_write_igroupr(gicd_base, 0, ~0);
+
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
+	gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
+
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, MAX_PRI_VAL);
+	gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, MAX_PRI_VAL);
+
+	gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
+	gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
+}
+
+/*******************************************************************************
+ * Global gic distributor setup which will be done by the primary cpu after a
+ * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
+ * then enables the secure GIC distributor interface.
+ ******************************************************************************/
+void gic_distif_setup(unsigned int gicd_base)
+{
+	unsigned int ctr, num_ints, ctlr;
+
+	/* Disable the distributor before going further */
+	ctlr = gicd_read_ctlr(gicd_base);
+	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
+	gicd_write_ctlr(gicd_base, ctlr);
+
+	/*
+	 * Mark out non-secure interrupts. Calculate number of
+	 * IGROUPR registers to consider. Will be equal to the
+	 * number of IT_LINES
+	 */
+	num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
+	num_ints++;
+	for (ctr = 0; ctr < num_ints; ctr++)
+		gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
+
+	/* Configure secure interrupts now */
+	gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
+	gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, MAX_PRI_VAL);
+	gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
+			   platform_get_core_pos(read_mpidr()));
+	gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
+	gic_pcpu_distif_setup(gicd_base);
+
+	gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
+}
+
+void gic_setup(void)
+{
+	unsigned int gicd_base, gicc_base;
+
+	gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
+	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+
+	gic_cpuif_setup(gicc_base);
+	gic_distif_setup(gicd_base);
+}

plat/fvp/platform.h

@@ -57,8 +57,8 @@
 #define PLATFORM_CLUSTER_COUNT		2ull
 #define PLATFORM_CLUSTER0_CORE_COUNT	4
 #define PLATFORM_CLUSTER1_CORE_COUNT	4
-#define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER1_CORE_COUNT + \
-			       		 PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
+						PLATFORM_CLUSTER0_CORE_COUNT)
 #define PLATFORM_MAX_CPUS_PER_CLUSTER	4
 #define PRIMARY_CPU			0x0
 
@@ -333,6 +333,12 @@ extern void plat_report_exception(unsigned long);
 extern unsigned long plat_get_ns_image_entrypoint(void);
 extern unsigned long platform_get_stack(unsigned long mpidr);
 
+/* Declarations for fvp_gic.c */
+extern void gic_cpuif_deactivate(unsigned int);
+extern void gic_cpuif_setup(unsigned int);
+extern void gic_pcpu_distif_setup(unsigned int);
+extern void gic_setup(void);
+
 /* Declarations for fvp_topology.c */
 extern int plat_setup_topology(void);
 extern int plat_get_max_afflvl(void);