Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes: plat: xilinx: versal: Add support of register notifier plat: xilinx: versal: Add support to get clock rate value plat: xilinx: versal: Add support of set max latency for the device plat: versal: Add InitFinalize API call xilinx: versal: Updated Response of QueryData API call plat:xilinx:versal: Use defaults when PDI is without sw partitions plat: xilinx: Mask unnecessary bytes of return error code xilinx: versal: Skip store/restore of GIC during CPU idle plat: versal: Update API list in feature check xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
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