Commit 86d0a52b authored by Samuel Payne's avatar Samuel Payne Committed by Varun Wadekar
Browse files

Tegra210: se: disable SMMU before suspending SE block



This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.

Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d
Signed-off-by: default avatarSamuel Payne <spayne@nvidia.com>
parent 61beb3e0
...@@ -153,6 +153,10 @@ ...@@ -153,6 +153,10 @@
#define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/* SMMU configuration registers*/
#define MC_SMMU_PPCS_ASID_0 0x270UL
#define PPCS_SMMU_ENABLE (0x1U << 31)
/******************************************************************************* /*******************************************************************************
* Tegra SE constants * Tegra SE constants
******************************************************************************/ ******************************************************************************/
......
...@@ -401,6 +401,14 @@ void tegra_se_init(void) ...@@ -401,6 +401,14 @@ void tegra_se_init(void)
int32_t tegra_se_suspend(void) int32_t tegra_se_suspend(void)
{ {
int32_t ret = 0; int32_t ret = 0;
uint32_t val = 0;
/* SE does not use SMMU in EL3, disable SMMU.
* This will be re-enabled by kernel on resume */
val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0);
val &= ~PPCS_SMMU_ENABLE;
mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val);
/* Atomic context save se2 and pka1 */ /* Atomic context save se2 and pka1 */
INFO("%s: SE2/PKA1 atomic context save\n", __func__); INFO("%s: SE2/PKA1 atomic context save\n", __func__);
......
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