Commit 8bac3689 authored by Mark Dykes's avatar Mark Dykes Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "add-versal-soc-support" into integration

* changes:
  zynqmp: pm: clock: Move custom flags to typeflags
  zynqmp: pm: clock: Add support for custom type flags
  plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
  zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list
parents 62ee1425 74cf2158
......@@ -30,6 +30,10 @@
#define CLK_TYPE_SHIFT U(2)
#define CLK_CLKFLAGS_SHIFT U(8)
#define CLK_TYPEFLAGS_SHIFT U(24)
#define CLK_TYPEFLAGS2_SHIFT U(4)
#define CLK_TYPEFLAGS_BITS_MASK U(0xFF)
#define CLK_TYPEFLAGS2_BITS_MASK U(0x0F00)
#define CLK_TYPEFLAGS_BITS U(8)
#define CLK_EXTERNAL_PARENT (PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN)
......@@ -364,9 +368,8 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = {
.offset = PERIPH_MUX_SHIFT,
.width = PERIPH_MUX_WIDTH,
.clkflags = CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT |
CLK_FRAC | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
CLK_SET_RATE_PARENT | CLK_IS_BASIC,
.typeflags = CLK_FRAC,
.mult = NA_MULT,
.div = NA_DIV,
},
......@@ -375,8 +378,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = {
.offset = PERIPH_DIV1_SHIFT,
.width = PERIPH_DIV1_WIDTH,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
CLK_FRAC | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_FRAC,
.mult = NA_MULT,
.div = NA_DIV,
},
......@@ -385,8 +389,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = {
.offset = PERIPH_DIV2_SHIFT,
.width = PERIPH_DIV2_WIDTH,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
CLK_FRAC | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_FRAC,
.mult = NA_MULT,
.div = NA_DIV,
},
......@@ -2352,7 +2357,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB,
CLK_DBG_TSTMP,
CLK_DDR_REF,
CLK_TOPSW_MAIN,
CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF,
CLK_LPD_SWITCH,
CLK_CPU_R5,
......@@ -2462,6 +2466,7 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
struct pm_clock_node *clock_nodes;
uint8_t num_nodes;
unsigned int i;
uint16_t typeflags;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
......@@ -2481,11 +2486,14 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
for (i = 0; i < 3U; i++) {
if ((index + i) == num_nodes)
break;
topology[i] = clock_nodes[index + i].type;
topology[i] = clock_nodes[index + i].type;
topology[i] |= clock_nodes[index + i].clkflags <<
CLK_CLKFLAGS_SHIFT;
topology[i] |= clock_nodes[index + i].typeflags <<
typeflags = clock_nodes[index + i].typeflags;
topology[i] |= (typeflags & CLK_TYPEFLAGS_BITS_MASK) <<
CLK_TYPEFLAGS_SHIFT;
topology[i] |= (typeflags & CLK_TYPEFLAGS2_BITS_MASK) >>
(CLK_TYPEFLAGS_BITS - CLK_TYPEFLAGS2_SHIFT);
}
return PM_RET_SUCCESS;
......
......@@ -43,7 +43,6 @@
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE BIT(12)
#define CLK_FRAC BIT(13)
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
......@@ -52,6 +51,7 @@
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
#define CLK_FRAC BIT(8)
#define END_OF_CLK "END_OF_CLK"
......
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -629,6 +629,22 @@ enum pm_ret_status pm_aes_engine(uint32_t address_high,
return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
/**
* pm_get_callbackdata() - Read from IPI response buffer
* @data - array of PAYLOAD_ARG_CNT elements
*
* Read value from ipi buffer response buffer.
*/
void pm_get_callbackdata(uint32_t *data, size_t count)
{
/* Return if interrupt is not from PMU */
if (!pm_ipi_irq_status(primary_proc))
return;
pm_ipi_buff_read_callb(data, count);
pm_ipi_irq_clear(primary_proc);
}
/**
* pm_pinctrl_request() - Request Pin from firmware
* @pin Pin number to request
......
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -116,6 +116,7 @@ enum pm_ret_status pm_secure_rsaaes(uint32_t address_high,
uint32_t size,
uint32_t flags);
unsigned int pm_get_shutdown_scope(void);
void pm_get_callbackdata(uint32_t *data, size_t count);
enum pm_ret_status pm_pinctrl_request(unsigned int pin);
enum pm_ret_status pm_pinctrl_release(unsigned int pin);
enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
......
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -25,6 +25,7 @@
#include "pm_client.h"
#include "pm_ipi.h"
#define PM_GET_CALLBACK_DATA 0xa01
#define PM_SET_SUSPEND_MODE 0xa02
#define PM_GET_TRUSTZONE_VERSION 0xa03
......@@ -412,6 +413,16 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_CALLBACK_DATA:
{
uint32_t result[4] = {0};
pm_get_callbackdata(result, (sizeof(result)/sizeof(uint32_t)));
SMC_RET2(handle,
(uint64_t)result[0] | ((uint64_t)result[1] << 32),
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
}
case PM_PINCTRL_REQUEST:
ret = pm_pinctrl_request(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
......
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