Commit 8ccf4954 authored by Lionel Debieve's avatar Lionel Debieve Committed by Yann Gautier
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stm32mp1: add support for new SoC profiles



Update to support new part numbers.

Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F,
STM32MP151D, STM32MP153D, STM32MP157D

The STM32MP1 series is available in 3 different lines which are pin-to-pin
compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
              3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
              and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz

Each line comes with a security option (cryptography & secure boot)
& a Cortex-A frequency option :

- A      Basic + Cortex-A7 @ 650 MHz
- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D      Basic + Cortex-A7 @ 800 MHz
- F      Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz

Remove useless variable in stm32mp_is_single_core().

Change-Id: Id30c836af986c6340c91efa8a7ae9480a2827089
Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
parent ffb3f277
...@@ -37,6 +37,12 @@ ...@@ -37,6 +37,12 @@
#define STM32MP153A_PART_NB U(0x05000025) #define STM32MP153A_PART_NB U(0x05000025)
#define STM32MP151C_PART_NB U(0x0500002E) #define STM32MP151C_PART_NB U(0x0500002E)
#define STM32MP151A_PART_NB U(0x0500002F) #define STM32MP151A_PART_NB U(0x0500002F)
#define STM32MP157F_PART_NB U(0x05000080)
#define STM32MP157D_PART_NB U(0x05000081)
#define STM32MP153F_PART_NB U(0x050000A4)
#define STM32MP153D_PART_NB U(0x050000A5)
#define STM32MP151F_PART_NB U(0x050000AE)
#define STM32MP151D_PART_NB U(0x050000AF)
#define STM32MP1_REV_B U(0x2000) #define STM32MP1_REV_B U(0x2000)
#define STM32MP1_REV_Z U(0x2001) #define STM32MP1_REV_Z U(0x2001)
......
...@@ -220,6 +220,24 @@ void stm32mp_print_cpuinfo(void) ...@@ -220,6 +220,24 @@ void stm32mp_print_cpuinfo(void)
case STM32MP151A_PART_NB: case STM32MP151A_PART_NB:
cpu_s = "151A"; cpu_s = "151A";
break; break;
case STM32MP157F_PART_NB:
cpu_s = "157F";
break;
case STM32MP157D_PART_NB:
cpu_s = "157D";
break;
case STM32MP153F_PART_NB:
cpu_s = "153F";
break;
case STM32MP153D_PART_NB:
cpu_s = "153D";
break;
case STM32MP151F_PART_NB:
cpu_s = "151F";
break;
case STM32MP151D_PART_NB:
cpu_s = "151D";
break;
default: default:
cpu_s = "????"; cpu_s = "????";
break; break;
...@@ -323,7 +341,6 @@ void stm32mp_print_boardinfo(void) ...@@ -323,7 +341,6 @@ void stm32mp_print_boardinfo(void)
bool stm32mp_is_single_core(void) bool stm32mp_is_single_core(void)
{ {
uint32_t part_number; uint32_t part_number;
bool ret = false;
if (get_part_number(&part_number) < 0) { if (get_part_number(&part_number) < 0) {
ERROR("Invalid part number, assume single core chip"); ERROR("Invalid part number, assume single core chip");
...@@ -333,14 +350,13 @@ bool stm32mp_is_single_core(void) ...@@ -333,14 +350,13 @@ bool stm32mp_is_single_core(void)
switch (part_number) { switch (part_number) {
case STM32MP151A_PART_NB: case STM32MP151A_PART_NB:
case STM32MP151C_PART_NB: case STM32MP151C_PART_NB:
ret = true; case STM32MP151D_PART_NB:
break; case STM32MP151F_PART_NB:
return true;
default: default:
break; return false;
} }
return ret;
} }
/* Return true when device is in closed state */ /* Return true when device is in closed state */
......
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