uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox

The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS
is disabled.

The warm boot mailbox is useless for UniPhier SoC family because BL1
is not the first image.  The UniPhier platform implements non-TF ROM,
then BL1 works as a pseudo ROM, so it is never executed in the warm
boot.

The reset vector address is not actually programmable for UniPhier
platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS
to disable the mailbox and remove pointless plat_get_my_entrypoint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

plat/socionext/uniphier/platform.mk

 #
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-override COLD_BOOT_SINGLE_CPU	:= 1
-override ENABLE_PLAT_COMPAT	:= 0
-override LOAD_IMAGE_V2		:= 1
-override USE_COHERENT_MEM	:= 1
-override USE_TBBR_DEFS		:= 1
-override ENABLE_SVE_FOR_NS	:= 0
+override COLD_BOOT_SINGLE_CPU		:= 1
+override ENABLE_PLAT_COMPAT		:= 0
+override LOAD_IMAGE_V2			:= 1
+override PROGRAMMABLE_RESET_ADDRESS	:= 1
+override USE_COHERENT_MEM		:= 1
+override USE_TBBR_DEFS			:= 1
+override ENABLE_SVE_FOR_NS		:= 0
 
 # Cortex-A53 revision r0p4-51rel0
 # needed for LD20, unneeded for LD11, PXs3 (no ACE)
@@ -48,7 +49,6 @@ PLAT_BL_COMMON_SOURCES	+=	drivers/console/aarch64/console.S	\
 
 BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a72.S		\
-				$(PLAT_PATH)/uniphier_bl1_helpers.S	\
 				$(PLAT_PATH)/uniphier_bl1_setup.c	\
 				$(IO_SOURCES)
 

plat/socionext/uniphier/uniphier_bl1_helpers.S

-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-
-	.globl	plat_get_my_entrypoint
-
-func plat_get_my_entrypoint
-	mov	x0, #0
-	ret
-endfunc plat_get_my_entrypoint