Merge changes from topic "tegra-downstream-03192020" into integration

* changes:
  Tegra194: move cluster and CPU counter to header file.
  Tegra: gicv2: initialize target masks
  spd: tlkd: support new TLK SMCs for RPMB service
  Tegra210: trigger CPU0 hotplug power on using FC
  Tegra: memctrl: cleanup streamid override registers
  Tegra: memctrl_v2: remove support to secure TZSRAM
  Tegra: include platform headers from individual makefiles
  Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
  Tegra194: SiP function ID to read SMMU_PER registers
  Tegra: memctrl: map video memory as uncached
  Tegra: remove support for USE_COHERENT_MEM
  Tegra: remove circular dependency with common_def.h
  Tegra: include missing stdbool.h
  Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

include/bl32/payloads/tlk.h

@@ -24,6 +24,9 @@
 #define TLK_SS_REGISTER_HANDLER	TLK_TOS_YIELD_FID(0x3)
 #define TLK_REGISTER_NS_DRAM_RANGES	TLK_TOS_YIELD_FID(0x4)
 #define TLK_SET_ROOT_OF_TRUST	TLK_TOS_YIELD_FID(0x5)
+#define TLK_SET_BL_VERSION	TLK_TOS_YIELD_FID(0x6)
+#define TLK_LOCK_BL_INTERFACE	TLK_TOS_YIELD_FID(0x7)
+#define TLK_BL_RPMB_SERVICE	TLK_TOS_YIELD_FID(0x8)
 #define TLK_RESUME_FID		TLK_TOS_YIELD_FID(0x100)
 #define TLK_SYSTEM_SUSPEND	TLK_TOS_YIELD_FID(0xE001)
 #define TLK_SYSTEM_RESUME	TLK_TOS_YIELD_FID(0xE002)

plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c

@@ -8,6 +8,7 @@
 #include <assert.h>
 #include <common/debug.h>
 #include <errno.h>
+#include <stdbool.h>
 #include <stddef.h>
 #include <string.h>
 

plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -117,7 +117,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
 	ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
 				non_overlap_area_start, /* VA */
 				non_overlap_area_size, /* size */
-				MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+				MT_NS | MT_RW | MT_EXECUTE_NEVER |
+				MT_NON_CACHEABLE); /* attrs */
 	assert(ret == 0);
 
 	zeromem((void *)non_overlap_area_start, non_overlap_area_size);

plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c

@@ -159,69 +159,7 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
  */
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
-	uint32_t index;
-	uint32_t total_128kb_blocks = size_in_bytes >> 17;
-	uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
-	uint32_t val;
-
-	INFO("Configuring TrustZone SRAM Memory Carveout\n");
-
-	/*
-	 * Reset the access configuration registers to restrict access
-	 * to the TZRAM aperture
-	 */
-	for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
-	     index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
-	     index += 4U) {
-		tegra_mc_write_32(index, 0);
-	}
-
-	/*
-	 * Enable CPU access configuration registers to access the TZRAM aperture
-	 */
-	if (!tegra_chipid_is_t186()) {
-		val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
-		val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
-		tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
-	}
-
-	/*
-	 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
-	 */
-	assert((phys_base & (uint64_t)0xFFF) == 0U);
-	tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
-	tegra_mc_write_32(MC_TZRAM_BASE_HI,
-		(uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
-
-	/*
-	 * Set the TZRAM size
-	 *
-	 * total size = (number of 128KB blocks) + (number of remaining 4KB
-	 * blocks)
-	 *
-	 */
-	val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
-	      total_128kb_blocks;
-	tegra_mc_write_32(MC_TZRAM_SIZE, val);
-
-	/*
-	 * Lock the configuration settings by disabling TZ-only lock
-	 * and locking the configuration against any future changes
-	 * at all.
-	 */
-	val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
-	val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
-	val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
-	if (!tegra_chipid_is_t186()) {
-		val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
-	}
-	tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
-
-	/*
-	 * MCE propagates the security configuration values across the
-	 * CCPLEX.
-	 */
-	mce_update_gsc_tzram();
+	; /* do nothing */
 }
 
 /*
@@ -348,7 +286,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
 	ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
 				non_overlap_area_start, /* VA */
 				non_overlap_area_size, /* size */
-				MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+				MT_NS | MT_RW | MT_EXECUTE_NEVER |
+				MT_NON_CACHEABLE); /* attrs */
 	assert(ret == 0);
 
 	zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);

plat/nvidia/tegra/common/tegra_bl31_setup.c

@@ -39,15 +39,8 @@
  * Declarations of linker defined symbols which will help us find the layout
  * of trusted SRAM
  ******************************************************************************/
-
 IMPORT_SYM(uint64_t, __RW_START__,	BL31_RW_START);
 
-static const uint64_t BL31_RW_END	= BL_END;
-static const uint64_t BL31_RODATA_BASE	= BL_RO_DATA_BASE;
-static const uint64_t BL31_RODATA_END	= BL_RO_DATA_END;
-static const uint64_t TEXT_START	= BL_CODE_BASE;
-static const uint64_t TEXT_END		= BL_CODE_END;
-
 extern uint64_t tegra_bl31_phys_base;
 
 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
@@ -314,15 +307,12 @@ void bl31_plat_runtime_setup(void)
 void bl31_plat_arch_setup(void)
 {
 	uint64_t rw_start = BL31_RW_START;
-	uint64_t rw_size = BL31_RW_END - BL31_RW_START;
-	uint64_t rodata_start = BL31_RODATA_BASE;
-	uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
-	uint64_t code_base = TEXT_START;
-	uint64_t code_size = TEXT_END - TEXT_START;
+	uint64_t rw_size = BL_END - BL31_RW_START;
+	uint64_t rodata_start = BL_RO_DATA_BASE;
+	uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
+	uint64_t code_base = BL_CODE_BASE;
+	uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
 	const mmap_region_t *plat_mmio_map = NULL;
-#if USE_COHERENT_MEM
-	uint32_t coh_start, coh_size;
-#endif
 	const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
 
 	/*
@@ -349,15 +339,6 @@ void bl31_plat_arch_setup(void)
 			code_size,
 			MT_CODE | MT_SECURE);
 
-#if USE_COHERENT_MEM
-	coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
-	coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
-
-	mmap_add_region(coh_start, coh_start,
-			coh_size,
-			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
-#endif
-
 	/* map TZDRAM used by BL31 as coherent memory */
 	if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
 		mmap_add_region(params_from_bl2->tzdram_base,

plat/nvidia/tegra/common/tegra_common.mk

@@ -6,8 +6,7 @@
 
 PLAT_INCLUDES		:=	-Iplat/nvidia/tegra/include/drivers \
 				-Iplat/nvidia/tegra/include/lib \
-				-Iplat/nvidia/tegra/include \
-				-Iplat/nvidia/tegra/include/${TARGET_SOC}
+				-Iplat/nvidia/tegra/include
 
 include lib/xlat_tables_v2/xlat_tables.mk
 PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}

plat/nvidia/tegra/common/tegra_gicv2.c

 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-
 #include <platform_def.h>
 
 #include <common/bl_common.h>
 #include <drivers/arm/gicv2.h>
 #include <lib/utils.h>
+#include <plat/common/platform.h>
 
 #include <tegra_private.h>
 #include <tegra_def.h>
 
+static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT];
+
 /******************************************************************************
  * Tegra common helper to setup the GICv2 driver data.
  *****************************************************************************/
@@ -33,6 +36,8 @@ void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
 	tegra_gic_data.gicc_base = TEGRA_GICC_BASE;
 	tegra_gic_data.interrupt_props = interrupt_props;
 	tegra_gic_data.interrupt_props_num = interrupt_props_num;
+	tegra_gic_data.target_masks = tegra_target_masks;
+	tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks);
 	gicv2_driver_init(&tegra_gic_data);
 }
 
@@ -43,6 +48,7 @@ void tegra_gic_init(void)
 {
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
+	gicv2_set_pe_target_mask(plat_my_core_pos());
 	gicv2_cpuif_enable();
 }
 
@@ -61,5 +67,6 @@ void tegra_gic_cpuif_deactivate(void)
 void tegra_gic_pcpu_init(void)
 {
 	gicv2_pcpu_distif_init();
+	gicv2_set_pe_target_mask(plat_my_core_pos());
 	gicv2_cpuif_enable();
 }

plat/nvidia/tegra/include/drivers/flowctrl.h

 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +10,8 @@
 
 #include <lib/mmio.h>
 
+#include <stdbool.h>
+
 #include <tegra_def.h>
 
 #define FLOWCTRL_HALT_CPU0_EVENTS	(0x0U)

plat/nvidia/tegra/include/drivers/mce.h

 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -69,7 +69,6 @@ int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 int mce_update_reset_vector(void);
 int mce_update_gsc_videomem(void);
 int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
 __dead2 void mce_enter_ccplex_state(uint32_t state_idx);
 void mce_update_cstate_info(const mce_cstate_info_t *cstate);
 void mce_verify_firmware_version(void);

plat/nvidia/tegra/include/platform_def.h

 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +13,19 @@
 
 #include <tegra_def.h>
 
+/*******************************************************************************
+ * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
+ ******************************************************************************/
+#if !SEPARATE_CODE_AND_RODATA
+#error "SEPARATE_CODE_AND_RODATA should be set to 1"
+#endif
+
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
 /*
  * Platform binary types for linking
  */
@@ -33,7 +47,7 @@
 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
 					 PLATFORM_MAX_CPUS_PER_CLUSTER)
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
-					 PLATFORM_CLUSTER_COUNT + 1)
+					 PLATFORM_CLUSTER_COUNT + U(1))
 
 /*******************************************************************************
  * Platform console related constants
@@ -72,4 +86,5 @@
 #define MAX_IO_DEVICES			U(0)
 #define MAX_IO_HANDLES			U(0)
 
+
 #endif /* PLATFORM_DEF_H */

plat/nvidia/tegra/include/t194/tegra_def.h

@@ -9,6 +9,12 @@
 
 #include <lib/utils_def.h>
 
+/*******************************************************************************
+ * Chip specific cluster and cpu numbers
+ ******************************************************************************/
+#define PLATFORM_CLUSTER_COUNT		U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(2)
+
 /*******************************************************************************
  * Chip specific page table and MMU setup constants
  ******************************************************************************/

plat/nvidia/tegra/platform.mk

@@ -40,7 +40,7 @@ OVERRIDE_LIBC		:=	1
 
 # Flag to enable WDT FIQ interrupt handling for Tegra SoCs
 # prior to Tegra186
-ENABLE_WDT_LEGACY_FIQ_HANDLING	?= 0
+ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING	?= 0
 
 # Flag to allow relocation of BL32 image to TZDRAM during boot
 RELOCATE_BL32_IMAGE		?= 0
@@ -48,7 +48,7 @@ RELOCATE_BL32_IMAGE		?= 0
 include plat/nvidia/tegra/common/tegra_common.mk
 include ${SOC_DIR}/platform_${TARGET_SOC}.mk
 
-$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING))
 $(eval $(call add_define,RELOCATE_BL32_IMAGE))
 
 # modify BUILD_PLAT to point to SoC specific build directory

plat/nvidia/tegra/soc/t132/platform_t132.mk

@@ -20,6 +20,9 @@ $(eval $(call add_define,MAX_XLAT_TABLES))
 MAX_MMAP_REGIONS		:= 8
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
+# platform files
+PLAT_INCLUDES		+=	-Iplat/nvidia/tegra/include/t132
+
 BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S		\
 				lib/cpus/aarch64/denver.S		\
 				${COMMON_DIR}/drivers/flowctrl/flowctrl.c	\

plat/nvidia/tegra/soc/t186/drivers/mce/mce.c

 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -385,14 +386,6 @@ int32_t mce_update_gsc_tzdram(void)
 	return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX);
 }
 
-/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
-	return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM);
-}
-
 /*******************************************************************************
  * Handler to shutdown/reset the entire system
  ******************************************************************************/

plat/nvidia/tegra/soc/t186/plat_memctrl.c

@@ -21,29 +21,6 @@ extern uint64_t tegra_bl31_phys_base;
  * Array to hold stream_id override config register offsets
  ******************************************************************************/
 const static uint32_t tegra186_streamid_override_regs[] = {
-	MC_STREAMID_OVERRIDE_CFG_PTCR,
-	MC_STREAMID_OVERRIDE_CFG_AFIR,
-	MC_STREAMID_OVERRIDE_CFG_HDAR,
-	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
-	MC_STREAMID_OVERRIDE_CFG_SATAR,
-	MC_STREAMID_OVERRIDE_CFG_MPCORER,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
-	MC_STREAMID_OVERRIDE_CFG_AFIW,
-	MC_STREAMID_OVERRIDE_CFG_HDAW,
-	MC_STREAMID_OVERRIDE_CFG_MPCOREW,
-	MC_STREAMID_OVERRIDE_CFG_SATAW,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWB,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
-	MC_STREAMID_OVERRIDE_CFG_GPUSRD,
-	MC_STREAMID_OVERRIDE_CFG_GPUSWR,
 	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
 	MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
 	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
@@ -52,47 +29,6 @@ const static uint32_t tegra186_streamid_override_regs[] = {
 	MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
 	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
 	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD,
-	MC_STREAMID_OVERRIDE_CFG_VICSWR,
-	MC_STREAMID_OVERRIDE_CFG_VIW,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
-	MC_STREAMID_OVERRIDE_CFG_APER,
-	MC_STREAMID_OVERRIDE_CFG_APEW,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
-	MC_STREAMID_OVERRIDE_CFG_SESRD,
-	MC_STREAMID_OVERRIDE_CFG_SESWR,
-	MC_STREAMID_OVERRIDE_CFG_ETRR,
-	MC_STREAMID_OVERRIDE_CFG_ETRW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
-	MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
-	MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
-	MC_STREAMID_OVERRIDE_CFG_AXISR,
-	MC_STREAMID_OVERRIDE_CFG_AXISW,
-	MC_STREAMID_OVERRIDE_CFG_EQOSR,
-	MC_STREAMID_OVERRIDE_CFG_EQOSW,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPW,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
-	MC_STREAMID_OVERRIDE_CFG_AONR,
-	MC_STREAMID_OVERRIDE_CFG_AONW,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
-	MC_STREAMID_OVERRIDE_CFG_SCER,
-	MC_STREAMID_OVERRIDE_CFG_SCEW,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
 };
 
 /*******************************************************************************

plat/nvidia/tegra/soc/t186/platform_t186.mk

@@ -37,7 +37,8 @@ MAX_MMAP_REGIONS			:= 27
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files
-PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/include
+PLAT_INCLUDES		+=	-Iplat/nvidia/tegra/include/t186 \
+				-I${SOC_DIR}/drivers/include
 
 BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S	\
 				lib/cpus/aarch64/denver.S		\

plat/nvidia/tegra/soc/t194/drivers/mce/mce.c

@@ -115,25 +115,6 @@ int32_t mce_update_gsc_tzdram(void)
 	return ret;
 }
 
-/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
-	int32_t ret;
-
-	/*
-	 * MCE firmware is not running on simulation platforms.
-	 */
-	if (mce_firmware_not_supported()) {
-		ret = -EINVAL;
-	} else {
-		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
-	}
-
-	return ret;
-}
-
 /*******************************************************************************
  * Handler to issue the UPDATE_CSTATE_INFO request
  ******************************************************************************/

plat/nvidia/tegra/soc/t194/plat_memctrl.c

@@ -11,150 +11,6 @@
 #include <tegra_mc_def.h>
 #include <tegra_platform.h>
 
-/*******************************************************************************
- * Array to hold stream_id override config register offsets
- ******************************************************************************/
-const static uint32_t tegra194_streamid_override_regs[] = {
-	MC_STREAMID_OVERRIDE_CFG_PTCR,
-	MC_STREAMID_OVERRIDE_CFG_HDAR,
-	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
-	MC_STREAMID_OVERRIDE_CFG_SATAR,
-	MC_STREAMID_OVERRIDE_CFG_MPCORER,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
-	MC_STREAMID_OVERRIDE_CFG_HDAW,
-	MC_STREAMID_OVERRIDE_CFG_MPCOREW,
-	MC_STREAMID_OVERRIDE_CFG_SATAW,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA,
-	MC_STREAMID_OVERRIDE_CFG_ISPFALR,
-	MC_STREAMID_OVERRIDE_CFG_ISPWA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWB,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD,
-	MC_STREAMID_OVERRIDE_CFG_VICSWR,
-	MC_STREAMID_OVERRIDE_CFG_VIW,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
-	MC_STREAMID_OVERRIDE_CFG_APER,
-	MC_STREAMID_OVERRIDE_CFG_APEW,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
-	MC_STREAMID_OVERRIDE_CFG_SESRD,
-	MC_STREAMID_OVERRIDE_CFG_SESWR,
-	MC_STREAMID_OVERRIDE_CFG_AXIAPR,
-	MC_STREAMID_OVERRIDE_CFG_AXIAPW,
-	MC_STREAMID_OVERRIDE_CFG_ETRR,
-	MC_STREAMID_OVERRIDE_CFG_ETRW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
-	MC_STREAMID_OVERRIDE_CFG_AXISR,
-	MC_STREAMID_OVERRIDE_CFG_AXISW,
-	MC_STREAMID_OVERRIDE_CFG_EQOSR,
-	MC_STREAMID_OVERRIDE_CFG_EQOSW,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPW,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
-	MC_STREAMID_OVERRIDE_CFG_AONR,
-	MC_STREAMID_OVERRIDE_CFG_AONW,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
-	MC_STREAMID_OVERRIDE_CFG_SCER,
-	MC_STREAMID_OVERRIDE_CFG_SCEW,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
-	MC_STREAMID_OVERRIDE_CFG_VIFALR,
-	MC_STREAMID_OVERRIDE_CFG_VIFALW,
-	MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
-	MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
-	MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
-	MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
-	MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
-	MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
-	MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
-	MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
-	MC_STREAMID_OVERRIDE_CFG_RCER,
-	MC_STREAMID_OVERRIDE_CFG_RCEW,
-	MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
-	MC_STREAMID_OVERRIDE_CFG_PCIE0R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE0W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE1R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE1W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
-	MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
-	MC_STREAMID_OVERRIDE_CFG_PCIE3R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE3W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE4R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE4W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5W,
-	MC_STREAMID_OVERRIDE_CFG_ISPFALW,
-	MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
-	MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA1,
-	MC_STREAMID_OVERRIDE_CFG_PCIE0R1,
-	MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD,
-	MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR,
-	MC_STREAMID_OVERRIDE_CFG_MIU0R,
-	MC_STREAMID_OVERRIDE_CFG_MIU0W,
-	MC_STREAMID_OVERRIDE_CFG_MIU1R,
-	MC_STREAMID_OVERRIDE_CFG_MIU1W,
-	MC_STREAMID_OVERRIDE_CFG_MIU2R,
-	MC_STREAMID_OVERRIDE_CFG_MIU2W,
-	MC_STREAMID_OVERRIDE_CFG_MIU3R,
-	MC_STREAMID_OVERRIDE_CFG_MIU3W,
-	MC_STREAMID_OVERRIDE_CFG_MIU4R,
-	MC_STREAMID_OVERRIDE_CFG_MIU4W,
-	MC_STREAMID_OVERRIDE_CFG_MIU5R,
-	MC_STREAMID_OVERRIDE_CFG_MIU5W,
-	MC_STREAMID_OVERRIDE_CFG_MIU6R,
-	MC_STREAMID_OVERRIDE_CFG_MIU6W,
-	MC_STREAMID_OVERRIDE_CFG_MIU7R,
-	MC_STREAMID_OVERRIDE_CFG_MIU7W
-};
-
 /*******************************************************************************
  * Array to hold the security configs for stream IDs
  ******************************************************************************/
@@ -571,8 +427,6 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
  * Struct to hold the memory controller settings
  ******************************************************************************/
 static tegra_mc_settings_t tegra194_mc_settings = {
-	.streamid_override_cfg = tegra194_streamid_override_regs,
-	.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
 	.streamid_security_cfg = tegra194_streamid_sec_cfgs,
 	.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
 	.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx

plat/nvidia/tegra/soc/t194/plat_sip_calls.c

@@ -16,11 +16,13 @@
 #include <common/runtime_svc.h>
 #include <tegra_private.h>
 #include <tegra_platform.h>
+#include <smmu.h>
 #include <stdbool.h>
 
 /*******************************************************************************
  * Tegra194 SiP SMCs
  ******************************************************************************/
+#define TEGRA_SIP_GET_SMMU_PER		0xC200FF00U
 
 /*******************************************************************************
  * This function is responsible for handling all T194 SiP calls
@@ -34,13 +36,43 @@ int32_t plat_sip_handler(uint32_t smc_fid,
 		     void *handle,
 		     uint64_t flags)
 {
-	int32_t ret = -ENOTSUP;
+	int32_t ret = 0;
+	uint32_t i, smmu_per[6] = {0};
+	uint32_t num_smmu_devices = plat_get_num_smmu_devices();
+	uint64_t per[3] = {0ULL};
 
-	(void)smc_fid;
 	(void)x1;
 	(void)x4;
 	(void)cookie;
 	(void)flags;
 
+	switch (smc_fid) {
+	case TEGRA_SIP_GET_SMMU_PER:
+
+		/* make sure we dont go past the array length */
+		assert(num_smmu_devices <= ARRAY_SIZE(smmu_per));
+
+		/* read all supported SMMU_PER records */
+		for (i = 0U; i < num_smmu_devices; i++) {
+			smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER);
+		}
+
+		/* pack results into 3 64bit variables. */
+		per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U);
+		per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U);
+		per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U);
+
+		/* provide the results via X1-X3 CPU registers */
+		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]);
+		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]);
+		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]);
+
+		break;
+
+	default:
+		ret = -ENOTSUP;
+		break;
+	}
+
 	return ret;
 }

plat/nvidia/tegra/soc/t194/platform_t194.mk

@@ -24,12 +24,6 @@ COLD_BOOT_SINGLE_CPU			:= 1
 TZDRAM_BASE				:= 0x40000000
 $(eval $(call add_define,TZDRAM_BASE))
 
-PLATFORM_CLUSTER_COUNT			:= 4
-$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-
-PLATFORM_MAX_CPUS_PER_CLUSTER		:= 2
-$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-
 MAX_XLAT_TABLES				:= 25
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
@@ -37,7 +31,8 @@ MAX_MMAP_REGIONS			:= 30
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files
-PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/include
+PLAT_INCLUDES		+=	-Iplat/nvidia/tegra/include/t194 \
+				-I${SOC_DIR}/drivers/include
 
 BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S \
 				lib/cpus/aarch64/denver.S		\