Merge changes from topic "tegra-downstream-01202020" into integration

* changes:
  Tegra194: mce: remove unused NVG functions
  Tegra194: support for NVG interface v6.6
  Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list
  Tegra194: enable driver for general purpose DMA engine
  Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
  Tegra194: organize the memory/mmio map to make it linear
  Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
  Tegra194: support for boot params wider than 32-bits
  Tegra194: memctrl: set reorder depth limit for PCIE blocks
  Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
  Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
  Tegra194: memctrl: update mss reprogramming as HW PROD settings
  Tegra194: memctrl: Disable PVARDC coalescer
  Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
  Tegra194: Request CG7 from last core in cluster
  Tegra194: toggle SE clock during context save/restore
  Tegra: bpmp: fix header file paths

plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c

 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
 #include <bpmp_ipc.h>
-#include <debug.h>
+#include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <errno.h>
 #include <lib/mmio.h>

plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c

 /*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch_helpers.h>
 #include <assert.h>
-#include <debug.h>
+#include <common/debug.h>
 #include <errno.h>
 #include <stddef.h>
 #include <string.h>

plat/nvidia/tegra/include/t194/tegra_def.h

@@ -53,6 +53,11 @@
 #define  BOARD_SHIFT_BITS		U(24)
 #define MISCREG_PFCFG			U(0x200C)
 
+/*******************************************************************************
+ * Tegra General Purpose Centralised DMA constants
+ ******************************************************************************/
+#define TEGRA_GPCDMA_BASE		U(0x02610000)
+
 /*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/
@@ -126,6 +131,18 @@
 #define TEGRA_UARTF_BASE		U(0x03150000)
 #define TEGRA_UARTG_BASE		U(0x0C290000)
 
+/*******************************************************************************
+ * XUSB PADCTL
+ ******************************************************************************/
+#define TEGRA_XUSB_PADCTL_BASE			U(0x03520000)
+#define TEGRA_XUSB_PADCTL_SIZE			U(0x10000)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0	U(0x136c)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0	U(0x1370)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1	U(0x1374)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2	U(0x1378)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3	U(0x137c)
+#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0	U(0x139c)
+
 /*******************************************************************************
  * Tegra Fuse Controller related constants
  ******************************************************************************/
@@ -151,6 +168,14 @@
 #define TEGRA_RNG1_BASE			U(0x03AE0000)
 #define  RNG1_MUTEX_WATCHDOG_NS_LIMIT	U(0xFE0)
 
+/*******************************************************************************
+ * Tegra HSP doorbell #0 constants
+ ******************************************************************************/
+#define TEGRA_HSP_DBELL_BASE		U(0x03C90000)
+#define  HSP_DBELL_1_ENABLE		U(0x104)
+#define  HSP_DBELL_3_TRIGGER		U(0x300)
+#define  HSP_DBELL_3_ENABLE		U(0x304)
+
 /*******************************************************************************
  * Tegra hardware synchronization primitives for the SPE engine
  ******************************************************************************/
@@ -172,6 +197,7 @@
  * Tegra scratch registers constants
  ******************************************************************************/
 #define TEGRA_SCRATCH_BASE		U(0x0C390000)
+#define  SECURE_SCRATCH_RSV75   	U(0x2BC)
 #define  SECURE_SCRATCH_RSV81_LO	U(0x2EC)
 #define  SECURE_SCRATCH_RSV81_HI	U(0x2F0)
 #define  SECURE_SCRATCH_RSV97		U(0x36C)
@@ -180,8 +206,14 @@
 #define  SECURE_SCRATCH_RSV109_LO	U(0x3CC)
 #define  SECURE_SCRATCH_RSV109_HI	U(0x3D0)
 
-#define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV81_LO
-#define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV81_HI
+#define SCRATCH_BL31_PARAMS_HI_ADDR	SECURE_SCRATCH_RSV75
+#define  SCRATCH_BL31_PARAMS_HI_ADDR_MASK  U(0xFFFF)
+#define  SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0)
+#define SCRATCH_BL31_PARAMS_LO_ADDR	SECURE_SCRATCH_RSV81_LO
+#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75
+#define  SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK  U(0xFFFF0000)
+#define  SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16)
+#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI
 #define SCRATCH_SECURE_BOOTP_FCFG	SECURE_SCRATCH_RSV97
 #define SCRATCH_SMMU_TABLE_ADDR_LO	SECURE_SCRATCH_RSV99_LO
 #define SCRATCH_SMMU_TABLE_ADDR_HI	SECURE_SCRATCH_RSV99_HI
@@ -206,6 +238,13 @@
 #define TEGRA_TZRAM_BASE		U(0x40000000)
 #define TEGRA_TZRAM_SIZE		U(0x40000)
 
+/*******************************************************************************
+ * Tegra CCPLEX-BPMP IPC constants
+ ******************************************************************************/
+#define TEGRA_BPMP_IPC_TX_PHYS_BASE	U(0x4004C000)
+#define TEGRA_BPMP_IPC_RX_PHYS_BASE	U(0x4004D000)
+#define TEGRA_BPMP_IPC_CH_MAP_SIZE	U(0x1000) /* 4KB */
+
 /*******************************************************************************
  * Tegra Clock and Reset Controller constants
  ******************************************************************************/
@@ -214,18 +253,8 @@
 #define TEGRA_GPU_RESET_GPU_SET_OFFSET  U(0x1C)
 #define  GPU_RESET_BIT			(U(1) << 0)
 #define  GPU_SET_BIT			(U(1) << 0)
-
-/*******************************************************************************
- * XUSB PADCTL
- ******************************************************************************/
-#define TEGRA_XUSB_PADCTL_BASE			U(0x3520000)
-#define TEGRA_XUSB_PADCTL_SIZE			U(0x10000)
-#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0	U(0x136c)
-#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0	U(0x1370)
-#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1	U(0x1374)
-#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2	U(0x1378)
-#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3	U(0x137c)
-#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0	U(0x139c)
+#define TEGRA_GPCDMA_RST_SET_REG_OFFSET	U(0x6A0004)
+#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET	U(0x6A0008)
 
 /*******************************************************************************
  * XUSB STREAMIDs

plat/nvidia/tegra/include/t194/tegra_mc_def.h

@@ -18,14 +18,14 @@
 #define MC_CLIENT_ORDER_ID_27				U(0x2a6c)
 #define  MC_CLIENT_ORDER_ID_27_RESET_VAL		0x00000000U
 #define  MC_CLIENT_ORDER_ID_27_PCIE0W_MASK		(0x3U << 4)
-#define  MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID		(1U << 4)
+#define  MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID		(2U << 4)
 
 #define MC_CLIENT_ORDER_ID_28				U(0x2a70)
 #define  MC_CLIENT_ORDER_ID_28_RESET_VAL		0x00000000U
 #define  MC_CLIENT_ORDER_ID_28_PCIE4W_MASK		(0x3U << 4)
 #define  MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID		(3U << 4)
 #define  MC_CLIENT_ORDER_ID_28_PCIE5W_MASK		(0x3U << 12)
-#define  MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID		(2U << 12)
+#define  MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID		(1U << 12)
 
 #define mc_client_order_id(val, id, client) \
 	((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \
@@ -53,6 +53,11 @@
 #define  MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK		(0x3U << 28)
 #define  MC_HUB_PC_VC_ID_4_NIC_VC_ID			(VC_NISO << 28)
 
+#define MC_HUB_PC_VC_ID_12				U(0x2aa8)
+#define  MC_HUB_PC_VC_ID_12_RESET_VAL 			0x11001011U
+#define  MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK		(0x3U << 12)
+#define  MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID		(VC_NISO << 12)
+
 #define mc_hub_vc_id(val, id, client) \
 	((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \
 	MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
@@ -105,7 +110,7 @@
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK		(1U << 7)
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED 	(0U << 13)
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK		(1U << 13)
-#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED 		(1U << 15)
+#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED 	(0U << 15)
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK		(1U << 15)
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED	(0U << 17)
 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK		(1U << 17)
@@ -531,7 +536,10 @@
 #define MC_CLIENT_HOTRESET_STATUS2				0x1898U
 
 #define MC_COALESCE_CTRL					0x2930U
-#define  MC_COALESCE_CTRL_COALESCER_ENABLE			(1U << 31)
+#define MC_COALESCE_CTRL_COALESCER_ENABLE			(1U << 31)
+#define MC_COALESCE_CONFIG_6_0					0x294cU
+#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED	(1U << 8)
+#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED	(1U << 14)
 
 /*******************************************************************************
  * Tegra TSA Controller constants
@@ -649,5 +657,29 @@
 
 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK			(ULL(0x3) << 11)
 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU			(ULL(0) << 11)
+#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK			(ULL(0x3) << 15)
+#define TSA_CONFIG_CSW_SO_DEV_HUB2				(ULL(2) << 15)
+
+#define REORDER_DEPTH_LIMIT					16
+#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK			(ULL(0x7FF) << 21)
+#define reorder_depth_limit(limit)				(ULL(limit) << 21)
+
+#define tsa_read_32(client) \
+		mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client)
+
+#define mc_set_tsa_hub2(val, client) \
+	{ \
+		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
+		((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \
+		TSA_CONFIG_CSW_SO_DEV_HUB2)); \
+	}
+
+#define mc_set_tsa_depth_limit(limit, client) \
+	{ \
+		uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \
+		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
+		((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \
+		reorder_depth_limit(limit))); \
+	}
 
 #endif /* TEGRA_MC_DEF_H */

plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h

@@ -45,10 +45,6 @@
 
 /* declarations for NVG handler functions */
 uint64_t nvg_get_version(void);
-int32_t nvg_enable_power_perf_mode(void);
-int32_t nvg_disable_power_perf_mode(void);
-int32_t nvg_enable_power_saver_modes(void);
-int32_t nvg_disable_power_saver_modes(void);
 void nvg_set_wake_time(uint32_t wake_time);
 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
 		uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
@@ -57,19 +53,20 @@ uint64_t nvg_get_cstate_stat_query_value(void);
 int32_t nvg_is_sc7_allowed(void);
 int32_t nvg_online_core(uint32_t core);
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_clean_cache(void);
-int32_t nvg_roc_flush_cache(void);
 int32_t nvg_roc_clean_cache_trbits(void);
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
+int32_t nvg_roc_clean_cache_trbits(void);
+void nvg_enable_strict_checking_mode(void);
+void nvg_system_shutdown(void);
+void nvg_system_reboot(void);
+
+/* declarations for assembly functions */
 void nvg_set_request_data(uint64_t req, uint64_t data);
 void nvg_set_request(uint64_t req);
 uint64_t nvg_get_result(void);
 uint64_t nvg_cache_clean(void);
 uint64_t nvg_cache_clean_inval(void);
 uint64_t nvg_cache_inval_all(void);
-void nvg_enable_strict_checking_mode(void);
-void nvg_system_shutdown(void);
-void nvg_system_reboot(void);
 
 /* MCE helper functions */
 void mce_enable_strict_checking(void);

plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h

@@ -20,61 +20,65 @@
  */
 enum {
 	TEGRA_NVG_VERSION_MAJOR = 6,
-	TEGRA_NVG_VERSION_MINOR = 4
+	TEGRA_NVG_VERSION_MINOR = 6
 };
 
 typedef enum {
-	TEGRA_NVG_CHANNEL_VERSION			=  0,
-	TEGRA_NVG_CHANNEL_POWER_PERF			=  1,
-	TEGRA_NVG_CHANNEL_POWER_MODES			=  2,
-	TEGRA_NVG_CHANNEL_WAKE_TIME			=  3,
-	TEGRA_NVG_CHANNEL_CSTATE_INFO			=  4,
-	TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND	=  5,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND	=  6,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND	=  8,
-	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST	= 10,
-	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE	= 11,
-	TEGRA_NVG_CHANNEL_SHUTDOWN			= 42,
-	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED		= 43,
-	TEGRA_NVG_CHANNEL_ONLINE_CORE			= 44,
-	TEGRA_NVG_CHANNEL_CC3_CTRL			= 45,
-	TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL		= 49,
-	TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC		= 50,
-	TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL		= 53,
-	TEGRA_NVG_CHANNEL_SECURITY_CONFIG		= 54,
-	TEGRA_NVG_CHANNEL_DEBUG_CONFIG			= 55,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_MCF			= 56,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD1			= 57,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD2			= 58,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD3			= 59,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ISO			= 60,
-	TEGRA_NVG_CHANNEL_DDA_MCF_SISO			= 61,
-	TEGRA_NVG_CHANNEL_DDA_MCF_NISO			= 62,
-	TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE		= 63,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO		= 64,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO		= 65,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO		= 66,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE	= 67,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL		= 68,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR		= 69,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA	= 70,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA	= 71,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL		= 72,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL			= 73,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D		= 74,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD		= 75,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR		= 76,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL		= 77,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL	= 78,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
+	TEGRA_NVG_CHANNEL_VERSION				= 0,
+	TEGRA_NVG_CHANNEL_POWER_PERF				= 1,
+	TEGRA_NVG_CHANNEL_POWER_MODES				= 2,
+	TEGRA_NVG_CHANNEL_WAKE_TIME				= 3,
+	TEGRA_NVG_CHANNEL_CSTATE_INFO				= 4,
+	TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND		= 5,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND		= 6,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND		= 8,
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST		= 10,
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE		= 11,
+	TEGRA_NVG_CHANNEL_NUM_CORES				= 20,
+	TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID			= 21,
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING		= 22,
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR			= 23,
+	TEGRA_NVG_CHANNEL_SHUTDOWN				= 42,
+	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED			= 43,
+	TEGRA_NVG_CHANNEL_ONLINE_CORE				= 44,
+	TEGRA_NVG_CHANNEL_CC3_CTRL				= 45,
+	TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL			= 49,
+	TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC			= 50,
+	TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL			= 53,
+	TEGRA_NVG_CHANNEL_SECURITY_CONFIG			= 54,
+	TEGRA_NVG_CHANNEL_DEBUG_CONFIG				= 55,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_MCF				= 56,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD1				= 57,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD2				= 58,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD3				= 59,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ISO				= 60,
+	TEGRA_NVG_CHANNEL_DDA_MCF_SISO				= 61,
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO				= 62,
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE			= 63,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO			= 64,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO			= 65,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO			= 66,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE		= 67,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL			= 68,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR			= 69,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA		= 70,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA		= 71,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL			= 72,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL				= 73,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D			= 74,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD			= 75,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR			= 76,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL			= 77,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL		= 78,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL	= 79,
 
 	TEGRA_NVG_CHANNEL_LAST_INDEX
 } tegra_nvg_channel_id_t;
 
 typedef enum {
-	NVG_STAT_QUERY_SC7_ENTRIES		=  1,
-	NVG_STAT_QUERY_CC6_ENTRIES		=  6,
-	NVG_STAT_QUERY_CG7_ENTRIES		=  7,
+	NVG_STAT_QUERY_SC7_ENTRIES		= 1,
+	NVG_STAT_QUERY_CC6_ENTRIES		= 6,
+	NVG_STAT_QUERY_CG7_ENTRIES		= 7,
 	NVG_STAT_QUERY_C6_ENTRIES		= 10,
 	NVG_STAT_QUERY_C7_ENTRIES		= 14,
 	NVG_STAT_QUERY_SC7_RESIDENCY_SUM	= 32,
@@ -112,8 +116,14 @@ typedef enum {
 	TEGRA_NVG_CORE_WARMRSTREQ = 8
 } tegra_nvg_core_sleep_state_t;
 
+typedef enum {
+	TEGRA_NVG_SHUTDOWN = 0U,
+	TEGRA_NVG_REBOOT = 1U
+} tegra_nvg_shutdown_reboot_state_t;
+
 typedef enum {
 	TEGRA_NVG_CLUSTER_CC0 = 0,
+	TEGRA_NVG_CLUSTER_AUTO_CC1 = 1,
 	TEGRA_NVG_CLUSTER_CC6 = 6
 } tegra_nvg_cluster_sleep_state_t;
 
@@ -128,11 +138,6 @@ typedef enum {
 	TEGRA_NVG_SYSTEM_SC8 = 8
 } tegra_nvg_system_sleep_state_t;
 
-typedef enum {
-    TEGRA_NVG_SHUTDOWN = 0U,
-    TEGRA_NVG_REBOOT = 1U,
-} tegra_nvg_shutdown_reboot_state_t;
-
 // ---------------------------------------------------------------------------
 // NVG Data subformats
 // ---------------------------------------------------------------------------
@@ -206,18 +211,31 @@ typedef union {
 typedef union {
 	uint64_t flat;
 	struct nvg_cstate_info_channel_t {
-		uint32_t cluster_state	: 3;
-		uint32_t reserved_6_3	: 4;
-		uint32_t update_cluster	: 1;
-		uint32_t cg_cstate	: 3;
-		uint32_t reserved_14_11	: 4;
-		uint32_t update_cg	: 1;
-		uint32_t system_cstate	: 4;
-		uint32_t reserved_22_20	: 3;
-		uint32_t update_system	: 1;
-		uint32_t reserved_30_24	: 7;
-		uint32_t update_wake_mask : 1;
-		uint32_t wake_mask	: 32;
+		uint32_t cluster_state			: 3;
+		uint32_t reserved_6_3			: 4;
+		uint32_t update_cluster			: 1;
+		uint32_t cg_cstate				: 3;
+		uint32_t reserved_14_11			: 4;
+		uint32_t update_cg				: 1;
+		uint32_t system_cstate			: 4;
+		uint32_t reserved_22_20			: 3;
+		uint32_t update_system			: 1;
+		uint32_t reserved_30_24			: 7;
+		uint32_t update_wake_mask		: 1;
+		union {
+			uint32_t flat				: 32;
+			struct {
+				uint32_t vfiq			: 1;
+				uint32_t virq			: 1;
+				uint32_t fiq			: 1;
+				uint32_t irq			: 1;
+				uint32_t serror			: 1;
+				uint32_t reserved_10_5	: 6;
+				uint32_t fiqout			: 1;
+				uint32_t irqout			: 1;
+				uint32_t reserved_31_13	: 19;
+			} carmel;
+		} wake_mask;
 	} bits;
 } nvg_cstate_info_channel_t;
 
@@ -239,6 +257,52 @@ typedef union {
 	} bits;
 } nvg_cstate_stat_query_channel_t;
 
+typedef union {
+	uint64_t flat;
+	struct nvg_num_cores_channel_t {
+		uint32_t num_cores		: 4;
+		uint32_t reserved_31_4	: 28;
+		uint32_t reserved_63_32 : 32;
+	} bits;
+} nvg_num_cores_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_unique_logical_id_channel_t {
+		uint32_t unique_core_id	: 3;
+		uint32_t reserved_31_3	: 29;
+		uint32_t reserved_63_32 : 32;
+	} bits;
+} nvg_unique_logical_id_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_logical_to_physical_mappings_channel_t {
+		uint32_t lcore0_pcore_id	: 4;
+		uint32_t lcore1_pcore_id	: 4;
+		uint32_t lcore2_pcore_id	: 4;
+		uint32_t lcore3_pcore_id	: 4;
+		uint32_t lcore4_pcore_id	: 4;
+		uint32_t lcore5_pcore_id	: 4;
+		uint32_t lcore6_pcore_id	: 4;
+		uint32_t lcore7_pcore_id	: 4;
+		uint32_t reserved_63_32		: 32;
+	} bits;
+} nvg_logical_to_physical_mappings_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_logical_to_mpidr_channel_write_t {
+		uint32_t lcore_id		: 3;
+		uint32_t reserved_31_3	: 29;
+		uint32_t reserved_63_32	: 32;
+	} write;
+	struct nvg_logical_to_mpidr_channel_read_t {
+		uint32_t mpidr			: 32;
+		uint32_t reserved_63_32	: 32;
+	} read;
+} nvg_logical_to_mpidr_channel_t;
+
 typedef union {
 	uint64_t flat;
 	struct nvg_is_sc7_allowed_channel_t {
@@ -260,50 +324,50 @@ typedef union {
 typedef union {
 	uint64_t flat;
 	struct nvg_cc3_control_channel_t {
-		uint32_t freq_req	: 8;
-		uint32_t reserved_30_8	: 23;
+		uint32_t freq_req	: 9;
+		uint32_t reserved_30_9	: 22;
 		uint32_t enable		: 1;
 		uint32_t reserved_63_32	: 32;
 	} bits;
 } nvg_cc3_control_channel_t;
 
 typedef enum {
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL		=  0,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC		=  1,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1		=  2,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2		=  3,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA		=  4,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB		=  5,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP		=  6,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_APE		=  7,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE		=  8,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE		=  9,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_APR		=  10,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM		=  11,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC	=  12,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE	=  13,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE	=  14,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7		=  15,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE	=  16,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE		=  17,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP	=  18,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1		=  19,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP	=  20,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7		=  21,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW	=  23,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST	=  24,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB		=  25,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CV			=  26,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2		=  27,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW	=  28,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES	=  29,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_30			=  30,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_31			=  31,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM		=  32,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK		=  33,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS		=  34,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR		=  35,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL			=	0,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC			=	1,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1			=	2,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2			=	3,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA			=	4,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB			=	5,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP			=	6,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APE			=	7,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE			=	8,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE			=	9,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APR			=	10,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM			=	11,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC		=	12,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE		=	13,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE		=	14,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7			=	15,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE		=	16,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE			=	17,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP		=	18,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1			=	19,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP		=	20,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7			=	21,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP	=	22,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW		=	23,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST		=	24,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB			=	25,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CV				=	26,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2			=	27,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW		=	28,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES		=	29,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_30				=	30,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_31				=	31,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM			=	32,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK			=	33,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS			=	34,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR			=	35,
 	TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
 } tegra_nvg_channel_update_gsc_gsc_enum_t;
 
@@ -335,4 +399,26 @@ typedef union {
 	} bits;
 } nvg_shutdown_t;
 
+typedef union {
+	uint64_t flat;
+	struct nvg_debug_config_channel_t {
+		uint32_t enter_debug_state_on_mca : 1;
+		uint32_t reserved_31_1            : 31;
+		uint32_t reserved_63_32           : 32;
+	} bits;
+} nvg_debug_config_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_hsm_error_ctrl_channel_t {
+		uint32_t uncorr			: 1;
+		uint32_t corr			: 1;
+		uint32_t reserved_31_2	: 30;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_hsm_error_ctrl_channel_t;
+
+extern nvg_debug_config_t nvg_debug_config;
+
 #endif
+

plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c

@@ -30,54 +30,6 @@ uint64_t nvg_get_version(void)
 	return (uint64_t)nvg_get_result();
 }
 
-/*
- * Enable the perf per watt mode.
- *
- * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode
- */
-int32_t nvg_enable_power_perf_mode(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
-
-	return 0;
-}
-
-/*
- * Disable the perf per watt mode.
- *
- * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode
- */
-int32_t nvg_disable_power_perf_mode(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
-
-	return 0;
-}
-
-/*
- * Enable the battery saver mode.
- *
- * NVGDATA[2]: SW(RW), 1 = enable battery saver mode
- */
-int32_t nvg_enable_power_saver_modes(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
-
-	return 0;
-}
-
-/*
- * Disable the battery saver mode.
- *
- * NVGDATA[2]: SW(RW), 0 = disable battery saver mode
- */
-int32_t nvg_disable_power_saver_modes(void)
-{
-	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
-
-	return 0;
-}
-
 /*
  * Set the expected wake time in TSC ticks for the next low-power state the
  * core enters.
@@ -197,48 +149,6 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
 	return ret;
 }
 
-/*
- * Cache clean operation for all CCPLEX caches.
- */
-int32_t nvg_roc_clean_cache(void)
-{
-	int32_t ret = 0;
-
-	/* check if cache flush through mts is supported */
-	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
-			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
-		if (nvg_cache_clean() == 0U) {
-			ERROR("%s: failed\n", __func__);
-			ret = -ENODEV;
-		}
-	} else {
-		ret = -ENOTSUP;
-	}
-
-	return ret;
-}
-
-/*
- * Cache clean and invalidate operation for all CCPLEX caches.
- */
-int32_t nvg_roc_flush_cache(void)
-{
-	int32_t ret = 0;
-
-	/* check if cache flush through mts is supported */
-	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
-			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
-		if (nvg_cache_clean_inval() == 0U) {
-			ERROR("%s: failed\n", __func__);
-			ret = -ENODEV;
-		}
-	} else {
-		ret = -ENOTSUP;
-	}
-
-	return ret;
-}
-
 /*
  * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
  */

plat/nvidia/tegra/soc/t194/drivers/se/se.c

 /*
  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 #include <stdbool.h>
 
 #include <arch_helpers.h>
+#include <bpmp_ipc.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <lib/mmio.h>
@@ -181,6 +182,12 @@ int32_t tegra_se_suspend(void)
 {
 	int32_t ret = 0;
 
+	/* initialise communication channel with BPMP */
+	assert(tegra_bpmp_ipc_init() == 0);
+
+	/* Enable SE clock before SE context save */
+	tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+
 	/* save SE registers */
 	se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
 	se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
@@ -193,6 +200,9 @@ int32_t tegra_se_suspend(void)
 		ERROR("%s: context save failed (%d)\n", __func__, ret);
 	}
 
+	/* Disable SE clock after SE context save */
+	tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+
 	return ret;
 }
 
@@ -201,6 +211,12 @@ int32_t tegra_se_suspend(void)
  */
 void tegra_se_resume(void)
 {
+	/* initialise communication channel with BPMP */
+	assert(tegra_bpmp_ipc_init() == 0);
+
+	/* Enable SE clock before SE context restore */
+	tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+
 	/*
 	 * When TZ takes over after System Resume, TZ should first reconfigure
 	 * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
@@ -211,4 +227,7 @@ void tegra_se_resume(void)
 	mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
 	mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
 	mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
+
+	/* Disable SE clock after SE context restore */
+	tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
 }

plat/nvidia/tegra/soc/t194/plat_psci_handlers.c

@@ -251,6 +251,8 @@ static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *
 
 			/* Enable CC6 state and turn off wake mask */
 			cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6;
+			cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7;
+			cstate_info.system_state_force = 1;
 			cstate_info.update_wake_mask = 1U;
 			mce_update_cstate_info(&cstate_info);
 
@@ -428,18 +430,21 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 		 * in above registers to support both virtualization and
 		 * non-virtualization platforms
 		 */
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
-		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-			XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+		if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+			mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+				XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+		}
 
 		/*
 		 * Reset power state info for the last core doing SC7

plat/nvidia/tegra/soc/t194/plat_setup.c

@@ -64,13 +64,15 @@ const uint8_t *plat_get_power_domain_tree_desc(void)
  * Table of regions to map using the MMU.
  */
 static const mmap_region_t tegra_mmap[] = {
-	MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 #if !ENABLE_CONSOLE_SPE
 	MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
@@ -80,35 +82,37 @@ static const mmap_region_t tegra_mmap[] = {
 	MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 #endif
-	MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
+	MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 #if ENABLE_CONSOLE_SPE
-	MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 #endif
-	MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
+	MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
+	MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */
-			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	{0}
 };
@@ -231,18 +235,21 @@ void plat_early_platform_setup(void)
 	 * above registers to support both virtualization and
 	 * non-virtualization platforms
 	 */
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
-	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
-		XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+	if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+	}
 }
 
 /* Secure IRQs for Tegra194 */
@@ -272,9 +279,12 @@ void plat_gic_setup(void)
  ******************************************************************************/
 struct tegra_bl31_params *plat_get_bl31_params(void)
 {
-	uint32_t val;
+	uint64_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
+	val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
+		SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
+	val <<= 32;
+	val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
 
 	return (struct tegra_bl31_params *)(uintptr_t)val;
 }
@@ -284,9 +294,12 @@ struct tegra_bl31_params *plat_get_bl31_params(void)
  ******************************************************************************/
 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
 {
-	uint32_t val;
+	uint64_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
+	val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
+		SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
+	val <<= 32;
+	val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
 
 	return (plat_params_from_bl2_t *)(uintptr_t)val;
 }

plat/nvidia/tegra/soc/t194/plat_smmu.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -139,6 +139,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	mc_make_sid_security_cfg(NVENCSRD1),
 	mc_make_sid_security_cfg(NVENC1SRD1),
 	mc_make_sid_security_cfg(ISPRA1),
+	mc_make_sid_security_cfg(PCIE0R1),
 	mc_make_sid_security_cfg(MIU0R),
 	mc_make_sid_security_cfg(MIU0W),
 	mc_make_sid_security_cfg(MIU1R),
@@ -262,6 +263,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	mc_make_sid_override_cfg(NVENCSRD1),
 	mc_make_sid_override_cfg(NVENC1SRD1),
 	mc_make_sid_override_cfg(ISPRA1),
+	mc_make_sid_override_cfg(PCIE0R1),
 	mc_make_sid_override_cfg(MIU0R),
 	mc_make_sid_override_cfg(MIU0W),
 	mc_make_sid_override_cfg(MIU1R),

plat/nvidia/tegra/soc/t194/plat_trampoline.S

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 
 #define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
 #define TEGRA194_STATE_SYSTEM_RESUME	0x600D
-#define TEGRA194_SMMU_CTX_SIZE		0x80B
+#define TEGRA194_SMMU_CTX_SIZE		0x80D
 
 	.align 4
 	.globl	tegra194_cpu_reset_handler

plat/nvidia/tegra/soc/t194/platform_t194.mk

@@ -8,9 +8,12 @@
 ENABLE_CONSOLE_SPE			:= 0
 $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
-ENABLE_STRICT_CHECKING_MODE	:= 1
+ENABLE_STRICT_CHECKING_MODE		:= 1
 $(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
 
+USE_GPC_DMA				:= 1
+$(eval $(call add_define,USE_GPC_DMA))
+
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1
@@ -38,6 +41,9 @@ PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/include
 
 BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S \
 				lib/cpus/aarch64/denver.S		\
+				${COMMON_DIR}/drivers/bpmp_ipc/intf.c	\
+				${COMMON_DIR}/drivers/bpmp_ipc/ivc.c	\
+				${COMMON_DIR}/drivers/gpcdma/gpcdma.c	\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c	\
 				${COMMON_DIR}/drivers/smmu/smmu.c	\
 				${SOC_DIR}/drivers/mce/mce.c		\