Commit 91ecca23 authored by Olivier Deprez's avatar Olivier Deprez Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "spm-devel" into integration

* changes:
  spm-mm: Rename aarch64 assembly files
  spm-mm: Rename source files
  spm-mm: Rename spm_shim_private.h
  spm-mm: Rename spm_private.h
  spm-mm: Rename component makefile
  spm-mm: Remove mm_svc.h header
  spm-mm: Refactor spm_svc.h and its contents
  spm-mm: Refactor secure_partition.h and its contents
  spm: Remove SPM Alpha 1 prototype and support files
  Remove dependency between SPM_MM and ENABLE_SPM build flags
parents b8e17967 99c69109
#
# Copyright (c) 2018, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
SPRT_LIB_SOURCES := $(addprefix lib/sprt/, \
sprt_host.c \
sprt_queue.c)
SPRT_LIB_INCLUDES := -Iinclude/lib/sprt/
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include "sprt_queue.h"
void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size)
{
assert(queue_base != NULL);
assert(entry_size > 0U);
assert(entry_num > 0U);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
queue->entry_num = entry_num;
queue->entry_size = entry_size;
queue->idx_write = 0U;
queue->idx_read = 0U;
memset(queue->data, 0, entry_num * entry_size);
}
int sprt_queue_is_empty(void *queue_base)
{
assert(queue_base != NULL);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
return (queue->idx_write == queue->idx_read);
}
int sprt_queue_is_full(void *queue_base)
{
assert(queue_base != NULL);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint32_t idx_next_write = (queue->idx_write + 1) % queue->entry_num;
return (idx_next_write == queue->idx_read);
}
int sprt_queue_push(void *queue_base, const void *entry)
{
assert(entry != NULL);
assert(queue_base != NULL);
if (sprt_queue_is_full(queue_base) != 0) {
return -ENOMEM;
}
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint8_t *dst_entry = &queue->data[queue->entry_size * queue->idx_write];
memcpy(dst_entry, entry, queue->entry_size);
/*
* Make sure that the message data is visible before increasing the
* counter of available messages.
*/
__asm__ volatile("dmb st" ::: "memory");
queue->idx_write = (queue->idx_write + 1) % queue->entry_num;
__asm__ volatile("dmb st" ::: "memory");
return 0;
}
int sprt_queue_pop(void *queue_base, void *entry)
{
assert(entry != NULL);
assert(queue_base != NULL);
if (sprt_queue_is_empty(queue_base) != 0) {
return -ENOENT;
}
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint8_t *src_entry = &queue->data[queue->entry_size * queue->idx_read];
memcpy(entry, src_entry, queue->entry_size);
/*
* Make sure that the message data is visible before increasing the
* counter of read messages.
*/
__asm__ volatile("dmb st" ::: "memory");
queue->idx_read = (queue->idx_read + 1) % queue->entry_num;
__asm__ volatile("dmb st" ::: "memory");
return 0;
}
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPRT_QUEUE_H
#define SPRT_QUEUE_H
#include <stdint.h>
/* Struct that defines a queue. Not to be used directly. */
struct __attribute__((__packed__)) sprt_queue {
uint32_t entry_num; /* Number of entries */
uint32_t entry_size; /* Size of an entry */
uint32_t idx_write; /* Index of first empty entry */
uint32_t idx_read; /* Index of first entry to read */
uint8_t data[0]; /* Start of data */
};
#define SPRT_QUEUE_HEADER_SIZE (sizeof(struct sprt_queue))
/*
* Initializes a memory region to be used as a queue of the given number of
* entries with the specified size.
*/
void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size);
/* Returns 1 if the queue is empty, 0 otherwise */
int sprt_queue_is_empty(void *queue_base);
/* Returns 1 if the queue is full, 0 otherwise */
int sprt_queue_is_full(void *queue_base);
/*
* Pushes a new entry intro the queue. Returns 0 on success, -ENOMEM if the
* queue is full.
*/
int sprt_queue_push(void *queue_base, const void *entry);
/*
* Pops an entry from the queue. Returns 0 on success, -ENOENT if the queue is
* empty.
*/
int sprt_queue_pop(void *queue_base, void *entry);
#endif /* SPRT_QUEUE_H */
......@@ -178,11 +178,8 @@ RECLAIM_INIT_CODE := 0
# SPD choice
SPD := none
# For including the Secure Partition Manager
ENABLE_SPM := 0
# Use the SPM based on MM
SPM_MM := 1
# Enable the Management Mode (MM)-based Secure Partition Manager implementation
SPM_MM := 0
# Flag to introduce an infinite loop in BL1 just before it exits into the next
# image. This is meant to help debugging the post-BL2 phase.
......
......@@ -18,7 +18,7 @@
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <services/secure_partition.h>
#include <services/spm_mm_partition.h>
#include "fvp_private.h"
......@@ -96,12 +96,9 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_BL1_RW,
#endif
#endif /* TRUSTED_BOARD_BOOT */
#if ENABLE_SPM && SPM_MM
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if ENABLE_SPM && !SPM_MM
PLAT_MAP_SP_PACKAGE_MEM_RW,
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
......@@ -127,16 +124,13 @@ const mmap_region_t plat_arm_mmap[] = {
MAP_DEVICE0,
MAP_DEVICE1,
ARM_V2M_MAP_MEM_PROTECT,
#if ENABLE_SPM && SPM_MM
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
#if ENABLE_SPM && !SPM_MM
PLAT_MAP_SP_PACKAGE_MEM_RO,
#endif
{0}
};
#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
#if defined(IMAGE_BL31) && SPM_MM
const mmap_region_t plat_arm_secure_partition_mmap[] = {
V2M_MAP_IOFPGA_EL0, /* for the UART */
MAP_REGION_FLAT(DEVICE0_BASE, \
......@@ -190,12 +184,12 @@ static unsigned int get_interconnect_master(void)
}
#endif
#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
#if defined(IMAGE_BL31) && SPM_MM
/*
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
static secure_partition_mp_info_t sp_mp_info[] = {
static spm_mm_mp_info_t sp_mp_info[] = {
[0] = {0x80000000, 0},
[1] = {0x80000001, 0},
[2] = {0x80000002, 0},
......@@ -206,10 +200,10 @@ static secure_partition_mp_info_t sp_mp_info[] = {
[7] = {0x80000103, 0},
};
const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
.h.size = sizeof(secure_partition_boot_info_t),
.h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = ARM_SP_IMAGE_BASE,
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
......@@ -233,7 +227,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
return plat_arm_secure_partition_mmap;
}
const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
......
......@@ -61,7 +61,7 @@
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL31)
# if ENABLE_SPM
# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 9
# define PLAT_SP_IMAGE_MMAP_REGIONS 30
......@@ -116,11 +116,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
#if ENABLE_SPM && !SPM_MM
#define PLAT_ARM_MAX_BL31_SIZE UL(0x60000)
#else
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
#endif
#ifndef __aarch64__
/*
......
......@@ -281,11 +281,6 @@ else # if AArch64
ifeq (${RESET_TO_BL31},1)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
ifeq (${ENABLE_SPM},1)
ifeq (${SPM_MM},0)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
endif
ifeq (${SPD},trusty)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
......
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -24,7 +24,7 @@ ehf_pri_desc_t arm_exceptions[] = {
/* Normal priority SDEI */
EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
#endif
#if ENABLE_SPM
#if SPM_MM
EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SP_PRI),
#endif
};
......
......@@ -16,7 +16,7 @@
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <services/secure_partition.h>
#include <services/spm_mm_partition.h>
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
......
......@@ -248,16 +248,6 @@ PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
lib/extensions/pauth/pauth_helpers.S
endif
# SPM uses libfdt in Arm platforms
ifeq (${SPM_MM},0)
ifeq (${ENABLE_SPM},1)
BL31_SOURCES += common/fdt_wrappers.c \
plat/common/plat_spm_rd.c \
plat/common/plat_spm_sp.c \
${LIBFDT_SRCS}
endif
endif
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -28,7 +28,7 @@
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL31)
# if ENABLE_SPM
# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 7
# define PLAT_SP_IMAGE_MMAP_REGIONS 7
......@@ -101,7 +101,7 @@
#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE 0x400
#elif defined(IMAGE_BL31)
# if ENABLE_SPM
# if SPM_MM
# define PLATFORM_STACK_SIZE 0x500
# else
# define PLATFORM_STACK_SIZE 0x400
......
#
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
......@@ -10,8 +10,6 @@ CSS_ENT_BASE := plat/arm/css/sgi
RAS_EXTENSION := 0
ENABLE_SPM := 0
SDEI_SUPPORT := 0
EL3_EXCEPTION_HANDLING := 0
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -15,7 +15,7 @@
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
#include <sgi_base_platform_def.h>
#include <services/secure_partition.h>
#include <services/spm_mm_partition.h>
#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
......@@ -46,7 +46,7 @@ const mmap_region_t plat_arm_mmap[] = {
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
#if ENABLE_SPM
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
......@@ -61,13 +61,13 @@ const mmap_region_t plat_arm_mmap[] = {
V2M_MAP_IOFPGA,
CSS_SGI_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
#if ENABLE_SPM
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
{0}
};
#if ENABLE_SPM && defined(IMAGE_BL31)
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
......@@ -77,17 +77,17 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = {
ARM_SPM_BUF_EL0_MMAP,
{0}
};
#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
#endif /* SPM_MM && defined(IMAGE_BL31) */
#endif
ARM_CASSERT_MMAP
#if ENABLE_SPM && defined(IMAGE_BL31)
#if SPM_MM && defined(IMAGE_BL31)
/*
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
static secure_partition_mp_info_t sp_mp_info[] = {
static spm_mm_mp_info_t sp_mp_info[] = {
[0] = {0x81000000, 0},
[1] = {0x81000100, 0},
[2] = {0x81000200, 0},
......@@ -98,10 +98,10 @@ static secure_partition_mp_info_t sp_mp_info[] = {
[7] = {0x81010300, 0},
};
const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
.h.size = sizeof(secure_partition_boot_info_t),
.h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = ARM_SP_IMAGE_BASE,
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
......@@ -125,12 +125,12 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
return plat_arm_secure_partition_mmap;
}
const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
}
#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
#endif /* SPM_MM && defined(IMAGE_BL31) */
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -12,9 +12,8 @@
#include <lib/extensions/ras.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/common/platform.h>
#include <services/mm_svc.h>
#include <services/sdei.h>
#include <services/spm_svc.h>
#include <services/spm_mm_svc.h>
#include <sgi_ras.h>
......@@ -142,11 +141,11 @@ static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
sizeof(ras_map->ras_ev_num));
header->message_len = 4;
spm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
plat_my_core_pos());
spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
plat_my_core_pos());
/*
* Do an EOI of the RAS interuupt. This allows the
* Do an EOI of the RAS interrupt. This allows the
* sdei event to be dispatched at the SDEI event's
* priority.
*/
......
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <libfdt.h>
#include <platform_def.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <lib/object_pool.h>
#include <plat/common/platform.h>
#include <services/sp_res_desc.h>
/*******************************************************************************
* Resource pool
******************************************************************************/
static struct sp_rd_sect_mem_region rd_mem_regions[PLAT_SPM_MEM_REGIONS_MAX];
static OBJECT_POOL_ARRAY(rd_mem_regions_pool, rd_mem_regions);
static struct sp_rd_sect_notification rd_notifs[PLAT_SPM_NOTIFICATIONS_MAX];
static OBJECT_POOL_ARRAY(rd_notifs_pool, rd_notifs);
static struct sp_rd_sect_service rd_services[PLAT_SPM_SERVICES_MAX];
static OBJECT_POOL_ARRAY(rd_services_pool, rd_services);
/*******************************************************************************
* Attribute section handler
******************************************************************************/
static void rd_parse_attribute(struct sp_rd_sect_attribute *attr,
const void *fdt, int node)
{
int rc = 0;
/* The minimum size that can be read from the DTB is 32-bit. */
uint32_t version, sp_type, runtime_el, exec_type;
uint32_t panic_policy, xlat_granule;
rc |= fdtw_read_cells(fdt, node, "version", 1, &version);
if (version != 1) {
ERROR("Unsupported resource description version: 0x%x\n",
version);
panic();
}
rc |= fdtw_read_cells(fdt, node, "sp_type", 1, &sp_type);
rc |= fdtw_read_cells(fdt, node, "pe_mpidr", 1, &attr->pe_mpidr);
rc |= fdtw_read_cells(fdt, node, "runtime_el", 1, &runtime_el);
rc |= fdtw_read_cells(fdt, node, "exec_type", 1, &exec_type);
rc |= fdtw_read_cells(fdt, node, "panic_policy", 1, &panic_policy);
rc |= fdtw_read_cells(fdt, node, "xlat_granule", 1, &xlat_granule);
rc |= fdtw_read_cells(fdt, node, "binary_size", 1, &attr->binary_size);
rc |= fdtw_read_cells(fdt, node, "load_address", 2, &attr->load_address);
rc |= fdtw_read_cells(fdt, node, "entrypoint", 2, &attr->entrypoint);
attr->version = version;
attr->sp_type = sp_type;
attr->runtime_el = runtime_el;
attr->exec_type = exec_type;
attr->panic_policy = panic_policy;
attr->xlat_granule = xlat_granule;
VERBOSE(" Attribute Section:\n");
VERBOSE(" version: 0x%x\n", version);
VERBOSE(" sp_type: 0x%x\n", sp_type);
VERBOSE(" pe_mpidr: 0x%x\n", attr->pe_mpidr);
VERBOSE(" runtime_el: 0x%x\n", runtime_el);
VERBOSE(" exec_type: 0x%x\n", exec_type);
VERBOSE(" panic_policy: 0x%x\n", panic_policy);
VERBOSE(" xlat_granule: 0x%x\n", xlat_granule);
VERBOSE(" binary_size: 0x%x\n", attr->binary_size);
VERBOSE(" load_address: 0x%llx\n", attr->load_address);
VERBOSE(" entrypoint: 0x%llx\n", attr->entrypoint);
if (rc) {
ERROR("Failed to read attribute node elements.\n");
panic();
}
}
/*******************************************************************************
* Memory regions section handlers
******************************************************************************/
static void rd_parse_memory_region(struct sp_rd_sect_mem_region *rdmem,
const void *fdt, int node)
{
int rc = 0;
char name[RD_MEM_REGION_NAME_LEN];
rc |= fdtw_read_string(fdt, node, "str", (char *)&name, sizeof(name));
rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdmem->attr);
rc |= fdtw_read_cells(fdt, node, "base", 2, &rdmem->base);
rc |= fdtw_read_cells(fdt, node, "size", 2, &rdmem->size);
size_t len = strlcpy(rdmem->name, name, RD_MEM_REGION_NAME_LEN);
if (len >= RD_MEM_REGION_NAME_LEN) {
WARN("Memory region name truncated: '%s'\n", name);
}
VERBOSE(" Memory Region:\n");
VERBOSE(" name: '%s'\n", rdmem->name);
VERBOSE(" attr: 0x%x\n", rdmem->attr);
VERBOSE(" base: 0x%llx\n", rdmem->base);
VERBOSE(" size: 0x%llx\n", rdmem->size);
if (rc) {
ERROR("Failed to read mem_region node elements.\n");
panic();
}
}
static void rd_parse_memory_regions(struct sp_res_desc *rd, const void *fdt,
int node)
{
int child;
struct sp_rd_sect_mem_region *rdmem, *old_rdmem;
fdt_for_each_subnode(child, fdt, node) {
rdmem = pool_alloc(&rd_mem_regions_pool);
/* Add element to the start of the list */
old_rdmem = rd->mem_region;
rd->mem_region = rdmem;
rdmem->next = old_rdmem;
rd_parse_memory_region(rdmem, fdt, child);
}
if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node);
panic();
}
}
/*******************************************************************************
* Notifications section handlers
******************************************************************************/
static void rd_parse_notification(struct sp_rd_sect_notification *rdnot,
const void *fdt, int node)
{
int rc = 0;
rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdnot->attr);
rc |= fdtw_read_cells(fdt, node, "pe", 1, &rdnot->pe);
VERBOSE(" Notification:\n");
VERBOSE(" attr: 0x%x\n", rdnot->attr);
VERBOSE(" pe: 0x%x\n", rdnot->pe);
if (rc) {
ERROR("Failed to read notification node elements.\n");
panic();
}
}
static void rd_parse_notifications(struct sp_res_desc *rd, const void *fdt, int node)
{
int child;
struct sp_rd_sect_notification *rdnot, *old_rdnot;
fdt_for_each_subnode(child, fdt, node) {
rdnot = pool_alloc(&rd_notifs_pool);
/* Add element to the start of the list */
old_rdnot = rd->notification;
rd->notification = rdnot;
rdnot->next = old_rdnot;
rd_parse_notification(rdnot, fdt, child);
}
if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, child);
panic();
}
}
/*******************************************************************************
* Services section handlers
******************************************************************************/
static void rd_parse_service(struct sp_rd_sect_service *rdsvc, const void *fdt,
int node)
{
int rc = 0;
/* The minimum size that can be read from the DTB is 32-bit. */
uint32_t accessibility, request_type, connection_quota;
rc |= fdtw_read_array(fdt, node, "uuid", 4, &rdsvc->uuid);
rc |= fdtw_read_cells(fdt, node, "accessibility", 1, &accessibility);
rc |= fdtw_read_cells(fdt, node, "request_type", 1, &request_type);
rc |= fdtw_read_cells(fdt, node, "connection_quota", 1, &connection_quota);
rc |= fdtw_read_cells(fdt, node, "sec_mem_size", 1, &rdsvc->secure_mem_size);
rc |= fdtw_read_cells(fdt, node, "interrupt_num", 1, &rdsvc->interrupt_num);
rdsvc->accessibility = accessibility;
rdsvc->request_type = request_type;
rdsvc->connection_quota = connection_quota;
VERBOSE(" Service:\n");
VERBOSE(" uuid: 0x%08x 0x%08x 0x%08x 0x%08x\n", rdsvc->uuid[0],
rdsvc->uuid[1], rdsvc->uuid[2], rdsvc->uuid[3]);
VERBOSE(" accessibility: 0x%x\n", accessibility);
VERBOSE(" request_type: 0x%x\n", request_type);
VERBOSE(" connection_quota: 0x%x\n", connection_quota);
VERBOSE(" secure_memory_size: 0x%x\n", rdsvc->secure_mem_size);
VERBOSE(" interrupt_num: 0x%x\n", rdsvc->interrupt_num);
if (rc) {
ERROR("Failed to read attribute node elements.\n");
panic();
}
}
static void rd_parse_services(struct sp_res_desc *rd, const void *fdt, int node)
{
int child;
struct sp_rd_sect_service *rdsvc, *old_rdsvc;
fdt_for_each_subnode(child, fdt, node) {
rdsvc = pool_alloc(&rd_services_pool);
/* Add element to the start of the list */
old_rdsvc = rd->service;
rd->service = rdsvc;
rdsvc->next = old_rdsvc;
rd_parse_service(rdsvc, fdt, child);
}
if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node);
panic();
}
}
/*******************************************************************************
* Root node handler
******************************************************************************/
static void rd_parse_root(struct sp_res_desc *rd, const void *fdt, int root)
{
int node;
char *str;
str = "attribute";
node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
if (node < 0) {
ERROR("Root node doesn't contain subnode '%s'\n", str);
panic();
} else {
rd_parse_attribute(&rd->attribute, fdt, node);
}
str = "memory_regions";
node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
if (node < 0) {
ERROR("Root node doesn't contain subnode '%s'\n", str);
panic();
} else {
rd_parse_memory_regions(rd, fdt, node);
}
str = "notifications";
node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
if (node < 0) {
WARN("Root node doesn't contain subnode '%s'\n", str);
} else {
rd_parse_notifications(rd, fdt, node);
}
str = "services";
node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
if (node < 0) {
WARN("Root node doesn't contain subnode '%s'\n", str);
} else {
rd_parse_services(rd, fdt, node);
}
}
/*******************************************************************************
* Platform handler to load resource descriptor blobs into the active Secure
* Partition context.
******************************************************************************/
int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size)
{
int rc;
int root_node;
assert(rd != NULL);
assert(ptr != NULL);
INFO("Reading RD blob at address %p\n", ptr);
rc = fdt_check_header(ptr);
if (rc != 0) {
ERROR("Wrong format for resource descriptor blob (%d).\n", rc);
return -1;
}
root_node = fdt_node_offset_by_compatible(ptr, -1, "arm,sp_rd");
if (root_node < 0) {
ERROR("Unrecognized resource descriptor blob (%d)\n", rc);
return -1;
}
rd_parse_root(rd, ptr, root_node);
return 0;
}
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <common/debug.h>
#include <plat/common/platform.h>
#include <tools_share/sptool.h>
static unsigned int sp_next;
/*******************************************************************************
* Platform handler get the address of a Secure Partition and its resource
* description blob. It iterates through all SPs detected by the platform. If
* there is information for another SP, it returns 0. If there are no more SPs,
* it returns -1.
******************************************************************************/
int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size,
void **rd_base, size_t *rd_size)
{
assert((sp_base != NULL) && (sp_size != NULL));
assert((rd_base != NULL) && (rd_base != NULL));
const uint64_t *pkg_base = (uint64_t *)PLAT_SP_PACKAGE_BASE;
struct sp_pkg_header *pkg_header = (struct sp_pkg_header *)pkg_base;
if (sp_next == 0) {
if (pkg_header->version != 0x1) {
ERROR("SP package has an unsupported version 0x%llx\n",
pkg_header->version);
panic();
}
}
if (sp_next >= pkg_header->number_of_sp) {
/* No more partitions in the package */
return -1;
}
const struct sp_pkg_entry *entry_list =
(const struct sp_pkg_entry *)((uintptr_t)pkg_base
+ sizeof(struct sp_pkg_header));
const struct sp_pkg_entry *entry = &(entry_list[sp_next]);
uint64_t sp_offset = entry->sp_offset;
uint64_t rd_offset = entry->rd_offset;
uintptr_t pkg_sp_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + sp_offset);
uintptr_t pkg_rd_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + rd_offset);
uint64_t pkg_sp_size = entry->sp_size;
uint64_t pkg_rd_size = entry->rd_size;
uintptr_t pkg_end = (uintptr_t)PLAT_SP_PACKAGE_BASE
+ (uintptr_t)PLAT_SP_PACKAGE_SIZE - 1U;
/*
* Check for overflows. The package header isn't trusted, so assert()
* can't be used here.
*/
uintptr_t pkg_sp_end = pkg_sp_base + pkg_sp_size - 1U;
uintptr_t pkg_rd_end = pkg_rd_base + pkg_rd_size - 1U;
if ((pkg_sp_end > pkg_end) || (pkg_sp_end < pkg_sp_base)) {
ERROR("Invalid Secure Partition size (0x%llx)\n", pkg_sp_size);
panic();
}
if ((pkg_rd_end > pkg_end) || (pkg_rd_end < pkg_rd_base)) {
ERROR("Invalid Resource Description blob size (0x%llx)\n",
pkg_rd_size);
panic();
}
/* Return location of the binaries. */
*sp_base = (void *)pkg_sp_base;
*sp_size = pkg_sp_size;
*rd_base = (void *)pkg_rd_base;
*rd_size = pkg_rd_size;
sp_next++;
return 0;
}
......@@ -95,7 +95,7 @@ LR_RO_DATA +0
/* cpu_ops must always be defined */
ScatterAssert(ImageLength(__CPU_OPS__) > 0)
#if ENABLE_SPM
#if SPM_MM
LR_SPM +0
{
/*
......
#
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
......@@ -57,7 +57,7 @@ BL31_SOURCES += $(PLAT_PATH)/drivers/scp/sq_scmi.c \
drivers/arm/css/mhu/css_mhu_doorbell.c
endif
ifeq (${ENABLE_SPM},1)
ifeq (${SPM_MM},1)
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
BL31_SOURCES += $(PLAT_PATH)/sq_spm.c
......
......@@ -159,7 +159,7 @@ void bl31_plat_runtime_setup(void)
void bl31_plat_arch_setup(void)
{
static const mmap_region_t secure_partition_mmap[] = {
#if ENABLE_SPM && SPM_MM
#if SPM_MM
MAP_REGION_FLAT(PLAT_SPM_BUF_BASE,
PLAT_SPM_BUF_SIZE,
MT_RW_DATA | MT_SECURE),
......@@ -173,7 +173,7 @@ void bl31_plat_arch_setup(void)
sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap);
enable_mmu_el3(XLAT_TABLE_NC);
#if ENABLE_SPM && SPM_MM
#if SPM_MM
memcpy((void *)SPM_SHIM_EXCEPTIONS_START,
(void *)SPM_SHIM_EXCEPTIONS_LMA,
(uintptr_t)SPM_SHIM_EXCEPTIONS_END -
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -10,7 +10,7 @@
#include <bl31/ehf.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <services/secure_partition.h>
#include <services/spm_mm_partition.h>
static const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_SQ_FLASH_MMAP,
......@@ -27,7 +27,7 @@ static const mmap_region_t plat_arm_secure_partition_mmap[] = {
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
static secure_partition_mp_info_t sp_mp_info[] = {
static spm_mm_mp_info_t sp_mp_info[] = {
{0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0},
{0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0},
{0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0},
......@@ -36,10 +36,10 @@ static secure_partition_mp_info_t sp_mp_info[] = {
{0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0},
};
const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
.h.size = sizeof(secure_partition_boot_info_t),
.h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = BL32_BASE,
.sp_mem_limit = BL32_LIMIT,
......@@ -63,7 +63,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
return plat_arm_secure_partition_mmap;
}
const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
......
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