Commit 9262eb54 authored by Andrew F. Davis's avatar Andrew F. Davis
Browse files

GIC: Do not flush cache when unneeded



When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.
Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
parent 39a8fa70
...@@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) ...@@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
* enabled. When the secondary CPU boots up, it initializes the * enabled. When the secondary CPU boots up, it initializes the
* GICC/GICR interface with the caches disabled. Hence flush the * GICC/GICR interface with the caches disabled. Hence flush the
* driver_data to ensure coherency. This is not required if the * driver_data to ensure coherency. This is not required if the
* platform has HW_ASSISTED_COHERENCY enabled. * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
* enabled.
*/ */
#if !HW_ASSISTED_COHERENCY #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
#endif #endif
...@@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) ...@@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
if (driver_data->target_masks[proc_num] == 0) { if (driver_data->target_masks[proc_num] == 0) {
driver_data->target_masks[proc_num] = driver_data->target_masks[proc_num] =
gicv2_get_cpuif_id(driver_data->gicd_base); gicv2_get_cpuif_id(driver_data->gicd_base);
#if !HW_ASSISTED_COHERENCY #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
/* /*
* PEs only update their own masks. Primary updates it with * PEs only update their own masks. Primary updates it with
* caches on. But because secondaries does it with caches off, * caches on. But because secondaries does it with caches off,
......
...@@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) ...@@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
* enabled. When the secondary CPU boots up, it initializes the * enabled. When the secondary CPU boots up, it initializes the
* GICC/GICR interface with the caches disabled. Hence flush the * GICC/GICR interface with the caches disabled. Hence flush the
* driver data to ensure coherency. This is not required if the * driver data to ensure coherency. This is not required if the
* platform has HW_ASSISTED_COHERENCY enabled. * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
* enabled.
*/ */
#if !HW_ASSISTED_COHERENCY #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
flush_dcache_range((uintptr_t) &gicv3_driver_data, flush_dcache_range((uintptr_t) &gicv3_driver_data,
sizeof(gicv3_driver_data)); sizeof(gicv3_driver_data));
flush_dcache_range((uintptr_t) gicv3_driver_data, flush_dcache_range((uintptr_t) gicv3_driver_data,
......
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