Reset EL2 and EL3 configurable controls

This patch resets EL2 and EL3 registers that have architecturally
UNKNOWN values on reset and that also provide EL2/EL3 configuration
and trap controls.

Specifically, the EL2 physical timer is disabled to prevent timer
interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32,
respectively.

Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of
non-secure access to certain system registers at EL1 or lower.

For AArch32, the patch also reverts the reset to SDCR which was
incorrectly added in a previous change.

Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f
Signed-off-by: David Cunado <david.cunado@arm.com>

include/common/aarch32/el3_common_macros.S

@@ -67,14 +67,6 @@
 	orr	r0, r0, #SCR_SIF_BIT
 	stcopr	r0, SCR
 
-	/* -----------------------------------------------------------------
-	 * Reset those registers that may have architecturally unknown reset
-	 * values
-	 * -----------------------------------------------------------------
-	 */
-	mov	r0, #0
-	stcopr	r0, SDCR
-
 	/* -----------------------------------------------------
 	 * Enable the Asynchronous data abort now that the
 	 * exception vectors have been setup.

include/lib/aarch32/arch.h

@@ -382,8 +382,8 @@
 
 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
 #define HDCR		p15, 4, c1, c1, 1
-#define SDCR		p15, 0, c1, c3, 1
 #define PMCR		p15, 0, c9, c12, 0
+#define CNTHP_CTL	p15, 4, c14, c2, 1
 
 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
 #define ICC_IAR1	p15, 0, c12, c12, 0

include/lib/aarch32/arch_helpers.h

@@ -250,6 +250,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
 DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
 
 DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
+DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
 DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
 
 /*

include/lib/aarch64/arch_helpers.h

@@ -280,6 +280,8 @@ DEFINE_SYSREG_READ_FUNC(isr_el1)
 DEFINE_SYSREG_READ_FUNC(ctr_el0)
 
 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
+DEFINE_SYSREG_RW_FUNCS(hstr_el2)
+DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
 DEFINE_SYSREG_READ_FUNC(pmcr_el0)
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)

lib/el3_runtime/aarch32/context_mgmt.c

@@ -243,6 +243,12 @@ void cm_prepare_el3_exit(uint32_t security_state)
 			 * (5 bits) and HPMN is at offset zero within HDCR.
 			 */
 			write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT);
+
+			/*
+			 * Reset CNTHP_CTL to disable the EL2 physical timer and
+			 * therefore prevent timer interrupts.
+			 */
+			write_cnthp_ctl(0);
 			isb();
 
 			write_scr(read_scr() & ~SCR_NS_BIT);

lib/el3_runtime/aarch64/context_mgmt.c

@@ -269,6 +269,18 @@ void cm_prepare_el3_exit(uint32_t security_state)
 			 */
 			write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS)
 					>> PMCR_EL0_N_SHIFT);
+			/*
+			 * Avoid unexpected traps of non-secure access to
+			 * certain system registers at EL1 or lower where
+			 * HSTR_EL2 is not completely reset to zero by the
+			 * hardware - zero the entire register.
+			 */
+			write_hstr_el2(0);
+			/*
+			 * Reset CNTHP_CTL_EL2 to disable the EL2 physical timer
+			 * and therefore prevent timer interrupts.
+			 */
+			write_cnthp_ctl_el2(0);
 		}
 	}