Merge changes from topic "pull-out-drivers" into integration

* changes:
  intel: Add ncore ccu driver
  intel: Fix watchdog driver structure
  intel: Fix qspi driver write config
  intel: Pull out common drivers into platform common

drivers/intel/soc/stratix10/io/s10_memmap_qspi.c

@@ -15,7 +15,7 @@
 #include <drivers/io/io_storage.h>
 #include <lib/utils.h>
 
-#include "drivers/qspi/cadence_qspi.h"
+#include "qspi/cadence_qspi.h"
 
 /* As we need to be able to keep state for seek, only one file can be open
  * at a time. Make this a structure and point to the entity->info. When we

plat/intel/soc/common/drivers/ccu/ncore_ccu.c

+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <errno.h>
+#include <lib/mmio.h>
+
+#include "ncore_ccu.h"
+#include <platform_def.h>
+
+uint32_t poll_active_bit(uint32_t dir);
+
+static coh_ss_id_t subsystem_id;
+
+
+void get_subsystem_id(void)
+{
+	uint32_t snoop_filter, directory, coh_agent;
+
+	snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR)));
+	directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
+	coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
+
+	subsystem_id.num_snoop_filter = snoop_filter + 1;
+	subsystem_id.num_directory = directory;
+	subsystem_id.num_coh_agent = coh_agent;
+}
+
+uint32_t directory_init(void)
+{
+	uint32_t dir_sf_mtn, dir_sf_en;
+	uint32_t dir, sf, ret;
+
+	for (dir = 0; dir < subsystem_id.num_directory; dir++) {
+
+		dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
+		dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
+
+		for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
+
+			/* Initialize All Entries */
+			mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
+
+			/* Poll Active Bit */
+			ret = poll_active_bit(dir);
+			if (ret != 0) {
+				ERROR("Timeout during active bit polling");
+				return -ETIMEDOUT;
+			}
+
+			/* Snoope Filter Enable */
+			mmio_write_32(dir_sf_en, BIT(sf));
+		}
+	}
+
+	return 0;
+}
+
+uint32_t coherent_agent_intfc_init(void)
+{
+	uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
+
+	for (dir = 0; dir < subsystem_id.num_directory; dir++) {
+
+		ca_snoop_en = DIRECTORY_UNIT(dir, NCORE_DIRUCASER0);
+
+		for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
+
+			ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
+
+			/* Coh Agent Snoop Enable */
+			if (CACHING_AGENT_BIT(ca_id))
+				mmio_write_32(ca_snoop_en, BIT(ca));
+
+			/* Coh Agent Snoop DVM Enable */
+			ca_type = CACHING_AGENT_TYPE(ca_id);
+			if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
+				mmio_write_32(NCORE_CCU_CSR(NCORE_CSADSER0),
+				BIT(ca));
+		}
+	}
+
+	return 0;
+}
+
+uint32_t poll_active_bit(uint32_t dir)
+{
+	uint32_t timeout = 80000;
+	uint32_t poll_dir =  DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR);
+
+	while (timeout > 0) {
+		if (mmio_read_32(poll_dir) == 0)
+			return 0;
+		timeout--;
+	}
+
+	return -1;
+}
+
+void bypass_ocram_firewall(void)
+{
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
+			OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+}
+
+uint32_t init_ncore_ccu(void)
+{
+	uint32_t status;
+
+	get_subsystem_id();
+	status = directory_init();
+	status = coherent_agent_intfc_init();
+	bypass_ocram_firewall();
+
+	return status;
+}

plat/intel/soc/common/drivers/ccu/ncore_ccu.h

+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NCORE_CCU_H
+#define NCORE_CCU_H
+
+
+#define NCORE_CCU_OFFSET		0xf7000000
+
+
+/* Coherent Sub-System Address Map */
+#define NCORE_CAIU_OFFSET		0x00000
+#define NCORE_CAIU_SIZE			0x01000
+
+#define NCORE_NCBU_OFFSET		0x60000
+#define NCORE_NCBU_SIZE			0x01000
+
+#define NCORE_DIRU_OFFSET		0x80000
+#define NCORE_DIRU_SIZE			0x01000
+
+#define NCORE_CMIU_OFFSET		0xc0000
+#define NCORE_CMIU_SIZE			0x01000
+
+#define NCORE_CSR_OFFSET		0xff000
+#define NCORE_CSADSERO			0x00040
+#define NCORE_CSUIDR			0x00ff8
+#define NCORE_CSIDR			0x00ffc
+
+/* Directory Unit Register Map */
+#define NCORE_DIRUSFER			0x00010
+#define NCORE_DIRUMRHER			0x00070
+#define NCORE_DIRUSFMCR			0x00080
+#define NCORE_DIRUSFMAR			0x00084
+
+/* Coherent Agent Interface Unit Register Map */
+#define NCORE_CAIUIDR			0x00ffc
+
+/* Snoop Enable Register */
+#define NCORE_DIRUCASER0		0x00040
+#define NCORE_DIRUCASER1		0x00044
+#define NCORE_DIRUCASER2		0x00048
+#define NCORE_DIRUCASER3		0x0004c
+
+#define NCORE_CSADSER0			0x00040
+#define NCORE_CSADSER1			0x00044
+#define NCORE_CSADSER2			0x00048
+#define NCORE_CSADSER3			0x0004c
+
+/* Protocols Definition */
+#define ACE_W_DVM			0
+#define ACE_L_W_DVM			1
+#define ACE_WO_DVM			2
+#define ACE_L_WO_DVM			3
+
+/* Bypass OC Ram Firewall */
+#define NCORE_FW_OCRAM_BLK_BASE		0x100200
+#define NCORE_FW_OCRAM_BLK_CGF1		0x04
+#define NCORE_FW_OCRAM_BLK_CGF2		0x08
+#define NCORE_FW_OCRAM_BLK_CGF3		0x0c
+#define NCORE_FW_OCRAM_BLK_CGF4		0x10
+
+#define OCRAM_PRIVILEGED_MASK		BIT(29)
+#define OCRAM_SECURE_MASK		BIT(30)
+
+/* Macros */
+#define NCORE_CCU_REG(base)		(NCORE_CCU_OFFSET + (base))
+#define NCORE_CCU_CSR(reg)		(NCORE_CCU_REG(NCORE_CSR_OFFSET)\
+						+ (reg))
+#define NCORE_CCU_DIR(reg)		(NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
+						+ (reg))
+#define NCORE_CCU_CAI(reg)		(NCORE_CCU_REG(NCORE_CAIU_OFFSET)\
+						+ (reg))
+
+#define DIRECTORY_UNIT(x, reg)		(NCORE_CCU_DIR(reg)\
+						+ NCORE_DIRU_SIZE * (x))
+#define COH_AGENT_UNIT(x, reg)		(NCORE_CCU_CAI(reg)\
+						+ NCORE_CAIU_SIZE * (x))
+
+#define COH_CPU0_BYPASS_REG(reg)	(NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
+						+ (reg))
+
+#define CSUIDR_NUM_CMI(x)		(((x) & 0x3f000000) >> 24)
+#define CSUIDR_NUM_DIR(x)		(((x) & 0x003f0000) >> 16)
+#define CSUIDR_NUM_NCB(x)		(((x) & 0x00003f00) >> 8)
+#define CSUIDR_NUM_CAI(x)		(((x) & 0x0000007f) >> 0)
+
+#define CSIDR_NUM_SF(x)			(((x) & 0x007c0000) >> 18)
+
+#define SNOOP_FILTER_ID(x)		(((x) << 16))
+
+#define CACHING_AGENT_BIT(x)		(((x) & 0x08000) >> 15)
+#define CACHING_AGENT_TYPE(x)		(((x) & 0xf0000) >> 16)
+
+
+typedef struct coh_ss_id {
+	uint8_t num_coh_mem;
+	uint8_t num_directory;
+	uint8_t num_non_coh_bridge;
+	uint8_t num_coh_agent;
+	uint8_t num_snoop_filter;
+} coh_ss_id_t;
+
+uint32_t init_ncore_ccu(void);
+
+#endif

plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c → plat/intel/soc/common/drivers/qspi/cadence_qspi.c

 /*
  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -65,13 +66,13 @@ int cad_qspi_set_read_config(uint32_t opcode, uint32_t instr_type,
 	return 0;
 }
 
-int cat_qspi_set_write_config(uint32_t addr_type, uint32_t data_type,
-		uint32_t mode_bit, uint32_t dummy_clk_cycle)
+int cad_qspi_set_write_config(uint32_t opcode, uint32_t addr_type,
+		uint32_t data_type, uint32_t dummy_clk_cycle)
 {
 	mmio_write_32(CAD_QSPI_OFFSET + CAD_QSPI_DEVWR,
+			CAD_QSPI_DEV_OPCODE(opcode) |
 			CAD_QSPI_DEV_ADDR_TYPE(addr_type) |
 			CAD_QSPI_DEV_DATA_TYPE(data_type) |
-			CAD_QSPI_DEV_MODE_BIT(mode_bit) |
 			CAD_QSPI_DEV_DUMMY_CLK_CYCLE(dummy_clk_cycle));
 
 	return 0;
@@ -161,7 +162,7 @@ int cad_qspi_stig_read_cmd(uint32_t opcode, uint32_t dummy, uint32_t num_bytes,
 		CAD_QSPI_FLASHCMD_NUMDUMMYBYTES(dummy);
 
 	if (cad_qspi_stig_cmd_helper(cad_qspi_cs, cmd)) {
-		ERROR("failed to send stig cmd");
+		ERROR("failed to send stig cmd\n");
 		return -1;
 	}
 
@@ -249,6 +250,8 @@ int cad_qspi_n25q_enable(void)
 	cad_qspi_set_read_config(QSPI_FAST_READ, CAD_QSPI_INST_SINGLE,
 			CAD_QSPI_ADDR_FASTREAD, CAT_QSPI_ADDR_SINGLE_IO, 1,
 			0);
+	cad_qspi_set_write_config(QSPI_WRITE, 0, 0, 0);
+
 	return 0;
 }
 
@@ -512,7 +515,7 @@ int cad_qspi_init(uint32_t desired_clk_freq, uint32_t clk_phase,
 	INFO("Initializing Qspi\n");
 
 	if (cad_qspi_idle() == 0) {
-		ERROR("device not idle");
+		ERROR("device not idle\n");
 		return -1;
 	}
 
@@ -587,8 +590,9 @@ int cad_qspi_init(uint32_t desired_clk_freq, uint32_t clk_phase,
 		return -1;
 	}
 
-	cad_qspi_configure_dev_size(S10_QSPI_ADDR_BYTES,
-				S10_QSPI_BYTES_PER_DEV, S10_BYTES_PER_BLOCK);
+	cad_qspi_configure_dev_size(INTEL_QSPI_ADDR_BYTES,
+				INTEL_QSPI_BYTES_PER_DEV,
+				INTEL_BYTES_PER_BLOCK);
 
 	INFO("Flash size: %d Bytes\n", qspi_device_size);
 
@@ -689,13 +693,13 @@ int cad_qspi_read(void *buffer, uint32_t  offset, uint32_t  size)
 			((long) ((int *)buffer) & 0x3)  ||
 			(offset & 0x3) ||
 			(size & 0x3)) {
-		ERROR("Invalid read parameter");
+		ERROR("Invalid read parameter\n");
 		return -1;
 	}
 
 	if (CAD_QSPI_INDRD_RD_STAT(mmio_read_32(CAD_QSPI_OFFSET +
 						CAD_QSPI_INDRD))) {
-		ERROR("Read in progress");
+		ERROR("Read in progress\n");
 		return -1;
 	}
 

plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.h → plat/intel/soc/common/drivers/qspi/cadence_qspi.h

 /*
  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CAD_QSPI_H__
-#define __CAD_QSPI_H__
+#ifndef CAD_QSPI_H
+#define CAD_QSPI_H
 
 #define CAD_QSPI_MICRON_N25Q_SUPPORT		1
 
@@ -146,12 +147,14 @@
 
 #define CAD_QSPI_SUBSECTOR_SIZE			0x1000
 
-#define S10_QSPI_ADDR_BYTES			2
-#define S10_QSPI_BYTES_PER_DEV			256
-#define S10_BYTES_PER_BLOCK			16
+#define INTEL_QSPI_ADDR_BYTES			2
+#define INTEL_QSPI_BYTES_PER_DEV		256
+#define INTEL_BYTES_PER_BLOCK			16
 
 #define QSPI_FAST_READ				0xb
 
+#define QSPI_WRITE				0x2
+
 // QSPI CONFIGURATIONS
 
 #define QSPI_CONFIG_CPOL			1

plat/intel/soc/stratix10/drivers/wdt/watchdog.c → plat/intel/soc/common/drivers/wdt/watchdog.c

@@ -28,10 +28,10 @@ void watchdog_info(void)
 void watchdog_status(void)
 {
 	if (mmio_read_32(WDT_CR) & 1) {
-		INFO("Watchdog Timer in currently enabled\n");
+		INFO("Watchdog Timer is currently enabled\n");
 		INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
 	} else {
-		INFO("Watchdog Timer in currently disabled\n");
+		INFO("Watchdog Timer is currently disabled\n");
 	}
 }
 
@@ -49,10 +49,5 @@ void watchdog_init(int watchdog_clk)
 
 	mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
 
-	watchdog_enable();
-}
-
-void watchdog_enable(void)
-{
 	mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
 }

plat/intel/soc/stratix10/drivers/wdt/watchdog.h → plat/intel/soc/common/drivers/wdt/watchdog.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CAD_WATCHDOG_H__
-#define __CAD_WATCHDOG_H__
+#ifndef CAD_WATCHDOG_H
+#define CAD_WATCHDOG_H
 
 #define WDT_BASE			(0xFFD00200)
 #define WDT_REG_SIZE_OFFSET		(0x4)
@@ -32,7 +32,6 @@
 
 
 void watchdog_init(int watchdog_clk);
-void watchdog_enable(void);
 void watchdog_info(void);
 void watchdog_status(void);
 void watchdog_sw_rst(void);

plat/intel/soc/stratix10/bl2_plat_setup.c

@@ -31,8 +31,8 @@
 #include "s10_pinmux.h"
 #include "aarch64/stratix10_private.h"
 #include "include/s10_mailbox.h"
-#include "drivers/qspi/cadence_qspi.h"
-#include "drivers/wdt/watchdog.h"
+#include "qspi/cadence_qspi.h"
+#include "wdt/watchdog.h"
 
 
 const mmap_region_t plat_stratix10_mmap[] = {

plat/intel/soc/stratix10/platform.mk

@@ -7,6 +7,7 @@
 PLAT_INCLUDES		:=	\
 			-Iplat/intel/soc/stratix10/			\
 			-Iplat/intel/soc/stratix10/include/		\
+			-Iplat/intel/soc/common/drivers/
 
 PLAT_BL_COMMON_SOURCES	:=	\
 			lib/xlat_tables/xlat_tables_common.c 		\
@@ -46,8 +47,8 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
 		common/desc_image_load.c				\
 		plat/intel/soc/stratix10/soc/s10_mailbox.c		\
-		plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c	\
-		plat/intel/soc/stratix10/drivers/wdt/watchdog.c
+		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
+		plat/intel/soc/common/drivers/wdt/watchdog.c
 
 BL31_SOURCES	+=	drivers/arm/cci/cci.c				\
 		lib/cpus/aarch64/cortex_a53.S				\