hikey960: drop LOAD_IMAGE v1

Since LOAD_IMAGE_V2 is always enabled in HiKey960 platform. Drop
LOAD_IMAGE v1 to simplify code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

plat/hisilicon/hikey960/hikey960_bl1_setup.c

@@ -74,7 +74,6 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
 	return &bl1_tzram_layout;
 }
 
-#if LOAD_IMAGE_V2
 /*******************************************************************************
  * Function that takes a memory layout into which BL2 has been loaded and
  * populates a new memory layout for BL2 that ensures that BL1's data sections
@@ -96,7 +95,6 @@ void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
 
 	flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
 }
-#endif /* LOAD_IMAGE_V2 */
 
 /*
  * Perform any BL1 specific platform actions.
@@ -118,16 +116,6 @@ void bl1_early_platform_setup(void)
 	bl1_tzram_layout.total_base = BL1_RW_BASE;
 	bl1_tzram_layout.total_size = BL1_RW_SIZE;
 
-#if !LOAD_IMAGE_V2
-	/* Calculate how much RAM BL1 is using and how much remains free */
-	bl1_tzram_layout.free_base = BL1_RW_BASE;
-	bl1_tzram_layout.free_size = BL1_RW_SIZE;
-	reserve_mem(&bl1_tzram_layout.free_base,
-		    &bl1_tzram_layout.free_size,
-		    BL1_RAM_BASE,
-		    BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
-#endif /* LOAD_IMAGE_V2 */
-
 	INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
 	     BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
 }

plat/hisilicon/hikey960/hikey960_bl2_setup.c

@@ -14,11 +14,9 @@
 #include <generic_delay_timer.h>
 #include <hi3660.h>
 #include <mmio.h>
-#if LOAD_IMAGE_V2
 #ifdef SPD_opteed
 #include <optee_utils.h>
 #endif
-#endif
 #include <platform_def.h>
 #include <string.h>
 #include <ufs.h>
@@ -47,98 +45,13 @@
 
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 
-#if !LOAD_IMAGE_V2
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t		bl31_params;
-	image_info_t		bl31_image_info;
-	image_info_t		bl32_image_info;
-	image_info_t		bl33_image_info;
-	entry_point_info_t	bl33_ep_info;
-	entry_point_info_t	bl32_ep_info;
-	entry_point_info_t	bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
-	return &bl2_tzram_layout;
-}
-
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
-	bl31_params_t *bl2_to_bl31_params = NULL;
-
-	/*
-	 * Initialise the memory for all the arguments that needs to
-	 * be passed to BL3-1
-	 */
-	memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
-
-	/* Assign memory for TF related information */
-	bl2_to_bl31_params = &bl31_params_mem.bl31_params;
-	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
-	/* Fill BL3-1 related information */
-	bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	/* Fill BL3-2 related information if it exists */
-#ifdef BL32_BASE
-	bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
-		VERSION_1, 0);
-	bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-#endif
-
-	/* Fill BL3-3 related information */
-	bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
-		PARAM_EP, VERSION_1, 0);
-
-	/* BL3-3 expects to receive the primary CPU MPID (through x0) */
-	bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
-	bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	return bl2_to_bl31_params;
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading SCP_BL2 (if used),
- * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
- ******************************************************************************/
-void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
-{
-	hikey960_init_ufs();
-	hikey960_io_setup();
-
-	*scp_bl2_meminfo = bl2_tzram_layout;
-}
-#endif /* LOAD_IMAGE_V2 */
-
 extern int load_lpm3(void);
 
 /*******************************************************************************
  * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
  * Return 0 on success, -1 otherwise.
  ******************************************************************************/
-#if LOAD_IMAGE_V2
 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#else
-int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#endif
 {
 	int i;
 	int *buf;
@@ -238,7 +151,6 @@ uint32_t hikey960_get_spsr_for_bl33_entry(void)
 }
 #endif /* AARCH32 */
 
-#if LOAD_IMAGE_V2
 int hikey960_bl2_handle_post_image_load(unsigned int image_id)
 {
 	int err = 0;
@@ -299,100 +211,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 	return hikey960_bl2_handle_post_image_load(image_id);
 }
 
-#else /* LOAD_IMAGE_V2 */
-
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
-	bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL;
-#endif
-
-	return &bl31_params_mem.bl31_ep_info;
-}
-
-void bl2_plat_set_bl31_ep_info(image_info_t *image,
-			       entry_point_info_t *bl31_ep_info)
-{
-	SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
-	bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-				       DISABLE_ALL_EXCEPTIONS);
-}
-
-/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On Hikey we only set the security state of the entrypoint
- ******************************************************************************/
-#ifdef BL32_BASE
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
-					entry_point_info_t *bl32_ep_info)
-{
-	SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
-	/*
-	 * The Secure Payload Dispatcher service is responsible for
-	 * setting the SPSR prior to entry into the BL32 image.
-	 */
-	bl32_ep_info->spsr = 0;
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
-	/*
-	 * Populate the extents of memory available for loading BL32.
-	 */
-	bl32_meminfo->total_base = BL32_BASE;
-	bl32_meminfo->free_base = BL32_BASE;
-	bl32_meminfo->total_size =
-			(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-	bl32_meminfo->free_size =
-			(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-}
-#endif /* BL32_BASE */
-
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
-			       entry_point_info_t *bl33_ep_info)
-{
-	unsigned long el_status;
-	unsigned int mode;
-
-	/* Figure out what mode we enter the non-secure world in */
-	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-	el_status &= ID_AA64PFR0_ELX_MASK;
-
-	if (el_status)
-		mode = MODE_EL2;
-	else
-		mode = MODE_EL1;
-
-	/*
-	 * TODO: Consider the possibility of specifying the SPSR in
-	 * the FIP ToC and allowing the platform to have a say as
-	 * well.
-	 */
-	bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX,
-				       DISABLE_ALL_EXCEPTIONS);
-	SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
-}
-
-void bl2_plat_flush_bl31_params(void)
-{
-	flush_dcache_range((unsigned long)&bl31_params_mem,
-			   sizeof(bl2_to_bl31_params_mem_t));
-}
-
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
-	bl33_meminfo->total_base = DDR_BASE;
-	bl33_meminfo->total_size = DDR_SIZE;
-	bl33_meminfo->free_base = DDR_BASE;
-	bl33_meminfo->free_size = DDR_SIZE;
-}
-#endif /* LOAD_IMAGE_V2 */
-
 void bl2_early_platform_setup(meminfo_t *mem_layout)
 {
 	unsigned int id, uart_base;

plat/hisilicon/hikey960/hikey960_bl31_setup.c

@@ -78,13 +78,8 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 	return NULL;
 }
 
-#if LOAD_IMAGE_V2
 void bl31_early_platform_setup(void *from_bl2,
 			       void *plat_params_from_bl2)
-#else
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-		void *plat_params_from_bl2)
-#endif
 {
 	unsigned int id, uart_base;
 
@@ -102,7 +97,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
 
-#if LOAD_IMAGE_V2
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
@@ -129,23 +123,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 
 	if (bl33_ep_info.pc == 0)
 		panic();
-
-#else /* LOAD_IMAGE_V2 */
-
-	/*
-	 * Check params passed from BL2 should not be NULL,
-	 */
-	assert(from_bl2 != NULL);
-	assert(from_bl2->h.type == PARAM_BL31);
-	assert(from_bl2->h.version >= VERSION_1);
-
-	/*
-	 * Copy BL3-2 and BL3-3 entry point information.
-	 * They are stored in Secure RAM, in BL2's address space.
-	 */
-	bl32_ep_info = *from_bl2->bl32_ep_info;
-	bl33_ep_info = *from_bl2->bl33_ep_info;
-#endif /* LOAD_IMAGE_V2 */
 }
 
 void bl31_plat_arch_setup(void)

plat/hisilicon/hikey960/include/platform_def.h

@@ -75,13 +75,11 @@
 #define BL32_DRAM_BASE                  DDR_SEC_BASE
 #define BL32_DRAM_LIMIT                 (DDR_SEC_BASE+DDR_SEC_SIZE)
 
-#if LOAD_IMAGE_V2
 #ifdef SPD_opteed
 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
 #define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE	(BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
 #define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE	0x400000 /* 4MB */
 #endif
-#endif
 
 #if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
 #define TSP_SEC_MEM_BASE		BL32_DRAM_BASE
@@ -121,15 +119,11 @@
 #endif
 
 #ifdef IMAGE_BL2
-#if LOAD_IMAGE_V2
 #ifdef SPD_opteed
 #define MAX_XLAT_TABLES			4
 #else
 #define MAX_XLAT_TABLES			3
 #endif
-#else
-#define MAX_XLAT_TABLES			3
-#endif
 #endif
 
 #define MAX_MMAP_REGIONS		16

plat/hisilicon/hikey960/platform.mk

@@ -66,23 +66,20 @@ BL1_SOURCES		+=	bl1/tbbr/tbbr_img_desc.c		\
 				plat/hisilicon/hikey960/hikey960_io_storage.c \
 				${HIKEY960_GIC_SOURCES}
 
-BL2_SOURCES		+=	drivers/io/io_block.c			\
+BL2_SOURCES		+=	common/desc_image_load.c		\
+				drivers/io/io_block.c			\
 				drivers/io/io_fip.c			\
 				drivers/io/io_storage.c			\
 				drivers/ufs/ufs.c			\
+				plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
 				plat/hisilicon/hikey960/hikey960_bl2_setup.c \
+				plat/hisilicon/hikey960/hikey960_image_load.c \
 				plat/hisilicon/hikey960/hikey960_io_storage.c \
 				plat/hisilicon/hikey960/hikey960_mcu_load.c
 
-ifeq (${LOAD_IMAGE_V2},1)
-BL2_SOURCES		+=	plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
-				plat/hisilicon/hikey960/hikey960_image_load.c \
-				common/desc_image_load.c
-
 ifeq (${SPD},opteed)
 BL2_SOURCES		+=	lib/optee/optee_utils.c
 endif
-endif
 
 BL31_SOURCES		+=	drivers/arm/cci/cci.c			\
 				lib/cpus/aarch64/cortex_a53.S           \