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adam.huang
Arm Trusted Firmware
Commits
9ad10314
Commit
9ad10314
authored
4 years ago
by
André Przywara
Committed by
TrustedFirmware Code Review
4 years ago
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Merge "allwinner: Use CPUIDLE hardware when available" into integration
parents
cebe4ccd
de37db6c
Changes
2
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2 changed files
plat/allwinner/common/sunxi_cpu_ops.c
+13
-1
plat/allwinner/common/sunxi_cpu_ops.c
plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
+6
-1
plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
with
19 additions
and
2 deletions
+19
-2
plat/allwinner/common/sunxi_cpu_ops.c
View file @
9ad10314
...
...
@@ -15,11 +15,14 @@
#include <lib/utils_def.h>
#include <plat/common/platform.h>
#include <core_off_arisc.h>
#include <sunxi_cpucfg.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
#ifndef SUNXI_CPUIDLE_EN_REG
#include <core_off_arisc.h>
#endif
static
void
sunxi_cpu_disable_power
(
unsigned
int
cluster
,
unsigned
int
core
)
{
if
(
mmio_read_32
(
SUNXI_CPU_POWER_CLAMP_REG
(
cluster
,
core
))
==
0xff
)
...
...
@@ -72,6 +75,14 @@ void sunxi_cpu_power_off_self(void)
/* Simplifies assembly, all SoCs so far are single cluster anyway. */
assert
(
MPIDR_AFFLVL1_VAL
(
mpidr
)
==
0
);
#ifdef SUNXI_CPUIDLE_EN_REG
/* Enable the CPUIDLE hardware (only really needs to be done once). */
mmio_write_32
(
SUNXI_CPUIDLE_EN_REG
,
0x16aa0000
);
mmio_write_32
(
SUNXI_CPUIDLE_EN_REG
,
0xaa160001
);
/* Trigger power off for this core. */
mmio_write_32
(
SUNXI_CORE_CLOSE_REG
,
BIT_32
(
core
));
#else
/*
* If we are supposed to turn ourself off, tell the arisc SCP
* to do that work for us. The code expects the core mask to be
...
...
@@ -79,6 +90,7 @@ void sunxi_cpu_power_off_self(void)
*/
sunxi_execute_arisc_code
(
arisc_core_off
,
sizeof
(
arisc_core_off
),
BIT_32
(
core
));
#endif
}
void
sunxi_cpu_on
(
u_register_t
mpidr
)
...
...
This diff is collapsed.
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plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
View file @
9ad10314
/*
* Copyright (c) 2017-201
8
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-20
2
1, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
...
...
@@ -24,4 +24,9 @@
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
#endif
/* SUNXI_CPUCFG_H */
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