Merge changes from topic "amlogic-refactoring" into integration

* changes:
  amlogic: Fix includes order
  amlogic: Fix header guards
  amlogic: Fix prefixes in the SoC specific files
  amlogic: Fix prefixes in the PM code
  amlogic: Fix prefixes in the SCPI related code
  amlogic: Fix prefixes in the MHU code
  amlogic: Fix prefixes in the SIP/SVC code
  amlogic: Fix prefixes in the thermal driver
  amlogic: Fix prefixes in the private header file
  amlogic: Fix prefixes in the efuse driver
  amlogic: Fix prefixes in the platform macros file
  amlogic: Fix prefixes in the helpers file
  amlogic: Rework Makefiles
  amlogic: Move the SIP SVC code to common directory
  amlogic: Move topology file to common directory
  amlogic: Move thermal code to common directory
  amlogic: Move MHU code to common directory
  amlogic: Move efuse code to common directory
  amlogic: Move platform macros assembly file to common directory
  amlogic: Introduce unified private header file
  amlogic: Move SCPI code to common directory
  amlogic: Move the SHA256 DMA driver to common directory
  amlogic: Move assembly helpers to common directory
  amlogic: Introduce directory parameters in the makefiles
  meson: Rename platform directory to amlogic

.gitignore

@@ -22,7 +22,7 @@ tools/cert_create/src/**/*.o
 tools/cert_create/cert_create
 tools/cert_create/cert_create.exe
 tools/marvell/doimage/doimage
-tools/meson/doimage
+tools/amlogic/doimage
 tools/stm32image/*.o
 tools/stm32image/stm32image
 tools/stm32image/stm32image.exe

docs/maintainers.rst

@@ -37,16 +37,16 @@ Amlogic Meson S905 (GXBB) platform port
 :M: Andre Przywara <andre.przywara@arm.com>
 :G: `Andre-ARM`_
 :F: docs/plat/meson-gxbb.rst
-:F: drivers/meson/
-:F: plat/meson/gxbb/
+:F: drivers/amlogic/
+:F: plat/amlogic/gxbb/
 
 Amlogic Meson S905x (GXL) platform port
 ---------------------------------------
 :M: Remi Pommarel <repk@triplefau.lt>
 :G: `remi-triplefault`_
 :F: docs/plat/meson-gxl.rst
-:F: drivers/meson/gxl
-:F: plat/meson/gxl/
+:F: drivers/amlogic/gxl
+:F: plat/amlogic/gxl/
 
 Armv7-A architecture port
 -------------------------

drivers/meson/console/aarch64/meson_console.S → drivers/amlogic/console/aarch64/meson_console.S

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #include <asm_macros.S>
 #include <assert_macros.S>
 #include <console_macros.S>
-#include <drivers/meson/meson_console.h>
+#include <drivers/amlogic/meson_console.h>
 
 	.globl console_meson_register
 	.globl console_meson_init

drivers/meson/gxl/crypto/sha_dma.c → drivers/amlogic/crypto/sha_dma.c

@@ -4,10 +4,10 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
 #include <arch_helpers.h>
-#include <lib/mmio.h>
+#include <assert.h>
 #include <crypto/sha_dma.h>
+#include <lib/mmio.h>
 
 #define AML_SHA_DMA_BASE 0xc883e000
 

plat/meson/gxbb/aarch64/gxbb_helpers.S → plat/amlogic/common/aarch64/aml_helpers.S

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 	.globl	plat_is_my_cpu_primary
 	.globl	plat_my_core_pos
 	.globl	plat_reset_handler
-	.globl	plat_gxbb_calc_core_pos
+	.globl	plat_calc_core_pos
 
 	/* -----------------------------------------------------
 	 * unsigned int plat_my_core_pos(void);
@@ -24,17 +24,17 @@
 	 */
 func plat_my_core_pos
 	mrs	x0, mpidr_el1
-	b	plat_gxbb_calc_core_pos
+	b	plat_calc_core_pos
 endfunc plat_my_core_pos
 
 	/* -----------------------------------------------------
-	 *  unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
+	 *  unsigned int plat_calc_core_pos(u_register_t mpidr);
 	 * -----------------------------------------------------
 	 */
-func plat_gxbb_calc_core_pos
+func plat_calc_core_pos
 	and	x0, x0, #MPIDR_CPU_MASK
 	ret
-endfunc plat_gxbb_calc_core_pos
+endfunc plat_calc_core_pos
 
 	/* -----------------------------------------------------
 	 * unsigned int plat_is_my_cpu_primary(void);
@@ -43,7 +43,7 @@ endfunc plat_gxbb_calc_core_pos
 func plat_is_my_cpu_primary
 	mrs	x0, mpidr_el1
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #GXBB_PRIMARY_CPU
+	cmp	x0, #AML_PRIMARY_CPU
 	cset	w0, eq
 	ret
 endfunc plat_is_my_cpu_primary
@@ -61,9 +61,9 @@ endfunc platform_mem_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_init
-	mov_imm	x0, GXBB_UART0_AO_BASE
-	mov_imm	x1, GXBB_UART0_AO_CLK_IN_HZ
-	mov_imm	x2, GXBB_UART_BAUDRATE
+	mov_imm	x0, AML_UART0_AO_BASE
+	mov_imm	x1, AML_UART0_AO_CLK_IN_HZ
+	mov_imm	x2, AML_UART_BAUDRATE
 	b	console_meson_init
 endfunc plat_crash_console_init
 
@@ -73,7 +73,7 @@ endfunc plat_crash_console_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	mov_imm	x1, GXBB_UART0_AO_BASE
+	mov_imm	x1, AML_UART0_AO_BASE
 	b	console_meson_core_putc
 endfunc plat_crash_console_putc
 
@@ -84,7 +84,7 @@ endfunc plat_crash_console_putc
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_flush
-	mov_imm	x0, GXBB_UART0_AO_BASE
+	mov_imm	x0, AML_UART0_AO_BASE
 	b	console_meson_core_flush
 endfunc plat_crash_console_flush
 

plat/meson/gxl/gxl_efuse.c → plat/amlogic/common/aml_efuse.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stdint.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 #define EFUSE_BASE	0x140
 #define EFUSE_SIZE	0xC0
 
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size)
+uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size)
 {
 	if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
 		return 0;
 
-	return scpi_efuse_read(dst, offset + EFUSE_BASE, size);
+	return aml_scpi_efuse_read(dst, offset + EFUSE_BASE, size);
 }
 
-uint64_t gxbb_efuse_user_max(void)
+uint64_t aml_efuse_user_max(void)
 {
 	return EFUSE_SIZE;
 }

plat/meson/gxl/gxl_mhu.c → plat/amlogic/common/aml_mhu.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,43 +10,43 @@
 
 static DEFINE_BAKERY_LOCK(mhu_lock);
 
-void mhu_secure_message_start(void)
+void aml_mhu_secure_message_start(void)
 {
 	bakery_lock_get(&mhu_lock);
 
-	while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
+	while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
 		;
 }
 
-void mhu_secure_message_send(uint32_t msg)
+void aml_mhu_secure_message_send(uint32_t msg)
 {
-	mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
+	mmio_write_32(AML_HIU_MAILBOX_SET_3, msg);
 
-	while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
+	while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
 		;
 }
 
-uint32_t mhu_secure_message_wait(void)
+uint32_t aml_mhu_secure_message_wait(void)
 {
 	uint32_t val;
 
 	do {
-		val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
+		val = mmio_read_32(AML_HIU_MAILBOX_STAT_0);
 	} while (val == 0);
 
 	return val;
 }
 
-void mhu_secure_message_end(void)
+void aml_mhu_secure_message_end(void)
 {
-	mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
+	mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
 
 	bakery_lock_release(&mhu_lock);
 }
 
-void mhu_secure_init(void)
+void aml_mhu_secure_init(void)
 {
 	bakery_lock_init(&mhu_lock);
 
-	mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
+	mmio_write_32(AML_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
 }

plat/meson/gxl/gxl_scpi.c → plat/amlogic/common/aml_scpi.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
+#include <crypto/sha_dma.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
 #include <string.h>
-#include <crypto/sha_dma.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 #define SIZE_SHIFT	20
 #define SIZE_MASK	0x1FF
@@ -30,19 +30,19 @@
 #define SCPI_CMD_SET_FW_ADDR 0xd3
 #define SCPI_CMD_FW_SIZE 0xd2
 
-static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
+static inline uint32_t aml_scpi_cmd(uint32_t command, uint32_t size)
 {
 	return command | (size << SIZE_SHIFT);
 }
 
-static void scpi_secure_message_send(uint32_t command, uint32_t size)
+static void aml_scpi_secure_message_send(uint32_t command, uint32_t size)
 {
-	mhu_secure_message_send(scpi_cmd(command, size));
+	aml_mhu_secure_message_send(aml_scpi_cmd(command, size));
 }
 
-uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
+static uint32_t aml_scpi_secure_message_receive(void **message_out, size_t *size_out)
 {
-	uint32_t response = mhu_secure_message_wait();
+	uint32_t response = aml_mhu_secure_message_wait();
 
 	size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
 
@@ -52,12 +52,12 @@ uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
 		*size_out = size;
 
 	if (message_out != NULL)
-		*message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
+		*message_out = (void *)AML_MHU_SECURE_SCP_TO_AP_PAYLOAD;
 
 	return response;
 }
 
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
+void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
 			      uint32_t cluster_state, uint32_t css_state)
 {
 	uint32_t state = (mpidr & 0x0F) | /* CPU ID */
@@ -66,45 +66,45 @@ void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
 			 (cluster_state << 12) |
 			 (css_state << 16);
 
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
+	aml_mhu_secure_message_start();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
+	aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
+	aml_mhu_secure_message_wait();
+	aml_mhu_secure_message_end();
 }
 
-uint32_t scpi_sys_power_state(uint64_t system_state)
+uint32_t aml_scpi_sys_power_state(uint64_t system_state)
 {
 	uint32_t *response;
 	size_t size;
 
-	mhu_secure_message_start();
-	mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
-	scpi_secure_message_receive((void *)&response, &size);
-	mhu_secure_message_end();
+	aml_mhu_secure_message_start();
+	mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
+	aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
+	aml_scpi_secure_message_receive((void *)&response, &size);
+	aml_mhu_secure_message_end();
 
 	return *response;
 }
 
-void scpi_jtag_set_state(uint32_t state, uint8_t select)
+void aml_scpi_jtag_set_state(uint32_t state, uint8_t select)
 {
-	assert(state <= GXBB_JTAG_STATE_OFF);
+	assert(state <= AML_JTAG_STATE_OFF);
 
-	if (select > GXBB_JTAG_A53_EE) {
+	if (select > AML_JTAG_A53_EE) {
 		WARN("BL31: Invalid JTAG select (0x%x).\n", select);
 		return;
 	}
 
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
+	aml_mhu_secure_message_start();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD,
 		      (state << 8) | (uint32_t)select);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
+	aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
+	aml_mhu_secure_message_wait();
+	aml_mhu_secure_message_end();
 }
 
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
+uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
 {
 	uint32_t *response;
 	size_t resp_size;
@@ -112,12 +112,12 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
 	if (size > 0x1FC)
 		return 0;
 
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
-	scpi_secure_message_receive((void *)&response, &resp_size);
-	mhu_secure_message_end();
+	aml_mhu_secure_message_start();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
+	aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
+	aml_scpi_secure_message_receive((void *)&response, &resp_size);
+	aml_mhu_secure_message_end();
 
 	/*
 	 * response[0] is the size of the response message.
@@ -129,60 +129,60 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
 	return *response;
 }
 
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
-			  uint32_t arg2, uint32_t arg3)
+void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
+			      uint32_t arg2, uint32_t arg3)
 {
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
-	mhu_secure_message_send(scpi_cmd(0xC3, 16));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
+	aml_mhu_secure_message_start();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
+	aml_mhu_secure_message_send(aml_scpi_cmd(0xC3, 16));
+	aml_mhu_secure_message_wait();
+	aml_mhu_secure_message_end();
 }
 
-static inline void scpi_copy_scp_data(uint8_t *data, size_t len)
+static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len)
 {
-	void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+	void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
 	size_t sz;
 
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
-	scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
-	mhu_secure_message_wait();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
+	aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
+	aml_mhu_secure_message_wait();
 
 	for (sz = 0; sz < len; sz += SIZE_FWBLK) {
 		memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz));
-		mhu_secure_message_send(SCPI_CMD_COPY_FW);
+		aml_mhu_secure_message_send(SCPI_CMD_COPY_FW);
 	}
 }
 
-static inline void scpi_set_scp_addr(uint64_t addr, size_t len)
+static inline void aml_scpi_set_scp_addr(uint64_t addr, size_t len)
 {
-	volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+	volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
 
 	/*
-	 * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
+	 * It is ok as AML_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
 	 * non cachable
 	 */
 	*dst = addr;
-	scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr));
-	mhu_secure_message_wait();
+	aml_scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr));
+	aml_mhu_secure_message_wait();
 
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
-	scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
-	mhu_secure_message_wait();
+	mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
+	aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
+	aml_mhu_secure_message_wait();
 }
 
-static inline void scpi_send_fw_hash(uint8_t hash[], size_t len)
+static inline void aml_scpi_send_fw_hash(uint8_t hash[], size_t len)
 {
-	void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+	void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
 
 	memcpy(dst, hash, len);
-	mhu_secure_message_send(0xd0);
-	mhu_secure_message_send(0xd1);
-	mhu_secure_message_send(0xd5);
-	mhu_secure_message_end();
+	aml_mhu_secure_message_send(0xd0);
+	aml_mhu_secure_message_send(0xd1);
+	aml_mhu_secure_message_send(0xd5);
+	aml_mhu_secure_message_end();
 }
 
 /**
@@ -193,7 +193,7 @@ static inline void scpi_send_fw_hash(uint8_t hash[], size_t len)
  * @param send: If set, actually copy the firmware in SCP memory otherwise only
  *  send the firmware address.
  */
-void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
+void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
 {
 	struct asd_ctx ctx;
 
@@ -201,11 +201,11 @@ void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
 	asd_sha_update(&ctx, (void *)addr, size);
 	asd_sha_finalize(&ctx);
 
-	mhu_secure_message_start();
+	aml_mhu_secure_message_start();
 	if (send == 0)
-		scpi_set_scp_addr(addr, size);
+		aml_scpi_set_scp_addr(addr, size);
 	else
-		scpi_copy_scp_data((void *)addr, size);
+		aml_scpi_copy_scp_data((void *)addr, size);
 
-	scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest));
+	aml_scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest));
 }

plat/meson/gxl/gxl_sip_svc.c → plat/amlogic/common/aml_sip_svc.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <common/debug.h>
+#include <common/runtime_svc.h>
 #include <lib/mmio.h>
 #include <platform_def.h>
-#include <common/runtime_svc.h>
 #include <stdint.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 /*******************************************************************************
  * This function is responsible for handling all SiP calls
  ******************************************************************************/
-static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
+static uintptr_t aml_sip_handler(uint32_t smc_fid,
 				  u_register_t x1, u_register_t x2,
 				  u_register_t x3, u_register_t x4,
 				  void *cookie, void *handle,
@@ -23,28 +23,28 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
 {
 	switch (smc_fid) {
 
-	case GXBB_SM_GET_SHARE_MEM_INPUT_BASE:
-		SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE);
+	case AML_SM_GET_SHARE_MEM_INPUT_BASE:
+		SMC_RET1(handle, AML_SHARE_MEM_INPUT_BASE);
 
-	case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE:
-		SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE);
+	case AML_SM_GET_SHARE_MEM_OUTPUT_BASE:
+		SMC_RET1(handle, AML_SHARE_MEM_OUTPUT_BASE);
 
-	case GXBB_SM_EFUSE_READ:
+	case AML_SM_EFUSE_READ:
 	{
-		void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE;
-		uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2);
+		void *dst = (void *)AML_SHARE_MEM_OUTPUT_BASE;
+		uint64_t ret = aml_efuse_read(dst, (uint32_t)x1, x2);
 
 		SMC_RET1(handle, ret);
 	}
-	case GXBB_SM_EFUSE_USER_MAX:
-		SMC_RET1(handle,  gxbb_efuse_user_max());
+	case AML_SM_EFUSE_USER_MAX:
+		SMC_RET1(handle,  aml_efuse_user_max());
 
-	case GXBB_SM_JTAG_ON:
-		scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1);
+	case AML_SM_JTAG_ON:
+		aml_scpi_jtag_set_state(AML_JTAG_STATE_ON, x1);
 		SMC_RET1(handle, 0);
 
-	case GXBB_SM_JTAG_OFF:
-		scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1);
+	case AML_SM_JTAG_OFF:
+		aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1);
 		SMC_RET1(handle, 0);
 
 	default:
@@ -56,11 +56,11 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
 }
 
 DECLARE_RT_SVC(
-	gxbb_sip_handler,
+	aml_sip_handler,
 
 	OEN_SIP_START,
 	OEN_SIP_END,
 	SMC_TYPE_FAST,
 	NULL,
-	gxbb_sip_handler
+	aml_sip_handler
 );

plat/meson/gxbb/gxbb_thermal.c → plat/amlogic/common/aml_thermal.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stdint.h>
 
-#include "gxbb_private.h"
+#include "aml_private.h"
 
 static int32_t modules_initialized = -1;
 
 /*******************************************************************************
  * Unknown commands related to something thermal-related
  ******************************************************************************/
-void gxbb_thermal_unknown(void)
+void aml_thermal_unknown(void)
 {
 	uint16_t ret;
 
 	if (modules_initialized == -1) {
-		scpi_efuse_read(&ret, 0, 2);
+		aml_scpi_efuse_read(&ret, 0, 2);
 		modules_initialized = ret;
 	}
 
-	scpi_unknown_thermal(10, 2,  /* thermal */
-			     13, 1); /* thermalver */
+	aml_scpi_unknown_thermal(10, 2,  /* thermal */
+				 13, 1); /* thermalver */
 }

plat/meson/gxl/gxl_topology.c → plat/amlogic/common/aml_topology.c

 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,7 @@
 #include <platform_def.h>
 #include <stdint.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 /* The power domain tree descriptor */
 static unsigned char power_domain_tree_desc[] = {
@@ -49,5 +49,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
 	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
 		return -1;
 
-	return plat_gxbb_calc_core_pos(mpidr);
+	return plat_calc_core_pos(mpidr);
 }

plat/amlogic/common/include/aml_private.h

+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AML_PRIVATE_H
+#define AML_PRIVATE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Utility functions */
+unsigned int plat_calc_core_pos(u_register_t mpidr);
+void aml_console_init(void);
+void aml_setup_page_tables(void);
+
+/* MHU functions */
+void aml_mhu_secure_message_start(void);
+void aml_mhu_secure_message_send(uint32_t msg);
+uint32_t aml_mhu_secure_message_wait(void);
+void aml_mhu_secure_message_end(void);
+void aml_mhu_secure_init(void);
+
+/* SCPI functions */
+void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
+				  uint32_t cluster_state, uint32_t css_state);
+uint32_t aml_scpi_sys_power_state(uint64_t system_state);
+void aml_scpi_jtag_set_state(uint32_t state, uint8_t select);
+uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
+void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
+			      uint32_t arg2, uint32_t arg3);
+void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send);
+
+/* Peripherals */
+void aml_thermal_unknown(void);
+uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size);
+uint64_t aml_efuse_user_max(void);
+
+#endif /* AML_PRIVATE_H */

plat/meson/gxbb/include/plat_macros.S → plat/amlogic/common/include/plat_macros.S

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,7 +33,7 @@ spacer:
 
 	/* GICC registers */
 
-	mov_imm	x17, GXBB_GICC_BASE
+	mov_imm	x17, AML_GICC_BASE
 
 	adr	x6, gicc_regs
 	ldr	w8, [x17, #GICC_HPPIR]
@@ -43,7 +43,7 @@ spacer:
 
 	/* GICD registers */
 
-	mov_imm	x16, GXBB_GICD_BASE
+	mov_imm	x16, AML_GICD_BASE
 
 	add	x7, x16, #GICD_ISPENDR
 	adr	x4, gicd_pend_reg

plat/meson/gxbb/gxbb_bl31_setup.c → plat/amlogic/gxbb/gxbb_bl31_setup.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-
-#include <platform_def.h>
-
 #include <common/bl_common.h>
 #include <common/interrupt_props.h>
 #include <drivers/arm/gicv2.h>
 #include <lib/xlat_tables/xlat_mmu_helpers.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include "gxbb_private.h"
+#include "aml_private.h"
 
 /*
  * Placeholder variables for copying the arguments that have been passed to
@@ -67,13 +65,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	struct gxbb_bl31_param *from_bl2;
 
 	/* Initialize the console to provide early debug support */
-	gxbb_console_init();
+	aml_console_init();
 
 	/*
 	 * In debug builds, we pass a special value in 'arg1' to verify platform
 	 * parameters from BL2 to BL31. In release builds it's not used.
 	 */
-	assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
+	assert(arg1 == AML_BL31_PLAT_PARAM_VAL);
 
 	/* Check that params passed from BL2 are not NULL. */
 	from_bl2 = (struct gxbb_bl31_param *) arg0;
@@ -97,7 +95,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 void bl31_plat_arch_setup(void)
 {
-	gxbb_setup_page_tables();
+	aml_setup_page_tables();
 
 	enable_mmu_el3(0);
 }
@@ -127,20 +125,20 @@ static const interrupt_prop_t gxbb_interrupt_props[] = {
 };
 
 static const gicv2_driver_data_t gxbb_gic_data = {
-	.gicd_base = GXBB_GICD_BASE,
-	.gicc_base = GXBB_GICC_BASE,
+	.gicd_base = AML_GICD_BASE,
+	.gicc_base = AML_GICC_BASE,
 	.interrupt_props = gxbb_interrupt_props,
 	.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
 };
 
 void bl31_platform_setup(void)
 {
-	mhu_secure_init();
+	aml_mhu_secure_init();
 
 	gicv2_driver_init(&gxbb_gic_data);
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
 	gicv2_cpuif_enable();
 
-	gxbb_thermal_unknown();
+	aml_thermal_unknown();
 }

plat/meson/gxbb/gxbb_common.c → plat/amlogic/gxbb/gxbb_common.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <stdint.h>
-
-#include <platform_def.h>
-
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <common/ep_info.h>
-#include <drivers/meson/meson_console.h>
+#include <drivers/amlogic/meson_console.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
+#include <platform_def.h>
+#include <stdint.h>
 
 /*******************************************************************************
  * Platform memory map regions
  ******************************************************************************/
-#define MAP_NSDRAM0	MAP_REGION_FLAT(GXBB_NSDRAM0_BASE,		\
-					GXBB_NSDRAM0_SIZE,		\
+#define MAP_NSDRAM0	MAP_REGION_FLAT(AML_NSDRAM0_BASE,		\
+					AML_NSDRAM0_SIZE,		\
 					MT_MEMORY | MT_RW | MT_NS)
 
-#define MAP_NSDRAM1	MAP_REGION_FLAT(GXBB_NSDRAM1_BASE,		\
-					GXBB_NSDRAM1_SIZE,		\
+#define MAP_NSDRAM1	MAP_REGION_FLAT(AML_NSDRAM1_BASE,		\
+					AML_NSDRAM1_SIZE,		\
 					MT_MEMORY | MT_RW | MT_NS)
 
-#define MAP_SEC_DEVICE0	MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE,		\
-					GXBB_SEC_DEVICE0_SIZE,		\
+#define MAP_SEC_DEVICE0	MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE,		\
+					AML_SEC_DEVICE0_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE1	MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE,		\
-					GXBB_SEC_DEVICE1_SIZE,		\
+#define MAP_SEC_DEVICE1	MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE,		\
+					AML_SEC_DEVICE1_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_TZRAM	MAP_REGION_FLAT(GXBB_TZRAM_BASE,		\
-					GXBB_TZRAM_SIZE,		\
+#define MAP_TZRAM	MAP_REGION_FLAT(AML_TZRAM_BASE,			\
+					AML_TZRAM_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE2	MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE,		\
-					GXBB_SEC_DEVICE2_SIZE,		\
+#define MAP_SEC_DEVICE2	MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE,		\
+					AML_SEC_DEVICE2_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE3	MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE,		\
-					GXBB_SEC_DEVICE3_SIZE,		\
+#define MAP_SEC_DEVICE3	MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE,		\
+					AML_SEC_DEVICE3_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
 static const mmap_region_t gxbb_mmap[] = {
@@ -81,7 +79,7 @@ static const mmap_region_t gxbb_mmap[] = {
 /*******************************************************************************
  * Function that sets up the translation tables.
  ******************************************************************************/
-void gxbb_setup_page_tables(void)
+void aml_setup_page_tables(void)
 {
 #if IMAGE_BL31
 	const mmap_region_t gxbb_bl_mmap[] = {
@@ -107,11 +105,11 @@ void gxbb_setup_page_tables(void)
  ******************************************************************************/
 static console_meson_t gxbb_console;
 
-void gxbb_console_init(void)
+void aml_console_init(void)
 {
-	int rc = console_meson_register(GXBB_UART0_AO_BASE,
-					GXBB_UART0_AO_CLK_IN_HZ,
-					GXBB_UART_BAUDRATE,
+	int rc = console_meson_register(AML_UART0_AO_BASE,
+					AML_UART0_AO_CLK_IN_HZ,
+					AML_UART_BAUDRATE,
 					&gxbb_console);
 	if (rc == 0) {
 		/*
@@ -133,13 +131,13 @@ unsigned int plat_get_syscnt_freq2(void)
 {
 	uint32_t val;
 
-	val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+	val = mmio_read_32(AML_SYS_CPU_CFG7);
 	val &= 0xFDFFFFFF;
-	mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+	mmio_write_32(AML_SYS_CPU_CFG7, val);
 
-	val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+	val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
 	val &= 0xFFFFFE00;
-	mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+	mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
 
-	return GXBB_OSC24M_CLK_IN_HZ;
+	return AML_OSC24M_CLK_IN_HZ;
 }

plat/meson/gxbb/gxbb_def.h → plat/amlogic/gxbb/gxbb_def.h

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,54 +12,54 @@
 /*******************************************************************************
  * System oscillator
  ******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
+#define AML_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
 
 /*******************************************************************************
  * Memory regions
  ******************************************************************************/
-#define GXBB_NSDRAM0_BASE			UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE			UL(0x0F000000)
+#define AML_NSDRAM0_BASE			UL(0x01000000)
+#define AML_NSDRAM0_SIZE			UL(0x0F000000)
 
-#define GXBB_NSDRAM1_BASE			UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE			UL(0x00100000)
+#define AML_NSDRAM1_BASE			UL(0x10000000)
+#define AML_NSDRAM1_SIZE			UL(0x00100000)
 
 #define BL31_BASE				UL(0x10100000)
 #define BL31_SIZE				UL(0x000C0000)
 #define BL31_LIMIT				(BL31_BASE + BL31_SIZE)
 
 /* Shared memory used for SMC services */
-#define GXBB_SHARE_MEM_INPUT_BASE		UL(0x100FE000)
-#define GXBB_SHARE_MEM_OUTPUT_BASE		UL(0x100FF000)
+#define AML_SHARE_MEM_INPUT_BASE		UL(0x100FE000)
+#define AML_SHARE_MEM_OUTPUT_BASE		UL(0x100FF000)
 
-#define GXBB_SEC_DEVICE0_BASE			UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE			UL(0x09000000)
+#define AML_SEC_DEVICE0_BASE			UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE			UL(0x09000000)
 
-#define GXBB_SEC_DEVICE1_BASE			UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE			UL(0x00008000)
+#define AML_SEC_DEVICE1_BASE			UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE			UL(0x00008000)
 
-#define GXBB_TZRAM_BASE				UL(0xD9000000)
-#define GXBB_TZRAM_SIZE				UL(0x00014000)
+#define AML_TZRAM_BASE				UL(0xD9000000)
+#define AML_TZRAM_SIZE				UL(0x00014000)
 /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
 
 /* Mailboxes */
-#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
-#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
-#define GXBB_PSCI_MAILBOX_BASE			UL(0xD9013F00)
+#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
+#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
+#define AML_PSCI_MAILBOX_BASE			UL(0xD9013F00)
 
-#define GXBB_TZROM_BASE				UL(0xD9040000)
-#define GXBB_TZROM_SIZE				UL(0x00010000)
+#define AML_TZROM_BASE				UL(0xD9040000)
+#define AML_TZROM_SIZE				UL(0x00010000)
 
-#define GXBB_SEC_DEVICE2_BASE			UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE			UL(0x00200000)
+#define AML_SEC_DEVICE2_BASE			UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE			UL(0x00200000)
 
-#define GXBB_SEC_DEVICE3_BASE			UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE			UL(0x00200000)
+#define AML_SEC_DEVICE3_BASE			UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE			UL(0x00200000)
 
 /*******************************************************************************
  * GIC-400 and interrupt handling related constants
  ******************************************************************************/
-#define GXBB_GICD_BASE				UL(0xC4301000)
-#define GXBB_GICC_BASE				UL(0xC4302000)
+#define AML_GICD_BASE				UL(0xC4301000)
+#define AML_GICC_BASE				UL(0xC4302000)
 
 #define IRQ_SEC_PHY_TIMER			29
 
@@ -75,44 +75,44 @@
 /*******************************************************************************
  * UART definitions
  ******************************************************************************/
-#define GXBB_UART0_AO_BASE			UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ			GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE			U(115200)
+#define AML_UART0_AO_BASE			UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ			AML_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE			U(115200)
 
 /*******************************************************************************
  * Memory-mapped I/O Registers
  ******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL			UL(0xC81000B4)
+#define AML_AO_TIMESTAMP_CNTL			UL(0xC81000B4)
 
-#define GXBB_SYS_CPU_CFG7			UL(0xC8834664)
+#define AML_SYS_CPU_CFG7			UL(0xC8834664)
 
-#define GXBB_AO_RTI_STATUS_REG3			UL(0xDA10001C)
+#define AML_AO_RTI_STATUS_REG3			UL(0xDA10001C)
 
-#define GXBB_HIU_MAILBOX_SET_0			UL(0xDA83C404)
-#define GXBB_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
-#define GXBB_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
-#define GXBB_HIU_MAILBOX_SET_3			UL(0xDA83C428)
-#define GXBB_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
-#define GXBB_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
+#define AML_HIU_MAILBOX_SET_0			UL(0xDA83C404)
+#define AML_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
+#define AML_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
+#define AML_HIU_MAILBOX_SET_3			UL(0xDA83C428)
+#define AML_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
+#define AML_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
 
 /*******************************************************************************
  * System Monitor Call IDs and arguments
  ******************************************************************************/
-#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE	U(0x82000020)
-#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
+#define AML_SM_GET_SHARE_MEM_INPUT_BASE		U(0x82000020)
+#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
 
-#define GXBB_SM_EFUSE_READ			U(0x82000030)
-#define GXBB_SM_EFUSE_USER_MAX			U(0x82000033)
+#define AML_SM_EFUSE_READ			U(0x82000030)
+#define AML_SM_EFUSE_USER_MAX			U(0x82000033)
 
-#define GXBB_SM_JTAG_ON				U(0x82000040)
-#define GXBB_SM_JTAG_OFF			U(0x82000041)
+#define AML_SM_JTAG_ON				U(0x82000040)
+#define AML_SM_JTAG_OFF				U(0x82000041)
 
-#define GXBB_JTAG_STATE_ON			U(0)
-#define GXBB_JTAG_STATE_OFF			U(1)
+#define AML_JTAG_STATE_ON			U(0)
+#define AML_JTAG_STATE_OFF			U(1)
 
-#define GXBB_JTAG_M3_AO				U(0)
-#define GXBB_JTAG_M3_EE				U(1)
-#define GXBB_JTAG_A53_AO			U(2)
-#define GXBB_JTAG_A53_EE			U(3)
+#define AML_JTAG_M3_AO				U(0)
+#define AML_JTAG_M3_EE				U(1)
+#define AML_JTAG_A53_AO				U(2)
+#define AML_JTAG_A53_EE				U(3)
 
 #endif /* GXBB_DEF_H */

plat/meson/gxbb/gxbb_pm.c → plat/amlogic/gxbb/gxbb_pm.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
-#include <errno.h>
-
-#include <platform_def.h>
-
 #include <arch_helpers.h>
+#include <assert.h>
 #include <common/debug.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/console.h>
+#include <errno.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include "gxbb_private.h"
+#include "aml_private.h"
 
 #define SCPI_POWER_ON		0
 #define SCPI_POWER_RETENTION	1
@@ -31,8 +29,8 @@ static volatile uint32_t gxbb_cpu0_go;
 
 static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-	uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
+	unsigned int core = plat_calc_core_pos(mpidr);
+	uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
 
 	mmio_write_64(cpu_mailbox_addr, value);
 	flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t));
@@ -42,7 +40,7 @@ static void __dead2 gxbb_system_reset(void)
 {
 	INFO("BL31: PSCI_SYSTEM_RESET\n");
 
-	uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
+	uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
 
 	NOTICE("BL31: Reboot reason: 0x%x\n", status);
 
@@ -50,9 +48,9 @@ static void __dead2 gxbb_system_reset(void)
 
 	console_flush();
 
-	mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
+	mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
 
-	int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
+	int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
 
 	if (ret != 0) {
 		ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret);
@@ -69,7 +67,7 @@ static void __dead2 gxbb_system_off(void)
 {
 	INFO("BL31: PSCI_SYSTEM_OFF\n");
 
-	unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+	unsigned int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
 
 	if (ret != 0) {
 		ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret);
@@ -86,10 +84,10 @@ static void __dead2 gxbb_system_off(void)
 
 static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
 
 		gxbb_cpu0_go = 1;
@@ -103,8 +101,8 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 	}
 
 	gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint);
-	scpi_set_css_power_state(mpidr,
-				 SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
+	aml_scpi_set_css_power_state(mpidr,
+				     SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
 	dmbsy();
 	sev();
 
@@ -113,12 +111,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 
 static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+	unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
 	assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
 					PLAT_LOCAL_STATE_OFF);
 
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		gxbb_cpu0_go = 0;
 		flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go));
 		dsb();
@@ -132,8 +130,8 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	u_register_t mpidr = read_mpidr_el1();
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-	uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
+	unsigned int core = plat_calc_core_pos(mpidr);
+	uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4);
 
 	mmio_write_32(addr, 0xFFFFFFFF);
 	flush_dcache_range(addr, sizeof(uint32_t));
@@ -141,20 +139,20 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 	gicv2_cpuif_disable();
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU)
+	if (core == AML_PRIMARY_CPU)
 		return;
 
-	scpi_set_css_power_state(mpidr,
-				 SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
+	aml_scpi_set_css_power_state(mpidr,
+				     SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
 }
 
 static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
 						 *target_state)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+	unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: CPU0 entering wait loop...\n");
 
 		while (gxbb_cpu0_go == 0)

plat/meson/gxbb/include/platform_def.h → plat/amlogic/gxbb/include/platform_def.h

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 #define PLATFORM_LINKER_ARCH		aarch64
 
 /* Special value used to verify platform parameters from BL2 to BL31 */
-#define GXBB_BL31_PLAT_PARAM_VAL	ULL(0x0F1E2D3C4B5A6978)
+#define AML_BL31_PLAT_PARAM_VAL	ULL(0x0F1E2D3C4B5A6978)
 
 #define PLATFORM_STACK_SIZE		UL(0x1000)
 
@@ -25,7 +25,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define GXBB_PRIMARY_CPU		U(0)
+#define AML_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \