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Commit 9b350702 authored by Sandrine Bailleux's avatar Sandrine Bailleux Committed by TrustedFirmware Code Review
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Merge changes I94acd1bb,I0ece5226,I82d0a213,Ia4fc9456,Ic9fb7ed1 into integration 

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
  rcar_gen3: drivers: rpc: Modify PFC code
  rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
  rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr-a: Update E3 DDR setting
parents 3ce3ce07 363fb55a
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drivers/renesas/rcar/auth/auth_mod.c
View file @ 9b350702
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
......@@ -25,7 +25,7 @@ extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define MFISSOFTMDR (0xE6260600U)
#define MFISOFTMDR (0xE6260600U)
#define MODEMR_MD5_MASK (0x00000020U)
#define MODEMR_MD5_SHIFT (5U)
#define SOFTMD_BOOTMODE_MASK (0x00000001U)
......@@ -139,7 +139,7 @@ static int32_t normal_boot_verify(uint32_t a, uint32_t b, void *c)
void auth_mod_init(void)
{
#if RCAR_SECURE_BOOT
uint32_t soft_md = mmio_read_32(MFISSOFTMDR) & SOFTMD_BOOTMODE_MASK;
uint32_t soft_md = mmio_read_32(MFISOFTMDR) & SOFTMD_BOOTMODE_MASK;
uint32_t md = mmio_read_32(RST_MODEMR) & MODEMR_MD5_MASK;
uint32_t lcs, ret;
......
drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
View file @ 9b350702
......@@ -610,7 +610,7 @@ void pfc_init_d3(void)
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
pfc_reg_write(PFC_POCCTRL1, 0XFFFFFFFEU);
pfc_reg_write(PFC_POCCTRL2, 0XFFFFFFFEU);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
/* initialize LSI pin pull-up/down control */
......
drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
View file @ 9b350702
......@@ -122,7 +122,7 @@
#define GPSR5_SCK2_A BIT(7)
#define GPSR5_TX1 BIT(6)
#define GPSR5_RX1 BIT(5)
#define GPSR5_RTS0_TANS_A BIT(4)
#define GPSR5_RTS0_A BIT(4)
#define GPSR5_CTS0_A BIT(3)
#define GPSR5_TX0_A BIT(2)
#define GPSR5_RX0_A BIT(1)
......@@ -155,7 +155,7 @@
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define IOCTRL30_MASK (0x0007F000U)
#define POCCTRL0_MASK (0x0007F000U)
#define POC_SD3_DS_33V BIT(29)
#define POC_SD3_DAT7_33V BIT(28)
#define POC_SD3_DAT6_33V BIT(27)
......@@ -180,7 +180,7 @@
#define POC_SD0_CMD_33V BIT(1)
#define POC_SD0_CLK_33V BIT(0)
#define IOCTRL32_MASK (0xFFFFFFFEU)
#define POCCTRL2_MASK (0xFFFFFFFEU)
#define POC2_VREF_33V BIT(0)
#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
......@@ -561,7 +561,7 @@ void pfc_init_e3(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2_A
| GPSR5_RTS0_TANS_A
| GPSR5_RTS0_A
| GPSR5_CTS0_A);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
| GPSR6_SSI_SDATA6
......@@ -581,7 +581,7 @@ void pfc_init_e3(void)
/* initialize POC control */
reg = mmio_read_32(PFC_POCCTRL0);
reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
| POC_SD1_DAT2_33V
| POC_SD1_DAT1_33V
| POC_SD1_DAT0_33V
......@@ -594,9 +594,9 @@ void pfc_init_e3(void)
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
pfc_reg_write(PFC_POCCTRL0, reg);
reg = mmio_read_32(PFC_POCCTRL1);
reg = (reg & IOCTRL32_MASK);
pfc_reg_write(PFC_POCCTRL1, reg);
reg = mmio_read_32(PFC_POCCTRL2);
reg = (reg & POCCTRL2_MASK);
pfc_reg_write(PFC_POCCTRL2, reg);
/* initialize LSI pin pull-up/down control */
pfc_reg_write(PFC_PUD0, 0xFDF80000U);
......
drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
View file @ 9b350702
......@@ -119,11 +119,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
......@@ -160,8 +160,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
......@@ -323,8 +321,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
......@@ -673,7 +671,6 @@ void pfc_init_h3_v1(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
......@@ -829,11 +826,11 @@ void pfc_init_h3_v1(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
......@@ -856,9 +853,7 @@ void pfc_init_h3_v1(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
......@@ -996,8 +991,8 @@ void pfc_init_h3_v1(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
......@@ -1153,6 +1148,7 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
......@@ -1162,6 +1158,7 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
......@@ -1182,4 +1179,5 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
View file @ 9b350702
......@@ -121,11 +121,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
......@@ -162,8 +162,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
......@@ -325,8 +323,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
......@@ -697,7 +695,6 @@ void pfc_init_h3_v2(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
......@@ -862,11 +859,11 @@ void pfc_init_h3_v2(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
......@@ -889,9 +886,7 @@ void pfc_init_h3_v2(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
......@@ -1029,8 +1024,8 @@ void pfc_init_h3_v2(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
......@@ -1186,6 +1181,7 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
......@@ -1195,6 +1191,7 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
......@@ -1215,4 +1212,5 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
View file @ 9b350702
......@@ -124,11 +124,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
......@@ -165,8 +165,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
......@@ -328,8 +326,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
......@@ -792,7 +790,6 @@ void pfc_init_m3(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
......@@ -957,11 +954,11 @@ void pfc_init_m3(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
......@@ -984,9 +981,7 @@ void pfc_init_m3(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
......@@ -1124,8 +1119,8 @@ void pfc_init_m3(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
......@@ -1281,6 +1276,7 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
......@@ -1290,6 +1286,7 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
......@@ -1310,4 +1307,5 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
View file @ 9b350702
......@@ -123,11 +123,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
......@@ -164,8 +164,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
......@@ -327,8 +325,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
......@@ -699,7 +697,6 @@ void pfc_init_m3n(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
......@@ -864,11 +861,11 @@ void pfc_init_m3n(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
......@@ -891,9 +888,7 @@ void pfc_init_m3n(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
......@@ -1031,8 +1026,8 @@ void pfc_init_m3n(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
......@@ -1188,6 +1183,7 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
......@@ -1197,6 +1193,7 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
......@@ -1217,4 +1214,5 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
View file @ 9b350702
......@@ -709,7 +709,7 @@ void pfc_init_v3m(void)
| IOCTRL31_POC_VI0_DATA7
| IOCTRL31_POC_VI0_DATA6);
pfc_reg_write(PFC_POCCTRL1, 0x00000000);
pfc_reg_write(PFC_POCCTRL2, 0x00000000);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
......
drivers/renesas/rcar/pfc/pfc_regs.h
View file @ 9b350702
......@@ -206,7 +206,7 @@
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
#define PFC_POCCTRL1 (PFC_BASE + 0x0388U)
#define PFC_POCCTRL2 (PFC_BASE + 0x0388U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
......
drivers/renesas/rcar/rpc/rpc_driver.c
View file @ 9b350702
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -11,11 +11,15 @@
#include <lib/mmio.h>
#include "cpg_registers.h"
#include "rpc_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "rpc_registers.h"
#define MSTPSR9_RPC_BIT (0x00020000U)
#define RPC_CMNCR_MD_BIT (0x80000000U)
#define RPC_PHYCNT_CAL BIT(31)
#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
#define RPC_PHYCNT_STRTIM (0x7 << 15UL)
static void rpc_enable(void)
{
......@@ -25,8 +29,25 @@ static void rpc_enable(void)
static void rpc_setup(void)
{
uint32_t product, cut, reg, phy_strtim;
if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
else
phy_strtim = RPC_PHYCNT_STRTIM;
reg = mmio_read_32(RPC_PHYCNT);
reg &= ~RPC_PHYCNT_STRTIM;
reg |= phy_strtim;
mmio_write_32(RPC_PHYCNT, reg);
reg |= RPC_PHYCNT_CAL;
mmio_write_32(RPC_PHYCNT, reg);
}
void rcar_rpc_init(void)
......
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View file @ 9b350702
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -100,12 +100,8 @@ uint32_t init_ddr(void)
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */
#else
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
......@@ -894,10 +890,6 @@ uint32_t recovery_from_backup_mode(void)
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
#else
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#endif
......
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
View file @ 9b350702
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -9,7 +9,7 @@
#include <stdint.h>
#define RCAR_E3_DDR_VERSION "rev.0.11"
#define RCAR_E3_DDR_VERSION "rev.0.12"
#ifdef ddr_qos_init_setting
#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View file @ 9b350702
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 20
#define BOARDNUM 22
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
......@@ -1425,6 +1425,108 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
}
}
},
/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0x04},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0xff},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0xff},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
......@@ -1522,10 +1624,10 @@ static const uint32_t TermcodeBySample[20][3] = {
#define GPIO_INDT5 0xE605500CU
#define GPIO_INDT6 0xE605540CU
#define BIT25 (1<<25)
#define BIT22 (1<<22)
#define BIT15 (1<<15)
#define BIT0 (1)
#define BIT25 BIT(25)
#define BIT22 BIT(22)
#define BIT15 BIT(15)
#define BIT0 BIT(0)
#define GPIO_GPSR6 (0xE6060118U)
#if (RCAR_GEN3_ULCB == 0)
......@@ -1673,7 +1775,7 @@ static uint32_t _board_judge(void)
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
/* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
brd = 19;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View file @ 9b350702
......@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.35"
#define RCAR_DDR_VERSION "rev.0.36"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
......@@ -144,11 +144,11 @@
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
#define DBSC_DBDFICUPDCNF 0xE679052CU
#define DBSC_INITCOMP(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_INITCOMP_0 0xE6790600U
#define DBSC_INITCOMP_1 0xE6790640U
#define DBSC_INITCOMP_2 0xE6790680U
#define DBSC_INITCOMP_3 0xE67906C0U
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_DBDFISTAT_0 0xE6790600U
#define DBSC_DBDFISTAT_1 0xE6790640U
#define DBSC_DBDFISTAT_2 0xE6790680U
#define DBSC_DBDFISTAT_3 0xE67906C0U
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
#define DBSC_DBDFICNT_0 0xE6790604U
......
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
View file @ 9b350702
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -1182,7 +1182,7 @@
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
const static uint32_t DDR_REGDEF_TBL[4][1173] = {
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
{
/*0000*/ 0xffffffffU,
/*0001*/ 0xffffffffU,
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
View file @ 9b350702
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......
plat/renesas/rcar/include/rcar_version.h
View file @ 9b350702
......@@ -9,7 +9,7 @@
#include <arch_helpers.h>
#define VERSION_OF_RENESAS "2.0.3"
#define VERSION_OF_RENESAS "2.0.4"
#define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
......
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