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adam.huang
Arm Trusted Firmware
Commits
9d068f66
Unverified
Commit
9d068f66
authored
6 years ago
by
Antonio Niño Díaz
Committed by
GitHub
6 years ago
Browse files
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Plain Diff
Merge pull request #1673 from antonio-nino-diaz-arm/an/headers
Standardise header guards across codebase
parents
f5ae1b0e
c3cf06f1
master
v2.5
v2.5-rc1
v2.5-rc0
v2.4
v2.4-rc2
v2.4-rc1
v2.4-rc0
v2.3
v2.3-rc2
v2.3-rc1
v2.3-rc0
v2.2
v2.2-rc2
v2.2-rc1
v2.2-rc0
v2.1
v2.1-rc1
v2.1-rc0
arm_cca_v0.2
arm_cca_v0.1
No related merge requests found
Changes
508
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20 changed files
include/lib/cassert.h
+3
-3
include/lib/cassert.h
include/lib/coreboot.h
+3
-3
include/lib/coreboot.h
include/lib/cpus/aarch32/aem_generic.h
+3
-3
include/lib/cpus/aarch32/aem_generic.h
include/lib/cpus/aarch32/cortex_a12.h
+3
-3
include/lib/cpus/aarch32/cortex_a12.h
include/lib/cpus/aarch32/cortex_a15.h
+3
-3
include/lib/cpus/aarch32/cortex_a15.h
include/lib/cpus/aarch32/cortex_a17.h
+3
-3
include/lib/cpus/aarch32/cortex_a17.h
include/lib/cpus/aarch32/cortex_a32.h
+3
-3
include/lib/cpus/aarch32/cortex_a32.h
include/lib/cpus/aarch32/cortex_a5.h
+3
-3
include/lib/cpus/aarch32/cortex_a5.h
include/lib/cpus/aarch32/cortex_a53.h
+3
-3
include/lib/cpus/aarch32/cortex_a53.h
include/lib/cpus/aarch32/cortex_a57.h
+4
-3
include/lib/cpus/aarch32/cortex_a57.h
include/lib/cpus/aarch32/cortex_a7.h
+3
-3
include/lib/cpus/aarch32/cortex_a7.h
include/lib/cpus/aarch32/cortex_a72.h
+3
-3
include/lib/cpus/aarch32/cortex_a72.h
include/lib/cpus/aarch32/cortex_a9.h
+3
-3
include/lib/cpus/aarch32/cortex_a9.h
include/lib/cpus/aarch32/cpu_macros.S
+3
-3
include/lib/cpus/aarch32/cpu_macros.S
include/lib/cpus/aarch64/aem_generic.h
+3
-4
include/lib/cpus/aarch64/aem_generic.h
include/lib/cpus/aarch64/cortex_a35.h
+3
-3
include/lib/cpus/aarch64/cortex_a35.h
include/lib/cpus/aarch64/cortex_a53.h
+3
-3
include/lib/cpus/aarch64/cortex_a53.h
include/lib/cpus/aarch64/cortex_a55.h
+3
-3
include/lib/cpus/aarch64/cortex_a55.h
include/lib/cpus/aarch64/cortex_a57.h
+3
-3
include/lib/cpus/aarch64/cortex_a57.h
include/lib/cpus/aarch64/cortex_a72.h
+3
-3
include/lib/cpus/aarch64/cortex_a72.h
with
61 additions
and
61 deletions
+61
-61
include/lib/cassert.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CASSERT_H
__
#define
__
CASSERT_H
__
#ifndef CASSERT_H
#define CASSERT_H
#include <cdefs.h>
...
...
@@ -20,4 +20,4 @@
#define CASSERT(cond, msg) \
typedef char msg[(cond) ? 1 : -1] __unused
#endif
/*
__
CASSERT_H
__
*/
#endif
/* CASSERT_H */
This diff is collapsed.
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include/lib/coreboot.h
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9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
COREBOOT_H
__
#define
__
COREBOOT_H
__
#ifndef COREBOOT_H
#define COREBOOT_H
#include <stdint.h>
...
...
@@ -21,4 +21,4 @@ extern coreboot_serial_t coreboot_serial;
void
coreboot_table_setup
(
void
*
base
);
#endif
/*
__
COREBOOT_H
__
*/
#endif
/* COREBOOT_H */
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include/lib/cpus/aarch32/aem_generic.h
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9d068f66
...
...
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
AEM_GENERIC_H
__
#define
__
AEM_GENERIC_H
__
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
/* BASE AEM midr for revision 0 */
#define BASE_AEM_MIDR 0x410FD0F0
#endif
/*
__
AEM_GENERIC_H
__
*/
#endif
/* AEM_GENERIC_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a12.h
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9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A12_H
__
#define
__
CORTEX_A12_H
__
#ifndef CORTEX_A12_H
#define CORTEX_A12_H
/*******************************************************************************
* Cortex-A12 midr with version/revision set to 0
...
...
@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A12_ACTLR_SMP_BIT (1 << 6)
#endif
/*
__
CORTEX_A12_H
__
*/
#endif
/* CORTEX_A12_H */
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include/lib/cpus/aarch32/cortex_a15.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A15_H
__
#define
__
CORTEX_A15_H
__
#ifndef CORTEX_A15_H
#define CORTEX_A15_H
/*******************************************************************************
* Cortex-A15 midr with version/revision set to 0
...
...
@@ -18,4 +18,4 @@
#define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0)
#define CORTEX_A15_ACTLR_SMP_BIT (1 << 6)
#endif
/*
__
CORTEX_A15_H
__
*/
#endif
/* CORTEX_A15_H */
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include/lib/cpus/aarch32/cortex_a17.h
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9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A17_H
__
#define
__
CORTEX_A17_H
__
#ifndef CORTEX_A17_H
#define CORTEX_A17_H
/*******************************************************************************
* Cortex-A17 midr with version/revision set to 0
...
...
@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A17_ACTLR_SMP_BIT (1 << 6)
#endif
/*
__
CORTEX_A17_H
__
*/
#endif
/* CORTEX_A17_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a32.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A32_H
__
#define
__
CORTEX_A32_H
__
#ifndef CORTEX_A32_H
#define CORTEX_A32_H
/* Cortex-A32 Main ID register for revision 0 */
#define CORTEX_A32_MIDR 0x410FD010
...
...
@@ -17,4 +17,4 @@
#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6)
#endif
/*
__
CORTEX_A32_H
__
*/
#endif
/* CORTEX_A32_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a5.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A5_H
__
#define
__
CORTEX_A5_H
__
#ifndef CORTEX_A5_H
#define CORTEX_A5_H
/*******************************************************************************
* Cortex-A8 midr with version/revision set to 0
...
...
@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6)
#endif
/*
__
CORTEX_A5_H
__
*/
#endif
/* CORTEX_A5_H */
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include/lib/cpus/aarch32/cortex_a53.h
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9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A53_H
__
#define
__
CORTEX_A53_H
__
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR 0x410FD030
...
...
@@ -67,4 +67,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR p15, 3, c15
#endif
/*
__
CORTEX_A53_H
__
*/
#endif
/* CORTEX_A53_H */
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include/lib/cpus/aarch32/cortex_a57.h
View file @
9d068f66
...
...
@@ -4,8 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#ifndef CORTEX_A57_H
#define CORTEX_A57_H
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
...
...
@@ -79,4 +80,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR p15, 3, c15
#endif
/*
__
CORTEX_A57_H
__
*/
#endif
/* CORTEX_A57_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a7.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A7_H
__
#define
__
CORTEX_A7_H
__
#ifndef CORTEX_A7_H
#define CORTEX_A7_H
/*******************************************************************************
* Cortex-A7 midr with version/revision set to 0
...
...
@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A7_ACTLR_SMP_BIT (1 << 6)
#endif
/*
__
CORTEX_A7_H
__
*/
#endif
/* CORTEX_A7_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a72.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A72_H
__
#define
__
CORTEX_A72_H
__
#ifndef CORTEX_A72_H
#define CORTEX_A72_H
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
...
...
@@ -54,4 +54,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR p15, 3, c15
#endif
/*
__
CORTEX_A72_H
__
*/
#endif
/* CORTEX_A72_H */
This diff is collapsed.
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include/lib/cpus/aarch32/cortex_a9.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A9_H
__
#define
__
CORTEX_A9_H
__
#ifndef CORTEX_A9_H
#define CORTEX_A9_H
/*******************************************************************************
* Cortex-A9 midr with version/revision set to 0
...
...
@@ -28,4 +28,4 @@
DEFINE_COPROCR_RW_FUNCS
(
pcr
,
PCR
)
#endif
#endif
/*
__
CORTEX_A9_H
__
*/
#endif
/* CORTEX_A9_H */
This diff is collapsed.
Click to expand it.
include/lib/cpus/aarch32/cpu_macros.S
View file @
9d068f66
...
...
@@ -3,8 +3,8 @@
*
*
SPDX
-
License
-
Identifier
:
BSD
-
3
-
Clause
*/
#ifndef
__
CPU_MACROS_S
__
#define
__
CPU_MACROS_S
__
#ifndef CPU_MACROS_S
#define CPU_MACROS_S
#include <arch.h>
#include <errata_report.h>
...
...
@@ -227,4 +227,4 @@
beq
\
_label
.
endm
#endif /*
__
CPU_MACROS_S
__
*/
#endif /* CPU_MACROS_S */
This diff is collapsed.
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include/lib/cpus/aarch64/aem_generic.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
AEM_GENERIC_H
__
#define
__
AEM_GENERIC_H
__
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
/* BASE AEM midr for revision 0 */
#define BASE_AEM_MIDR 0x410FD0F0
...
...
@@ -13,5 +13,4 @@
/* Foundation AEM midr for revision 0 */
#define FOUNDATION_AEM_MIDR 0x410FD000
#endif
/* __AEM_GENERIC_H__ */
#endif
/* AEM_GENERIC_H */
This diff is collapsed.
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include/lib/cpus/aarch64/cortex_a35.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A35_H
__
#define
__
CORTEX_A35_H
__
#ifndef CORTEX_A35_H
#define CORTEX_A35_H
/* Cortex-A35 Main ID register for revision 0 */
#define CORTEX_A35_MIDR 0x410FD040
...
...
@@ -17,4 +17,4 @@
#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6)
#endif
/*
__
CORTEX_A35_H
__
*/
#endif
/* CORTEX_A35_H */
This diff is collapsed.
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include/lib/cpus/aarch64/cortex_a53.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A53_H
__
#define
__
CORTEX_A53_H
__
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR U(0x410FD030)
...
...
@@ -71,4 +71,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
#endif
/*
__
CORTEX_A53_H
__
*/
#endif
/* CORTEX_A53_H */
This diff is collapsed.
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include/lib/cpus/aarch64/cortex_a55.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A55_H
__
#define
__
CORTEX_A55_H
__
#ifndef CORTEX_A55_H
#define CORTEX_A55_H
/* Cortex-A55 MIDR for revision 0 */
#define CORTEX_A55_MIDR 0x410fd050
...
...
@@ -19,4 +19,4 @@
/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1
#endif
/*
__
CORTEX_A55_H
__
*/
#endif
/* CORTEX_A55_H */
This diff is collapsed.
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include/lib/cpus/aarch64/cortex_a57.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A57_H
__
#define
__
CORTEX_A57_H
__
#ifndef CORTEX_A57_H
#define CORTEX_A57_H
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
...
...
@@ -81,4 +81,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
#endif
/*
__
CORTEX_A57_H
__
*/
#endif
/* CORTEX_A57_H */
This diff is collapsed.
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include/lib/cpus/aarch64/cortex_a72.h
View file @
9d068f66
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CORTEX_A72_H
__
#define
__
CORTEX_A72_H
__
#ifndef CORTEX_A72_H
#define CORTEX_A72_H
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
...
...
@@ -61,4 +61,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#endif
/*
__
CORTEX_A72_H
__
*/
#endif
/* CORTEX_A72_H */
This diff is collapsed.
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