Unverified Commit 9d068f66 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
Browse files

Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase
Showing with 61 additions and 61 deletions
+61 -61
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CASSERT_H__
#define __CASSERT_H__
#ifndef CASSERT_H
#define CASSERT_H
#include <cdefs.h>
......@@ -20,4 +20,4 @@
#define CASSERT(cond, msg) \
typedef char msg[(cond) ? 1 : -1] __unused
#endif /* __CASSERT_H__ */
#endif /* CASSERT_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __COREBOOT_H__
#define __COREBOOT_H__
#ifndef COREBOOT_H
#define COREBOOT_H
#include <stdint.h>
......@@ -21,4 +21,4 @@ extern coreboot_serial_t coreboot_serial;
void coreboot_table_setup(void *base);
#endif /* __COREBOOT_H__ */
#endif /* COREBOOT_H */
......@@ -4,10 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __AEM_GENERIC_H__
#define __AEM_GENERIC_H__
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
/* BASE AEM midr for revision 0 */
#define BASE_AEM_MIDR 0x410FD0F0
#endif /* __AEM_GENERIC_H__ */
#endif /* AEM_GENERIC_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A12_H__
#define __CORTEX_A12_H__
#ifndef CORTEX_A12_H
#define CORTEX_A12_H
/*******************************************************************************
* Cortex-A12 midr with version/revision set to 0
......@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A12_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A12_H__ */
#endif /* CORTEX_A12_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A15_H__
#define __CORTEX_A15_H__
#ifndef CORTEX_A15_H
#define CORTEX_A15_H
/*******************************************************************************
* Cortex-A15 midr with version/revision set to 0
......@@ -18,4 +18,4 @@
#define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0)
#define CORTEX_A15_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A15_H__ */
#endif /* CORTEX_A15_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A17_H__
#define __CORTEX_A17_H__
#ifndef CORTEX_A17_H
#define CORTEX_A17_H
/*******************************************************************************
* Cortex-A17 midr with version/revision set to 0
......@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A17_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A17_H__ */
#endif /* CORTEX_A17_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A32_H__
#define __CORTEX_A32_H__
#ifndef CORTEX_A32_H
#define CORTEX_A32_H
/* Cortex-A32 Main ID register for revision 0 */
#define CORTEX_A32_MIDR 0x410FD010
......@@ -17,4 +17,4 @@
#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6)
#endif /* __CORTEX_A32_H__ */
#endif /* CORTEX_A32_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A5_H__
#define __CORTEX_A5_H__
#ifndef CORTEX_A5_H
#define CORTEX_A5_H
/*******************************************************************************
* Cortex-A8 midr with version/revision set to 0
......@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A5_H__ */
#endif /* CORTEX_A5_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A53_H__
#define __CORTEX_A53_H__
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR 0x410FD030
......@@ -67,4 +67,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A53_H__ */
#endif /* CORTEX_A53_H */
......@@ -4,8 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#ifndef CORTEX_A57_H
#define CORTEX_A57_H
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
......@@ -79,4 +80,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A57_H__ */
#endif /* CORTEX_A57_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A7_H__
#define __CORTEX_A7_H__
#ifndef CORTEX_A7_H
#define CORTEX_A7_H
/*******************************************************************************
* Cortex-A7 midr with version/revision set to 0
......@@ -17,4 +17,4 @@
******************************************************************************/
#define CORTEX_A7_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A7_H__ */
#endif /* CORTEX_A7_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#ifndef CORTEX_A72_H
#define CORTEX_A72_H
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
......@@ -54,4 +54,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A72_H__ */
#endif /* CORTEX_A72_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A9_H__
#define __CORTEX_A9_H__
#ifndef CORTEX_A9_H
#define CORTEX_A9_H
/*******************************************************************************
* Cortex-A9 midr with version/revision set to 0
......@@ -28,4 +28,4 @@
DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
#endif
#endif /* __CORTEX_A9_H__ */
#endif /* CORTEX_A9_H */
......@@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CPU_MACROS_S__
#define __CPU_MACROS_S__
#ifndef CPU_MACROS_S
#define CPU_MACROS_S
#include <arch.h>
#include <errata_report.h>
......@@ -227,4 +227,4 @@
beq \_label
.endm
#endif /* __CPU_MACROS_S__ */
#endif /* CPU_MACROS_S */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __AEM_GENERIC_H__
#define __AEM_GENERIC_H__
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
/* BASE AEM midr for revision 0 */
#define BASE_AEM_MIDR 0x410FD0F0
......@@ -13,5 +13,4 @@
/* Foundation AEM midr for revision 0 */
#define FOUNDATION_AEM_MIDR 0x410FD000
#endif /* __AEM_GENERIC_H__ */
#endif /* AEM_GENERIC_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A35_H__
#define __CORTEX_A35_H__
#ifndef CORTEX_A35_H
#define CORTEX_A35_H
/* Cortex-A35 Main ID register for revision 0 */
#define CORTEX_A35_MIDR 0x410FD040
......@@ -17,4 +17,4 @@
#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6)
#endif /* __CORTEX_A35_H__ */
#endif /* CORTEX_A35_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A53_H__
#define __CORTEX_A53_H__
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR U(0x410FD030)
......@@ -71,4 +71,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A53_H__ */
#endif /* CORTEX_A53_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A55_H__
#define __CORTEX_A55_H__
#ifndef CORTEX_A55_H
#define CORTEX_A55_H
/* Cortex-A55 MIDR for revision 0 */
#define CORTEX_A55_MIDR 0x410fd050
......@@ -19,4 +19,4 @@
/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1
#endif /* __CORTEX_A55_H__ */
#endif /* CORTEX_A55_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#ifndef CORTEX_A57_H
#define CORTEX_A57_H
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
......@@ -81,4 +81,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A57_H__ */
#endif /* CORTEX_A57_H */
......@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#ifndef CORTEX_A72_H
#define CORTEX_A72_H
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
......@@ -61,4 +61,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A72_H__ */
#endif /* CORTEX_A72_H */
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