Commit 9e4afb02 authored by Justin Chadwell's avatar Justin Chadwell
Browse files

Update layerscape platform to not rely on undefined overflow behaviour



This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib63ef6e2e4616dd56828bfd3800d5fe2df109934
Signed-off-by: default avatarJustin Chadwell <justin.chadwell@arm.com>
parent 36cfbf3c
...@@ -66,12 +66,12 @@ static void ls1043_reset_core(int core_pos) ...@@ -66,12 +66,12 @@ static void ls1043_reset_core(int core_pos)
dsb(); dsb();
/* enable core soft reset */ /* enable core soft reset */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET, mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
htobe32(1 << 31)); htobe32(1U << 31));
dsb(); dsb();
isb(); isb();
/* reset core */ /* reset core */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET + mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
core_pos * 4, htobe32(1 << 31)); core_pos * 4, htobe32(1U << 31));
mdelay(10); mdelay(10);
} }
......
...@@ -35,7 +35,7 @@ void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) ...@@ -35,7 +35,7 @@ void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
soc_dev_id == (SVR_LS1043AE << 8)) && soc_dev_id == (SVR_LS1043AE << 8)) &&
((val & 0xff) == REV1_1)) { ((val & 0xff) == REV1_1)) {
val = be32toh(mmio_read_32((uintptr_t)gic_align)); val = be32toh(mmio_read_32((uintptr_t)gic_align));
if (val & (1 << GIC_ADDR_BIT)) { if (val & (1U << GIC_ADDR_BIT)) {
*gicc_base = GICC_BASE; *gicc_base = GICC_BASE;
*gicd_base = GICD_BASE; *gicd_base = GICD_BASE;
} else { } else {
......
...@@ -9,9 +9,9 @@ ...@@ -9,9 +9,9 @@
#include <stdint.h> #include <stdint.h>
#define SVR_WO_E 0xFFFFFE #define SVR_WO_E 0xFFFFFEu
#define SVR_LS1043A 0x879204 #define SVR_LS1043A 0x879204u
#define SVR_LS1043AE 0x879200 #define SVR_LS1043AE 0x879200u
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base); void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
......
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