rockchip: disable watchdog during suspend

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend time, it just switched from the
24M to the 32k clock. That meant that the WDT would fire if you slept for
long enough. In other word, the watchdog timer over count will increase to
750 (24*1000/32) times.
The RK3399 HW watchdog interval is 21 seconds. When machine enters the
suspend, the watchdog will reset the system after 35.7 (750/21) hours.

BUG=chrome-os-partner:59257
TEST=daisydog checked and set value, powerd_dbus_suspend to verify.

Change-Id: I88bb2a05b7d67d5ffd292f9d05d033ae9a6a3593
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

plat/rockchip/rk3399/drivers/pmu/pmu.c

@@ -1144,6 +1144,8 @@ static int sys_pwr_domain_suspend(void)
 	}
 	mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
 
+	secure_watchdog_disable();
+
 	/*
 	 * Disabling PLLs/PWM/DVFS is approaching WFI which is
 	 * the last steps in suspend.
@@ -1173,6 +1175,8 @@ static int sys_pwr_domain_resume(void)
 	enable_dvfs_plls();
 	plls_resume_finish();
 
+	secure_watchdog_restore();
+
 	/* restore clk_ddrc_bpll_src_en gate */
 	mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
 		      BITS_WITH_WMASK(clk_ddrc_save, 0xff, 0));

plat/rockchip/rk3399/drivers/soc/soc.c

@@ -192,6 +192,28 @@ static void dma_secure_cfg(uint32_t secure)
 /* pll suspend */
 struct deepsleep_data_s slp_data;
 
+void secure_watchdog_disable(void)
+{
+	slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3));
+
+	/* disable CA53 wdt pclk */
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
+		      BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK,
+				      PCLK_WDT_CA53_GATE_SHIFT));
+	/* disable CM0 wdt pclk */
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
+		      BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK,
+				      PCLK_WDT_CM0_GATE_SHIFT));
+}
+
+void secure_watchdog_restore(void)
+{
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
+		      slp_data.sgrf_con[3] |
+		      WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
+		      WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
+}
+
 static void pll_suspend_prepare(uint32_t pll_id)
 {
 	int i;

plat/rockchip/rk3399/drivers/soc/soc.h

@@ -73,6 +73,7 @@
 #define REG_SOC_WMSK			0xffff0000
 #define CLK_GATE_MASK			0x01
 
+#define SGRF_SOC_COUNT		0x17
 #define PMUCRU_GATE_COUNT	0x03
 #define CRU_GATE_COUNT		0x23
 #define PMUCRU_GATE_CON(n)	(0x100 + (n) * 4)
@@ -111,6 +112,7 @@ struct deepsleep_data_s {
 	uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
 	uint32_t cru_gate_con[CRU_GATE_COUNT];
 	uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
+	uint32_t sgrf_con[SGRF_SOC_COUNT];
 };
 
 /**************************************************
@@ -172,6 +174,20 @@ struct deepsleep_data_s {
 #define TIMER_FMODE		(0x0 << 1)
 #define TIMER_RMODE		(0x1 << 1)
 
+/**************************************************
+ * secure WDT
+ **************************************************/
+#define WDT_CM0_EN		0x0
+#define WDT_CM0_DIS		0x1
+#define WDT_CA53_EN		0x0
+#define WDT_CA53_DIS		0x1
+
+#define PCLK_WDT_CA53_GATE_SHIFT	8
+#define PCLK_WDT_CM0_GATE_SHIFT		10
+
+#define WDT_CA53_1BIT_MASK	0x1
+#define WDT_CM0_1BIT_MASK	0x1
+
 /**************************************************
  * cru reg, offset
  **************************************************/
@@ -330,6 +346,8 @@ static inline void pmu_sgrf_rst_hld(void)
 
 /* funciton*/
 void __dead2 soc_global_soft_reset(void);
+void secure_watchdog_disable();
+void secure_watchdog_restore();
 void plls_suspend_prepare(void);
 void disable_dvfs_plls(void);
 void disable_nodvfs_plls(void);