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Commit a391d494 authored by Pritesh Raithatha's avatar Pritesh Raithatha Committed by Varun Wadekar
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Tegra: smmu: remove context save sequence 



SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
parent e9044480
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Inline Side-by-side
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
View file @ a391d494
......@@ -21,6 +21,7 @@
#include <smmu.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/* Video Memory base and size (live values) */
static uint64_t video_mem_base;
......@@ -223,6 +224,58 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
mce_update_gsc_tzram();
}
/*
* Save MC settings before "System Suspend" to TZDRAM
*/
void tegra_mc_save_context(uint64_t mc_ctx_addr)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i, num_entries = 0;
mc_regs_t *mc_ctx_regs;
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
/* get MC context table */
mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx();
assert(mc_ctx_regs != NULL);
/*
* mc_ctx_regs[0].val contains the size of the context table minus
* the last entry. Sanity check the table size before we start with
* the context save operation.
*/
while (mc_ctx_regs[num_entries].reg != 0xFFFFFFFFU) {
num_entries++;
}
/* panic if the sizes do not match */
if (num_entries != mc_ctx_regs[0].val) {
ERROR("MC context size mismatch!");
panic();
}
/* save MC register values */
for (i = 1U; i < num_entries; i++) {
mc_ctx_regs[i].val = mmio_read_32(mc_ctx_regs[i].reg);
}
/* increment by 1 to take care of the last entry */
num_entries++;
/* Save MC config settings */
(void)memcpy((void *)mc_ctx_addr, mc_ctx_regs,
sizeof(mc_regs_t) * num_entries);
/* save the MC table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO,
(uint32_t)mc_ctx_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI,
(uint32_t)(mc_ctx_addr >> 32));
}
static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
uint64_t size_in_bytes)
{
......
plat/nvidia/tegra/common/drivers/smmu/smmu.c
View file @ a391d494
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -71,67 +72,8 @@ static void tegra_smmu_write_32(uint32_t smmu_id,
#endif
}
/*
* Save SMMU settings before "System Suspend" to TZDRAM
*/
void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
{
uint32_t i, num_entries = 0;
smmu_regs_t *smmu_ctx_regs;
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
uint32_t reg_id1, pgshift, cb_size;
/* sanity check SMMU settings c*/
reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
cb_size = ((uint32_t)2 << pgshift) * \
((uint32_t)1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1U));
assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
/* get SMMU context table */
smmu_ctx_regs = plat_get_smmu_ctx();
assert(smmu_ctx_regs != NULL);
/*
* smmu_ctx_regs[0].val contains the size of the context table minus
* the last entry. Sanity check the table size before we start with
* the context save operation.
*/
while ((smmu_ctx_regs[num_entries].reg != 0xFFFFFFFFU)) {
num_entries++;
}
/* panic if the sizes do not match */
if (num_entries != smmu_ctx_regs[0].val) {
ERROR("SMMU context size mismatch!");
panic();
}
/* save SMMU register values */
for (i = 1U; i < num_entries; i++) {
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
}
/* increment by 1 to take care of the last entry */
num_entries++;
/* Save SMMU config settings */
(void)memcpy16((uint8_t *)smmu_ctx_addr, (uint8_t *)smmu_ctx_regs,
(sizeof(smmu_regs_t) * num_entries));
/* save the SMMU table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_LO,
(uint32_t)smmu_ctx_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_HI,
(uint32_t)(smmu_ctx_addr >> 32));
}
#define SMMU_NUM_CONTEXTS 64
#define SMMU_CONTEXT_BANK_MAX_IDX 64
#define SMMU_NUM_CONTEXTS 64U
#define SMMU_CONTEXT_BANK_MAX_IDX 64U
/*
* Init SMMU during boot or "System Suspend" exit
......
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View file @ a391d494
......@@ -84,6 +84,41 @@ typedef struct mc_streamid_security_cfg {
.override_enable = OVERRIDE_ ## access \
}
typedef struct mc_regs {
uint32_t reg;
uint32_t val;
} mc_regs_t;
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_smmu_bypass_cfg \
{ \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
.val = 0x00000000U, \
}
#define _START_OF_TABLE_ \
{ \
.reg = 0xCAFE05C7U, \
.val = 0x00000000U, \
}
#define _END_OF_TABLE_ \
{ \
.reg = 0xFFFFFFFFU, \
.val = 0xFFFFFFFFU, \
}
/*******************************************************************************
* Structure to hold Memory Controller's Configuration settings
******************************************************************************/
......@@ -96,6 +131,7 @@ typedef struct tegra_mc_settings {
uint32_t num_txn_override_cfgs;
void (*reconfig_mss_clients)(void);
void (*set_txn_overrides)(void);
mc_regs_t* (*get_mc_system_suspend_ctx)(void);
} tegra_mc_settings_t;
static inline uint32_t tegra_mc_read_32(uint32_t off)
......@@ -165,6 +201,13 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void);
/*******************************************************************************
* Handler to save MC settings before "System Suspend" to TZDRAM
*
* Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl
******************************************************************************/
void tegra_mc_save_context(uint64_t mc_ctx_addr);
/*******************************************************************************
* Handler to program the scratch registers with TZDRAM settings for the
* resume firmware.
......
plat/nvidia/tegra/include/drivers/smmu.h
View file @ a391d494
This diff is collapsed.
plat/nvidia/tegra/include/t186/tegra186_private.h
View file @ a391d494
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -10,7 +10,7 @@
void tegra186_cpu_reset_handler(void);
uint64_t tegra186_get_cpu_reset_handler_base(void);
uint64_t tegra186_get_cpu_reset_handler_size(void);
uint64_t tegra186_get_smmu_ctx_offset(void);
uint64_t tegra186_get_mc_ctx_offset(void);
void tegra186_set_system_suspend_entry(void);
#endif /* TEGRA186_PRIVATE_H */
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ a391d494
......@@ -275,8 +275,8 @@
#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO
#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI
#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6
#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO
#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI
#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO
#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI
#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO
#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI
#define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO
......
plat/nvidia/tegra/include/t194/tegra194_private.h
View file @ a391d494
......@@ -10,7 +10,7 @@
void tegra194_cpu_reset_handler(void);
uint64_t tegra194_get_cpu_reset_handler_base(void);
uint64_t tegra194_get_cpu_reset_handler_size(void);
uint64_t tegra194_get_smmu_ctx_offset(void);
uint64_t tegra194_get_mc_ctx_offset(void);
void tegra194_set_system_suspend_entry(void);
#endif /* TEGRA194_PRIVATE_H */
plat/nvidia/tegra/include/t194/tegra_def.h
View file @ a391d494
......@@ -231,8 +231,8 @@
#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16)
#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI
#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
......
plat/nvidia/tegra/soc/t186/plat_memctrl.c
View file @ a391d494
......@@ -516,6 +516,171 @@ static void tegra186_memctrl_set_overrides(void)
}
}
/*******************************************************************************
* Array to hold MC context for Tegra186
******************************************************************************/
static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(AFIR),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(GPUSWR2),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(AFIW),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(SDMMCWAA),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(MPCORER),
mc_make_sid_security_cfg(PTCR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(GPUSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRAA),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(MPCOREW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(GPUSWR),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(GPUSRD2),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(AFIR),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(MPCOREW),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(GPUSWR),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(MPCORER),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(GPUSWR2),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(SDMMCRAA),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(SDMMCWAA),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(PTCR),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(GPUSRD2),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(GPUSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(AFIW),
mc_smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
return tegra186_mc_context;
}
/*******************************************************************************
* Struct to hold the memory controller settings
******************************************************************************/
......@@ -528,6 +693,7 @@ static tegra_mc_settings_t tegra186_mc_settings = {
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
.reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
.set_txn_overrides = tegra186_memctrl_set_overrides,
.get_mc_system_suspend_ctx = tegra186_get_mc_system_suspend_ctx,
};
/*******************************************************************************
......
plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
View file @ a391d494
......@@ -22,6 +22,7 @@
#include <bpmp_ipc.h>
#include <mce.h>
#include <memctrl_v2.h>
#include <security_engine.h>
#include <smmu.h>
#include <t18x_ari.h>
......@@ -99,7 +100,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
uint32_t cpu = plat_my_core_pos();
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
mce_cstate_info_t cstate_info = { 0 };
uint64_t smmu_ctx_base;
uint64_t mc_ctx_base;
uint32_t val;
/* get the state ID */
......@@ -132,10 +133,10 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
/* save SMMU context to TZDRAM */
smmu_ctx_base = params_from_bl2->tzdram_base +
tegra186_get_smmu_ctx_offset();
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
/* save MC context to TZDRAM */
mc_ctx_base = params_from_bl2->tzdram_base +
tegra186_get_mc_ctx_offset();
tegra_mc_save_context((uintptr_t)mc_ctx_base);
/* Prepare for system suspend */
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
......
plat/nvidia/tegra/soc/t186/plat_smmu.c
View file @ a391d494
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -12,171 +13,6 @@
#define MAX_NUM_SMMU_DEVICES U(1)
/*******************************************************************************
* Array to hold SMMU context for Tegra186
******************************************************************************/
static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(AFIR),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(GPUSWR2),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(AFIW),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(SDMMCWAA),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(MPCORER),
mc_make_sid_security_cfg(PTCR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(GPUSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRAA),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(MPCOREW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(GPUSWR),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(GPUSRD2),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(AFIR),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(MPCOREW),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(GPUSWR),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(MPCORER),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(GPUSWR2),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(SDMMCRAA),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(SDMMCWAA),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(PTCR),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(GPUSRD2),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(GPUSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(AFIW),
smmu_make_cfg(TEGRA_SMMU0_BASE),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
/*******************************************************************************
* Handler to return the pointer to the SMMU's context struct
******************************************************************************/
smmu_regs_t *plat_get_smmu_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra186_smmu_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_smmu_context)) - 1U;
return tegra186_smmu_context;
}
/*******************************************************************************
* Handler to return the support SMMU devices number
******************************************************************************/
......
plat/nvidia/tegra/soc/t186/plat_trampoline.S
View file @ a391d494
/*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -13,7 +14,7 @@
#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7
#define TEGRA186_STATE_SYSTEM_RESUME 0x600D
#define TEGRA186_SMMU_CTX_SIZE 0x420
#define TEGRA186_MC_CTX_SIZE 0x93
.globl tegra186_cpu_reset_handler
......@@ -69,8 +70,8 @@ endfunc tegra186_cpu_reset_handler
*
* 0x000: secure world's entrypoint
* 0x008: BL31 size (RO + RW)
* 0x00C: SMMU context start
* 0x42C: SMMU context end
* 0x00C: MC context start
* 0x42C: MC context end
*/
.align 4
......@@ -85,9 +86,9 @@ __tegra186_system_suspend_state:
.quad 0
.align 4
.globl __tegra186_smmu_context
__tegra186_smmu_context:
.rept TEGRA186_SMMU_CTX_SIZE
.globl __tegra186_mc_context
__tegra186_mc_context:
.rept TEGRA186_MC_CTX_SIZE
.quad 0
.endr
.size __tegra186_cpu_reset_handler_data, \
......@@ -99,7 +100,7 @@ __tegra186_cpu_reset_handler_end:
.globl tegra186_get_cpu_reset_handler_size
.globl tegra186_get_cpu_reset_handler_base
.globl tegra186_get_smmu_ctx_offset
.globl tegra186_get_mc_ctx_offset
.globl tegra186_set_system_suspend_entry
/* return size of the CPU reset handler */
......@@ -116,13 +117,13 @@ func tegra186_get_cpu_reset_handler_base
ret
endfunc tegra186_get_cpu_reset_handler_base
/* return the size of the SMMU context */
func tegra186_get_smmu_ctx_offset
adr x0, __tegra186_smmu_context
/* return the size of the MC context */
func tegra186_get_mc_ctx_offset
adr x0, __tegra186_mc_context
adr x1, tegra186_cpu_reset_handler
sub x0, x0, x1
ret
endfunc tegra186_get_smmu_ctx_offset
endfunc tegra186_get_mc_ctx_offset
/* set system suspend state before SC7 entry */
func tegra186_set_system_suspend_entry
......
plat/nvidia/tegra/soc/t194/plat_memctrl.c
View file @ a391d494
......@@ -299,6 +299,274 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE)
};
/*******************************************************************************
* Array to hold MC context for Tegra194
******************************************************************************/
static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(ISPFALR),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(AXIAPR),
mc_make_sid_security_cfg(AXIAPW),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(VIFALR),
mc_make_sid_security_cfg(VIFALW),
mc_make_sid_security_cfg(DLA0RDA),
mc_make_sid_security_cfg(DLA0FALRDB),
mc_make_sid_security_cfg(DLA0WRA),
mc_make_sid_security_cfg(DLA0FALWRB),
mc_make_sid_security_cfg(DLA1RDA),
mc_make_sid_security_cfg(DLA1FALRDB),
mc_make_sid_security_cfg(DLA1WRA),
mc_make_sid_security_cfg(DLA1FALWRB),
mc_make_sid_security_cfg(PVA0RDA),
mc_make_sid_security_cfg(PVA0RDB),
mc_make_sid_security_cfg(PVA0RDC),
mc_make_sid_security_cfg(PVA0WRA),
mc_make_sid_security_cfg(PVA0WRB),
mc_make_sid_security_cfg(PVA0WRC),
mc_make_sid_security_cfg(PVA1RDA),
mc_make_sid_security_cfg(PVA1RDB),
mc_make_sid_security_cfg(PVA1RDC),
mc_make_sid_security_cfg(PVA1WRA),
mc_make_sid_security_cfg(PVA1WRB),
mc_make_sid_security_cfg(PVA1WRC),
mc_make_sid_security_cfg(RCER),
mc_make_sid_security_cfg(RCEW),
mc_make_sid_security_cfg(RCEDMAR),
mc_make_sid_security_cfg(RCEDMAW),
mc_make_sid_security_cfg(NVENC1SRD),
mc_make_sid_security_cfg(NVENC1SWR),
mc_make_sid_security_cfg(PCIE0R),
mc_make_sid_security_cfg(PCIE0W),
mc_make_sid_security_cfg(PCIE1R),
mc_make_sid_security_cfg(PCIE1W),
mc_make_sid_security_cfg(PCIE2AR),
mc_make_sid_security_cfg(PCIE2AW),
mc_make_sid_security_cfg(PCIE3R),
mc_make_sid_security_cfg(PCIE3W),
mc_make_sid_security_cfg(PCIE4R),
mc_make_sid_security_cfg(PCIE4W),
mc_make_sid_security_cfg(PCIE5R),
mc_make_sid_security_cfg(PCIE5W),
mc_make_sid_security_cfg(ISPFALW),
mc_make_sid_security_cfg(DLA0RDA1),
mc_make_sid_security_cfg(DLA1RDA1),
mc_make_sid_security_cfg(PVA0RDA1),
mc_make_sid_security_cfg(PVA0RDB1),
mc_make_sid_security_cfg(PVA1RDA1),
mc_make_sid_security_cfg(PVA1RDB1),
mc_make_sid_security_cfg(PCIE5R1),
mc_make_sid_security_cfg(NVENCSRD1),
mc_make_sid_security_cfg(NVENC1SRD1),
mc_make_sid_security_cfg(ISPRA1),
mc_make_sid_security_cfg(PCIE0R1),
mc_make_sid_security_cfg(MIU0R),
mc_make_sid_security_cfg(MIU0W),
mc_make_sid_security_cfg(MIU1R),
mc_make_sid_security_cfg(MIU1W),
mc_make_sid_security_cfg(MIU2R),
mc_make_sid_security_cfg(MIU2W),
mc_make_sid_security_cfg(MIU3R),
mc_make_sid_security_cfg(MIU3W),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPFALR),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXIAPR),
mc_make_sid_override_cfg(AXIAPW),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(VIFALR),
mc_make_sid_override_cfg(VIFALW),
mc_make_sid_override_cfg(DLA0RDA),
mc_make_sid_override_cfg(DLA0FALRDB),
mc_make_sid_override_cfg(DLA0WRA),
mc_make_sid_override_cfg(DLA0FALWRB),
mc_make_sid_override_cfg(DLA1RDA),
mc_make_sid_override_cfg(DLA1FALRDB),
mc_make_sid_override_cfg(DLA1WRA),
mc_make_sid_override_cfg(DLA1FALWRB),
mc_make_sid_override_cfg(PVA0RDA),
mc_make_sid_override_cfg(PVA0RDB),
mc_make_sid_override_cfg(PVA0RDC),
mc_make_sid_override_cfg(PVA0WRA),
mc_make_sid_override_cfg(PVA0WRB),
mc_make_sid_override_cfg(PVA0WRC),
mc_make_sid_override_cfg(PVA1RDA),
mc_make_sid_override_cfg(PVA1RDB),
mc_make_sid_override_cfg(PVA1RDC),
mc_make_sid_override_cfg(PVA1WRA),
mc_make_sid_override_cfg(PVA1WRB),
mc_make_sid_override_cfg(PVA1WRC),
mc_make_sid_override_cfg(RCER),
mc_make_sid_override_cfg(RCEW),
mc_make_sid_override_cfg(RCEDMAR),
mc_make_sid_override_cfg(RCEDMAW),
mc_make_sid_override_cfg(NVENC1SRD),
mc_make_sid_override_cfg(NVENC1SWR),
mc_make_sid_override_cfg(PCIE0R),
mc_make_sid_override_cfg(PCIE0W),
mc_make_sid_override_cfg(PCIE1R),
mc_make_sid_override_cfg(PCIE1W),
mc_make_sid_override_cfg(PCIE2AR),
mc_make_sid_override_cfg(PCIE2AW),
mc_make_sid_override_cfg(PCIE3R),
mc_make_sid_override_cfg(PCIE3W),
mc_make_sid_override_cfg(PCIE4R),
mc_make_sid_override_cfg(PCIE4W),
mc_make_sid_override_cfg(PCIE5R),
mc_make_sid_override_cfg(PCIE5W),
mc_make_sid_override_cfg(ISPFALW),
mc_make_sid_override_cfg(DLA0RDA1),
mc_make_sid_override_cfg(DLA1RDA1),
mc_make_sid_override_cfg(PVA0RDA1),
mc_make_sid_override_cfg(PVA0RDB1),
mc_make_sid_override_cfg(PVA1RDA1),
mc_make_sid_override_cfg(PVA1RDB1),
mc_make_sid_override_cfg(PCIE5R1),
mc_make_sid_override_cfg(NVENCSRD1),
mc_make_sid_override_cfg(NVENC1SRD1),
mc_make_sid_override_cfg(ISPRA1),
mc_make_sid_override_cfg(PCIE0R1),
mc_make_sid_override_cfg(MIU0R),
mc_make_sid_override_cfg(MIU0W),
mc_make_sid_override_cfg(MIU1R),
mc_make_sid_override_cfg(MIU1W),
mc_make_sid_override_cfg(MIU2R),
mc_make_sid_override_cfg(MIU2W),
mc_make_sid_override_cfg(MIU3R),
mc_make_sid_override_cfg(MIU3W),
mc_smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U;
return tegra194_mc_context;
}
/*******************************************************************************
* Struct to hold the memory controller settings
******************************************************************************/
......@@ -306,7 +574,8 @@ static tegra_mc_settings_t tegra194_mc_settings = {
.streamid_override_cfg = tegra194_streamid_override_regs,
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs)
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
};
/*******************************************************************************
......
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View file @ a391d494
......@@ -20,6 +20,7 @@
#include <lib/psci/psci.h>
#include <mce.h>
#include <mce_private.h>
#include <memctrl_v2.h>
#include <plat/common/platform.h>
#include <se.h>
#include <smmu.h>
......@@ -118,7 +119,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
const plat_local_state_t *pwr_domain_state;
uint8_t stateid_afflvl0, stateid_afflvl2;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t smmu_ctx_base;
uint64_t mc_ctx_base;
uint32_t val;
mce_cstate_info_t sc7_cstate_info = {
.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
......@@ -151,10 +152,10 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
/* save SMMU context */
smmu_ctx_base = params_from_bl2->tzdram_base +
tegra194_get_smmu_ctx_offset();
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
/* save MC context */
mc_ctx_base = params_from_bl2->tzdram_base +
tegra194_get_mc_ctx_offset();
tegra_mc_save_context((uintptr_t)mc_ctx_base);
/*
* Suspend SE, RNG1 and PKA1 only on silcon and fpga,
......
plat/nvidia/tegra/soc/t194/plat_smmu.c
View file @ a391d494
......@@ -8,7 +8,6 @@
#include <common/debug.h>
#include <smmu.h>
#include <tegra_def.h>
#include <tegra_mc_def.h>
#define BOARD_SYSTEM_FPGA_BASE U(1)
#define BASE_CONFIG_SMMU_DEVICES U(2)
......@@ -19,276 +18,6 @@ static uint32_t tegra_misc_read_32(uint32_t off)
return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
}
/*******************************************************************************
* Array to hold SMMU context for Tegra194
******************************************************************************/
static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(ISPFALR),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(AXIAPR),
mc_make_sid_security_cfg(AXIAPW),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(VIFALR),
mc_make_sid_security_cfg(VIFALW),
mc_make_sid_security_cfg(DLA0RDA),
mc_make_sid_security_cfg(DLA0FALRDB),
mc_make_sid_security_cfg(DLA0WRA),
mc_make_sid_security_cfg(DLA0FALWRB),
mc_make_sid_security_cfg(DLA1RDA),
mc_make_sid_security_cfg(DLA1FALRDB),
mc_make_sid_security_cfg(DLA1WRA),
mc_make_sid_security_cfg(DLA1FALWRB),
mc_make_sid_security_cfg(PVA0RDA),
mc_make_sid_security_cfg(PVA0RDB),
mc_make_sid_security_cfg(PVA0RDC),
mc_make_sid_security_cfg(PVA0WRA),
mc_make_sid_security_cfg(PVA0WRB),
mc_make_sid_security_cfg(PVA0WRC),
mc_make_sid_security_cfg(PVA1RDA),
mc_make_sid_security_cfg(PVA1RDB),
mc_make_sid_security_cfg(PVA1RDC),
mc_make_sid_security_cfg(PVA1WRA),
mc_make_sid_security_cfg(PVA1WRB),
mc_make_sid_security_cfg(PVA1WRC),
mc_make_sid_security_cfg(RCER),
mc_make_sid_security_cfg(RCEW),
mc_make_sid_security_cfg(RCEDMAR),
mc_make_sid_security_cfg(RCEDMAW),
mc_make_sid_security_cfg(NVENC1SRD),
mc_make_sid_security_cfg(NVENC1SWR),
mc_make_sid_security_cfg(PCIE0R),
mc_make_sid_security_cfg(PCIE0W),
mc_make_sid_security_cfg(PCIE1R),
mc_make_sid_security_cfg(PCIE1W),
mc_make_sid_security_cfg(PCIE2AR),
mc_make_sid_security_cfg(PCIE2AW),
mc_make_sid_security_cfg(PCIE3R),
mc_make_sid_security_cfg(PCIE3W),
mc_make_sid_security_cfg(PCIE4R),
mc_make_sid_security_cfg(PCIE4W),
mc_make_sid_security_cfg(PCIE5R),
mc_make_sid_security_cfg(PCIE5W),
mc_make_sid_security_cfg(ISPFALW),
mc_make_sid_security_cfg(DLA0RDA1),
mc_make_sid_security_cfg(DLA1RDA1),
mc_make_sid_security_cfg(PVA0RDA1),
mc_make_sid_security_cfg(PVA0RDB1),
mc_make_sid_security_cfg(PVA1RDA1),
mc_make_sid_security_cfg(PVA1RDB1),
mc_make_sid_security_cfg(PCIE5R1),
mc_make_sid_security_cfg(NVENCSRD1),
mc_make_sid_security_cfg(NVENC1SRD1),
mc_make_sid_security_cfg(ISPRA1),
mc_make_sid_security_cfg(PCIE0R1),
mc_make_sid_security_cfg(MIU0R),
mc_make_sid_security_cfg(MIU0W),
mc_make_sid_security_cfg(MIU1R),
mc_make_sid_security_cfg(MIU1W),
mc_make_sid_security_cfg(MIU2R),
mc_make_sid_security_cfg(MIU2W),
mc_make_sid_security_cfg(MIU3R),
mc_make_sid_security_cfg(MIU3W),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPFALR),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXIAPR),
mc_make_sid_override_cfg(AXIAPW),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(VIFALR),
mc_make_sid_override_cfg(VIFALW),
mc_make_sid_override_cfg(DLA0RDA),
mc_make_sid_override_cfg(DLA0FALRDB),
mc_make_sid_override_cfg(DLA0WRA),
mc_make_sid_override_cfg(DLA0FALWRB),
mc_make_sid_override_cfg(DLA1RDA),
mc_make_sid_override_cfg(DLA1FALRDB),
mc_make_sid_override_cfg(DLA1WRA),
mc_make_sid_override_cfg(DLA1FALWRB),
mc_make_sid_override_cfg(PVA0RDA),
mc_make_sid_override_cfg(PVA0RDB),
mc_make_sid_override_cfg(PVA0RDC),
mc_make_sid_override_cfg(PVA0WRA),
mc_make_sid_override_cfg(PVA0WRB),
mc_make_sid_override_cfg(PVA0WRC),
mc_make_sid_override_cfg(PVA1RDA),
mc_make_sid_override_cfg(PVA1RDB),
mc_make_sid_override_cfg(PVA1RDC),
mc_make_sid_override_cfg(PVA1WRA),
mc_make_sid_override_cfg(PVA1WRB),
mc_make_sid_override_cfg(PVA1WRC),
mc_make_sid_override_cfg(RCER),
mc_make_sid_override_cfg(RCEW),
mc_make_sid_override_cfg(RCEDMAR),
mc_make_sid_override_cfg(RCEDMAW),
mc_make_sid_override_cfg(NVENC1SRD),
mc_make_sid_override_cfg(NVENC1SWR),
mc_make_sid_override_cfg(PCIE0R),
mc_make_sid_override_cfg(PCIE0W),
mc_make_sid_override_cfg(PCIE1R),
mc_make_sid_override_cfg(PCIE1W),
mc_make_sid_override_cfg(PCIE2AR),
mc_make_sid_override_cfg(PCIE2AW),
mc_make_sid_override_cfg(PCIE3R),
mc_make_sid_override_cfg(PCIE3W),
mc_make_sid_override_cfg(PCIE4R),
mc_make_sid_override_cfg(PCIE4W),
mc_make_sid_override_cfg(PCIE5R),
mc_make_sid_override_cfg(PCIE5W),
mc_make_sid_override_cfg(ISPFALW),
mc_make_sid_override_cfg(DLA0RDA1),
mc_make_sid_override_cfg(DLA1RDA1),
mc_make_sid_override_cfg(PVA0RDA1),
mc_make_sid_override_cfg(PVA0RDB1),
mc_make_sid_override_cfg(PVA1RDA1),
mc_make_sid_override_cfg(PVA1RDB1),
mc_make_sid_override_cfg(PCIE5R1),
mc_make_sid_override_cfg(NVENCSRD1),
mc_make_sid_override_cfg(NVENC1SRD1),
mc_make_sid_override_cfg(ISPRA1),
mc_make_sid_override_cfg(PCIE0R1),
mc_make_sid_override_cfg(MIU0R),
mc_make_sid_override_cfg(MIU0W),
mc_make_sid_override_cfg(MIU1R),
mc_make_sid_override_cfg(MIU1W),
mc_make_sid_override_cfg(MIU2R),
mc_make_sid_override_cfg(MIU2W),
mc_make_sid_override_cfg(MIU3R),
mc_make_sid_override_cfg(MIU3W),
smmu_make_cfg(TEGRA_SMMU0_BASE),
smmu_make_cfg(TEGRA_SMMU2_BASE),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
/*******************************************************************************
* Handler to return the pointer to the SMMU's context struct
******************************************************************************/
smmu_regs_t *plat_get_smmu_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U;
return tegra194_smmu_context;
}
/*******************************************************************************
* Handler to return the support SMMU devices number
******************************************************************************/
......
plat/nvidia/tegra/soc/t194/plat_trampoline.S
View file @ a391d494
......@@ -12,7 +12,7 @@
#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
#define TEGRA194_SMMU_CTX_SIZE 0x80D
#define TEGRA194_MC_CTX_SIZE 0xFB
.align 4
.globl tegra194_cpu_reset_handler
......@@ -69,8 +69,8 @@ endfunc tegra194_cpu_reset_handler
*
* 0x0000: secure world's entrypoint
* 0x0008: BL31 size (RO + RW)
* 0x0010: SMMU context start
* 0x2490: SMMU context end
* 0x0010: MC context start
* 0x2490: MC context end
*/
.align 4
......@@ -79,14 +79,13 @@ endfunc tegra194_cpu_reset_handler
__tegra194_cpu_reset_handler_data:
.quad tegra_secure_entrypoint
.quad __BL31_END__ - BL31_BASE
.globl __tegra194_system_suspend_state
__tegra194_system_suspend_state:
.quad 0
.align 4
__tegra194_smmu_context:
.rept TEGRA194_SMMU_CTX_SIZE
__tegra194_mc_context:
.rept TEGRA194_MC_CTX_SIZE
.quad 0
.endr
.size __tegra194_cpu_reset_handler_data, \
......@@ -98,7 +97,7 @@ __tegra194_cpu_reset_handler_end:
.globl tegra194_get_cpu_reset_handler_size
.globl tegra194_get_cpu_reset_handler_base
.globl tegra194_get_smmu_ctx_offset
.globl tegra194_get_mc_ctx_offset
.globl tegra194_set_system_suspend_entry
/* return size of the CPU reset handler */
......@@ -115,13 +114,13 @@ func tegra194_get_cpu_reset_handler_base
ret
endfunc tegra194_get_cpu_reset_handler_base
/* return the size of the SMMU context */
func tegra194_get_smmu_ctx_offset
adr x0, __tegra194_smmu_context
/* return the size of the MC context */
func tegra194_get_mc_ctx_offset
adr x0, __tegra194_mc_context
adr x1, tegra194_cpu_reset_handler
sub x0, x0, x1
ret
endfunc tegra194_get_smmu_ctx_offset
endfunc tegra194_get_mc_ctx_offset
/* set system suspend state before SC7 entry */
func tegra194_set_system_suspend_entry
......
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