Commit a3c2c0e9 authored by Steven Kao's avatar Steven Kao Committed by Manish Pandey
Browse files

Tegra194: config to enable/disable strict checking mode



This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.

Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
parent 181a9fab
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -186,6 +186,7 @@ void mce_verify_firmware_version(void) ...@@ -186,6 +186,7 @@ void mce_verify_firmware_version(void)
} }
} }
#if ENABLE_STRICT_CHECKING_MODE
/******************************************************************************* /*******************************************************************************
* Handler to enable the strict checking mode * Handler to enable the strict checking mode
******************************************************************************/ ******************************************************************************/
...@@ -235,3 +236,4 @@ void mce_enable_strict_checking(void) ...@@ -235,3 +236,4 @@ void mce_enable_strict_checking(void)
nvg_enable_strict_checking_mode(); nvg_enable_strict_checking_mode();
} }
} }
#endif
...@@ -288,6 +288,7 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) ...@@ -288,6 +288,7 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
return ret; return ret;
} }
#if ENABLE_STRICT_CHECKING_MODE
/* /*
* Enable strict checking mode * Enable strict checking mode
* *
...@@ -300,3 +301,4 @@ void nvg_enable_strict_checking_mode(void) ...@@ -300,3 +301,4 @@ void nvg_enable_strict_checking_mode(void)
nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
} }
#endif
...@@ -357,11 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -357,11 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
*/ */
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
#if ENABLE_STRICT_CHECKING_MODE
/* /*
* Enable strict checking after programming the GSC for * Enable strict checking after programming the GSC for
* enabling TZSRAM and TZDRAM * enabling TZSRAM and TZDRAM
*/ */
mce_enable_strict_checking(); mce_enable_strict_checking();
#endif
/* Init SMMU */ /* Init SMMU */
tegra_smmu_init(); tegra_smmu_init();
......
...@@ -293,9 +293,11 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) ...@@ -293,9 +293,11 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
void plat_late_platform_setup(void) void plat_late_platform_setup(void)
{ {
#if ENABLE_STRICT_CHECKING_MODE
/* /*
* Enable strict checking after programming the GSC for * Enable strict checking after programming the GSC for
* enabling TZSRAM and TZDRAM * enabling TZSRAM and TZDRAM
*/ */
mce_enable_strict_checking(); mce_enable_strict_checking();
#endif
} }
...@@ -8,6 +8,9 @@ ...@@ -8,6 +8,9 @@
ENABLE_CONSOLE_SPE := 0 ENABLE_CONSOLE_SPE := 0
$(eval $(call add_define,ENABLE_CONSOLE_SPE)) $(eval $(call add_define,ENABLE_CONSOLE_SPE))
ENABLE_STRICT_CHECKING_MODE := 1
$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
RESET_TO_BL31 := 1 RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1 PROGRAMMABLE_RESET_ADDRESS := 1
......
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