Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration

* changes:
  Rename Neoverse Zeus to Neoverse V1
  Rename Cortex Hercules AE to Cortex 78 AE

include/lib/cpus/aarch64/cortex_hercules_ae.h → include/lib/cpus/aarch64/cortex_a78_ae.h

@@ -4,11 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_HERCULES_AE_H
-#define CORTEX_HERCULES_AE_H
+#ifndef CORTEX_A78_AE_H
+#define CORTEX_A78_AE_H
 
 #include <cortex_a78.h>
 
-#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
+#define CORTEX_A78_AE_MIDR U(0x410FD420)
 
-#endif /* CORTEX_HERCULES_AE_H */
+#endif /* CORTEX_A78_AE_H */

include/lib/cpus/aarch64/neoverse_zeus.h → include/lib/cpus/aarch64/neoverse_v1.h

 /*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef NEOVERSE_ZEUS_H
-#define NEOVERSE_ZEUS_H
+#ifndef NEOVERSE_V1_H
+#define NEOVERSE_V1_H
 
-#define NEOVERSE_ZEUS_MIDR					U(0x410FD400)
+#define NEOVERSE_V1_MIDR					U(0x410FD400)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUECTLR_EL1				S3_0_C15_C1_4
+#define NEOVERSE_V1_CPUECTLR_EL1				S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1				S3_0_C15_C2_7
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define NEOVERSE_V1_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
-#endif /* NEOVERSE_ZEUS_H */
+#endif /* NEOVERSE_V1_H */

lib/cpus/aarch64/cortex_hercules_ae.S → lib/cpus/aarch64/cortex_a78_ae.S

@@ -7,21 +7,21 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_hercules_ae.h>
+#include <cortex_a78_ae.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 	/* -------------------------------------------------
-	 * The CPU Ops reset function for Cortex-Hercules-AE
+	 * The CPU Ops reset function for Cortex-A78-AE
 	 * -------------------------------------------------
 	 */
 #if ENABLE_AMU
-func cortex_hercules_ae_reset_func
+func cortex_a78_ae_reset_func
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
 	bic	x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
@@ -42,14 +42,14 @@ func cortex_hercules_ae_reset_func
 	isb
 
 	ret
-endfunc cortex_hercules_ae_reset_func
+endfunc cortex_a78_ae_reset_func
 #endif
 
 	/* -------------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * -------------------------------------------------------
 	 */
-func cortex_hercules_ae_core_pwr_dwn
+func cortex_a78_ae_core_pwr_dwn
 	/* -------------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * -------------------------------------------------------
@@ -59,19 +59,19 @@ func cortex_hercules_ae_core_pwr_dwn
 	msr	CORTEX_A78_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_hercules_ae_core_pwr_dwn
+endfunc cortex_a78_ae_core_pwr_dwn
 
 	/*
-	 * Errata printing function for cortex_hercules_ae. Must follow AAPCS.
+	 * Errata printing function for cortex_a78_ae. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_hercules_ae_errata_report
+func cortex_a78_ae_errata_report
 	ret
-endfunc cortex_hercules_ae_errata_report
+endfunc cortex_a78_ae_errata_report
 #endif
 
 	/* -------------------------------------------------------
-	 * This function provides cortex_hercules_ae specific
+	 * This function provides cortex_a78_ae specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -79,22 +79,22 @@ endfunc cortex_hercules_ae_errata_report
 	 * reported.
 	 * -------------------------------------------------------
 	 */
-.section .rodata.cortex_hercules_ae_regs, "aS"
-cortex_hercules_ae_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_a78_ae_regs, "aS"
+cortex_a78_ae_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_hercules_ae_cpu_reg_dump
-	adr	x6, cortex_hercules_ae_regs
+func cortex_a78_ae_cpu_reg_dump
+	adr	x6, cortex_a78_ae_regs
 	mrs	x8, CORTEX_A78_CPUECTLR_EL1
 	ret
-endfunc cortex_hercules_ae_cpu_reg_dump
+endfunc cortex_a78_ae_cpu_reg_dump
 
 #if ENABLE_AMU
-#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func
+#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
 #else
-#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC
+#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
 #endif
 
-declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \
-	HERCULES_AE_RESET_FUNC, \
-	cortex_hercules_ae_core_pwr_dwn
+declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
+	A78_AE_RESET_FUNC, \
+	cortex_a78_ae_core_pwr_dwn

lib/cpus/aarch64/neoverse_zeus.S → lib/cpus/aarch64/neoverse_v1.S

 /*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,46 +7,46 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <neoverse_zeus.h>
+#include <neoverse_v1.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
 	 */
-func neoverse_zeus_core_pwr_dwn
+func neoverse_v1_core_pwr_dwn
 	/* ---------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------
 	 */
-	mrs	x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1
-	orr	x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0
+	mrs	x0, NEOVERSE_V1_CPUPWRCTLR_EL1
+	orr	x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	NEOVERSE_V1_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc neoverse_zeus_core_pwr_dwn
+endfunc neoverse_v1_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Neoverse Zeus. Must follow AAPCS.
+	 * Errata printing function for Neoverse V1. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func neoverse_zeus_errata_report
+func neoverse_v1_errata_report
 	ret
-endfunc neoverse_zeus_errata_report
+endfunc neoverse_v1_errata_report
 #endif
 
-func neoverse_zeus_reset_func
+func neoverse_v1_reset_func
 	mov	x19, x30
 
 	/* Disable speculative loads */
@@ -54,10 +54,10 @@ func neoverse_zeus_reset_func
 
 	isb
 	ret	x19
-endfunc neoverse_zeus_reset_func
+endfunc neoverse_v1_reset_func
 
 	/* ---------------------------------------------
-	 * This function provides Neoverse-Zeus specific
+	 * This function provides Neoverse-V1 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -65,16 +65,16 @@ endfunc neoverse_zeus_reset_func
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.neoverse_zeus_regs, "aS"
-neoverse_zeus_regs:  /* The ascii list of register names to be reported */
+.section .rodata.neoverse_v1_regs, "aS"
+neoverse_v1_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func neoverse_zeus_cpu_reg_dump
-	adr	x6, neoverse_zeus_regs
-	mrs	x8, NEOVERSE_ZEUS_CPUECTLR_EL1
+func neoverse_v1_cpu_reg_dump
+	adr	x6, neoverse_v1_regs
+	mrs	x8, NEOVERSE_V1_CPUECTLR_EL1
 	ret
-endfunc neoverse_zeus_cpu_reg_dump
+endfunc neoverse_v1_cpu_reg_dump
 
-declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
-	neoverse_zeus_reset_func, \
-	neoverse_zeus_core_pwr_dwn
+declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
+	neoverse_v1_reset_func, \
+	neoverse_v1_core_pwr_dwn

plat/arm/board/arm_fpga/platform.mk

@@ -61,8 +61,8 @@ else
 				lib/cpus/aarch64/cortex_a78.S		\
 				lib/cpus/aarch64/neoverse_n1.S		\
 				lib/cpus/aarch64/neoverse_e1.S		\
-				lib/cpus/aarch64/neoverse_zeus.S	\
-				lib/cpus/aarch64/cortex_hercules_ae.S	\
+				lib/cpus/aarch64/neoverse_v1.S		\
+				lib/cpus/aarch64/cortex_a78_ae.S	\
 				lib/cpus/aarch64/cortex_a65.S		\
 				lib/cpus/aarch64/cortex_a65ae.S		\
 				lib/cpus/aarch64/cortex_klein.S		\

plat/arm/board/fvp/platform.mk

@@ -120,8 +120,8 @@ else
 					lib/cpus/aarch64/cortex_a78.S		\
 					lib/cpus/aarch64/neoverse_n1.S		\
 					lib/cpus/aarch64/neoverse_e1.S		\
-					lib/cpus/aarch64/neoverse_zeus.S	\
-					lib/cpus/aarch64/cortex_hercules_ae.S	\
+					lib/cpus/aarch64/neoverse_v1.S		\
+					lib/cpus/aarch64/cortex_a78_ae.S	\
 					lib/cpus/aarch64/cortex_klein.S	        \
 					lib/cpus/aarch64/cortex_matterhorn.S	\
 					lib/cpus/aarch64/cortex_a65.S		\

plat/arm/board/rddaniel/platform.mk

@@ -12,7 +12,7 @@ RDDANIEL_BASE		=	plat/arm/board/rddaniel
 
 PLAT_INCLUDES		+=	-I${RDDANIEL_BASE}/include/
 
-SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
 
 BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
 				${RDDANIEL_BASE}/rddaniel_err.c

plat/arm/board/rddanielxlr/platform.mk

@@ -13,7 +13,7 @@ RDDANIELXLR_BASE	=	plat/arm/board/rddanielxlr
 
 PLAT_INCLUDES		+=	-I${RDDANIELXLR_BASE}/include/
 
-SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
 
 BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
 				${RDDANIELXLR_BASE}/rddanielxlr_err.c