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Commit a6d28520 authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu
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xilinx: zynqmp: Remove PMU Firmware checks 



Xilinx now requires the PMU FW when using ATF, so it doesn't make sense
to maintain checks for the PMU FW in ATF. This also means that cases
where ATF came up before the PMU FW (such as on QEMU) ATF will now hang
waiting for the PMU FW instead of aborting.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 3d512f0b
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Inline Side-by-side
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file @ a6d28520
......@@ -289,57 +289,22 @@ static void zynqmp_print_platform_name(void)
break;
}
NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x%s\n",
NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
(rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE,
zynqmp_is_pmu_up() ? ", with PMU firmware" : "");
(rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
}
#else
static inline void zynqmp_print_platform_name(void) { }
#endif
/*
* Indicator for PMUFW discovery:
* 0 = No FW found
* non-zero = FW is present
*/
static int zynqmp_pmufw_present;
/*
* zynqmp_discover_pmufw - Discover presence of PMUFW
*
* Discover the presence of PMUFW and store it for later run-time queries
* through zynqmp_is_pmu_up.
* NOTE: This discovery method is fragile and will break if:
* - setting FW_PRESENT is done by PMUFW itself and could be left out in PMUFW
* (be it by error or intentionally)
* - XPPU/XMPU may restrict ATF's access to the PMU address space
*/
static int zynqmp_discover_pmufw(void)
{
zynqmp_pmufw_present = mmio_read_32(PMU_GLOBAL_CNTRL);
zynqmp_pmufw_present &= PMU_GLOBAL_CNTRL_FW_IS_PRESENT;
return !!zynqmp_pmufw_present;
}
/*
* zynqmp_is_pmu_up - Find if PMU firmware is up and running
*
* Return 0 if firmware is not available, non 0 otherwise
*/
int zynqmp_is_pmu_up(void)
{
return zynqmp_pmufw_present;
}
unsigned int zynqmp_get_bootmode(void)
{
uint32_t r;
unsigned int ret;
ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
if (zynqmp_is_pmu_up())
pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
else
if (ret != PM_RET_SUCCESS)
r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
return r & CRL_APB_BOOT_MODE_MASK;
......@@ -347,7 +312,6 @@ unsigned int zynqmp_get_bootmode(void)
void zynqmp_config_setup(void)
{
zynqmp_discover_pmufw();
zynqmp_print_platform_name();
generic_delay_timer_init();
}
......
plat/xilinx/zynqmp/plat_psci.c
View file @ a6d28520
......@@ -27,46 +27,6 @@ void zynqmp_cpu_standby(plat_local_state_t cpu_state)
wfi();
}
static int zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
{
uint32_t r;
unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
if (cpu_id == -1)
return PSCI_E_INTERN_FAIL;
/* program RVBAR */
mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry);
mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32);
/* clear VINITHI */
r = mmio_read_32(APU_CONFIG_0);
r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id);
mmio_write_32(APU_CONFIG_0, r);
/* clear power down request */
r = mmio_read_32(APU_PWRCTL);
r &= ~(1 << cpu_id);
mmio_write_32(APU_PWRCTL, r);
/* power up island */
mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id);
mmio_write_32(PMU_GLOBAL_REQ_PWRUP_TRIG, 1 << cpu_id);
/* FIXME: we should have a way to break out */
while (mmio_read_32(PMU_GLOBAL_REQ_PWRUP_STATUS) & (1 << cpu_id))
;
/* release core reset */
r = mmio_read_32(CRF_APB_RST_FPD_APU);
r &= ~((CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET |
CRF_APB_RST_FPD_APU_ACPU_RESET) << cpu_id);
mmio_write_32(CRF_APB_RST_FPD_APU, r);
return PSCI_E_SUCCESS;
}
static int zynqmp_pwr_domain_on(u_register_t mpidr)
{
unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
......@@ -87,24 +47,6 @@ static int zynqmp_pwr_domain_on(u_register_t mpidr)
return PSCI_E_SUCCESS;
}
static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state)
{
uint32_t r;
unsigned int cpu_id = plat_my_core_pos();
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* Prevent interrupts from spuriously waking up this cpu */
gicv2_cpuif_disable();
/* set power down request */
r = mmio_read_32(APU_PWRCTL);
r |= (1 << cpu_id);
mmio_write_32(APU_PWRCTL, r);
}
static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
{
unsigned int cpu_id = plat_my_core_pos();
......@@ -128,33 +70,6 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
}
static void zynqmp_nopmu_pwr_domain_suspend(const psci_power_state_t *target_state)
{
uint32_t r;
unsigned int cpu_id = plat_my_core_pos();
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* set power down request */
r = mmio_read_32(APU_PWRCTL);
r |= (1 << cpu_id);
mmio_write_32(APU_PWRCTL, r);
/* program RVBAR */
mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry);
mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32);
/* clear VINITHI */
r = mmio_read_32(APU_CONFIG_0);
r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id);
mmio_write_32(APU_CONFIG_0, r);
/* enable power up on IRQ */
mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id);
}
static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
{
unsigned int state;
......@@ -188,24 +103,6 @@ static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
gicv2_pcpu_distif_init();
}
static void zynqmp_nopmu_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
uint32_t r;
unsigned int cpu_id = plat_my_core_pos();
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* disable power up on IRQ */
mmio_write_32(PMU_GLOBAL_REQ_PWRUP_DIS, 1 << cpu_id);
/* clear powerdown bit */
r = mmio_read_32(APU_PWRCTL);
r &= ~(1 << cpu_id);
mmio_write_32(APU_PWRCTL, r);
}
static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
unsigned int cpu_id = plat_my_core_pos();
......@@ -232,15 +129,6 @@ static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_st
/*******************************************************************************
* ZynqMP handlers to shutdown/reboot the system
******************************************************************************/
static void __dead2 zynqmp_nopmu_system_off(void)
{
ERROR("ZynqMP System Off: operation not handled.\n");
/* disable coherency */
plat_arm_interconnect_exit_coherency();
panic();
}
static void __dead2 zynqmp_system_off(void)
{
......@@ -255,28 +143,6 @@ static void __dead2 zynqmp_system_off(void)
wfi();
}
static void __dead2 zynqmp_nopmu_system_reset(void)
{
/*
* This currently triggers a system reset. I.e. the whole
* system will be reset! Including RPUs, PMU, PL, etc.
*/
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* bypass RPLL (needed on 1.0 silicon) */
uint32_t reg = mmio_read_32(CRL_APB_RPLL_CTRL);
reg |= CRL_APB_RPLL_CTRL_BYPASS;
mmio_write_32(CRL_APB_RPLL_CTRL, reg);
/* trigger system reset */
mmio_write_32(CRL_APB_RESET_CTRL, CRL_APB_RESET_CTRL_SOFT_RESET);
while (1)
wfi();
}
static void __dead2 zynqmp_system_reset(void)
{
/* disable coherency */
......@@ -343,20 +209,6 @@ static const struct plat_psci_ops zynqmp_psci_ops = {
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
};
static const struct plat_psci_ops zynqmp_nopmu_psci_ops = {
.cpu_standby = zynqmp_cpu_standby,
.pwr_domain_on = zynqmp_nopmu_pwr_domain_on,
.pwr_domain_off = zynqmp_nopmu_pwr_domain_off,
.pwr_domain_suspend = zynqmp_nopmu_pwr_domain_suspend,
.pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
.pwr_domain_suspend_finish = zynqmp_nopmu_pwr_domain_suspend_finish,
.system_off = zynqmp_nopmu_system_off,
.system_reset = zynqmp_nopmu_system_reset,
.validate_power_state = zynqmp_validate_power_state,
.validate_ns_entrypoint = zynqmp_validate_ns_entrypoint,
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
};
/*******************************************************************************
* Export the platform specific power ops.
******************************************************************************/
......@@ -365,10 +217,7 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
{
zynqmp_sec_entry = sec_entrypoint;
if (zynqmp_is_pmu_up())
*psci_ops = &zynqmp_psci_ops;
else
*psci_ops = &zynqmp_nopmu_psci_ops;
*psci_ops = &zynqmp_psci_ops;
return 0;
}
plat/xilinx/zynqmp/pm_service/pm_svc_main.c
View file @ a6d28520
......@@ -53,9 +53,6 @@ int pm_setup(void)
{
int status, ret;
if (!zynqmp_is_pmu_up())
return -ENODEV;
status = pm_ipi_init(primary_proc);
if (status >= 0) {
......
plat/xilinx/zynqmp/zynqmp_private.h
View file @ a6d28520
......@@ -14,7 +14,6 @@ void zynqmp_config_setup(void);
/* ZynqMP specific functions */
unsigned int zynqmp_get_uart_clk(void);
int zynqmp_is_pmu_up(void);
unsigned int zynqmp_get_bootmode(void);
/* For FSBL handover */
......
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