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Commit ade9ce03 authored by Yann Gautier's avatar Yann Gautier
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stm32mp1: get peripheral base address from a define 



Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.
Signed-off-by: default avatarPascal Paillet <p.paillet@st.com>
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
parent f964f5c3
Hide whitespace changes
Inline Side-by-side
drivers/st/clk/stm32mp1_clk.c
View file @ ade9ce03
/* /*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/ */
...@@ -1664,28 +1664,26 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) ...@@ -1664,28 +1664,26 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
static void stm32mp1_stgen_config(void) static void stm32mp1_stgen_config(void)
{ {
uintptr_t stgen;
uint32_t cntfid0; uint32_t cntfid0;
unsigned long rate; unsigned long rate;
unsigned long long counter; unsigned long long counter;
stgen = fdt_get_stgen_base(); cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
if (cntfid0 == rate) { if (cntfid0 == rate) {
return; return;
} }
mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
counter = (counter * rate / cntfid0); counter = (counter * rate / cntfid0);
mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
mmio_write_32(stgen + CNTFID_OFF, rate); mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
write_cntfrq((u_register_t)rate); write_cntfrq((u_register_t)rate);
...@@ -1695,20 +1693,17 @@ static void stm32mp1_stgen_config(void) ...@@ -1695,20 +1693,17 @@ static void stm32mp1_stgen_config(void)
void stm32mp1_stgen_increment(unsigned long long offset_in_ms) void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
{ {
uintptr_t stgen;
unsigned long long cnt; unsigned long long cnt;
stgen = fdt_get_stgen_base(); cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
mmio_read_32(STGEN_BASE + CNTCVL_OFF);
cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
mmio_read_32(stgen + CNTCVL_OFF);
cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
} }
static void stm32mp1_pkcs_config(uint32_t pkcs) static void stm32mp1_pkcs_config(uint32_t pkcs)
......
drivers/st/clk/stm32mp_clkfunc.c
View file @ ade9ce03
/* /*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -14,8 +14,6 @@ ...@@ -14,8 +14,6 @@
#include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h> #include <drivers/st/stm32mp_clkfunc.h>
#define DT_STGEN_COMPAT "st,stm32-stgen"
/* /*
* Get the frequency of an oscillator from its name in device tree. * Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name * @param name: oscillator name
...@@ -168,33 +166,6 @@ int fdt_get_rcc_node(void *fdt) ...@@ -168,33 +166,6 @@ int fdt_get_rcc_node(void *fdt)
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
} }
/*
* Get the RCC base address from the device tree
* @return: RCC address or 0 on error
*/
uint32_t fdt_rcc_read_addr(void)
{
int node;
void *fdt;
const fdt32_t *cuint;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/* /*
* Read a series of parameters in rcc-clk section in device tree * Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read * @param prop_name: Name of the RCC property to be read
...@@ -298,33 +269,6 @@ bool fdt_get_rcc_secure_status(void) ...@@ -298,33 +269,6 @@ bool fdt_get_rcc_secure_status(void)
return !!(fdt_get_status(node) & DT_SECURE); return !!(fdt_get_status(node) & DT_SECURE);
} }
/*
* Get the stgen base address.
* @return: address of stgen on success, and NULL value on failure.
*/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/* /*
* Get the clock ID of the given node in device tree. * Get the clock ID of the given node in device tree.
* @param node: node offset * @param node: node offset
......
include/drivers/st/stm32mp_clkfunc.h
View file @ ade9ce03
/* /*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, ...@@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
uint32_t dflt_value); uint32_t dflt_value);
int fdt_get_rcc_node(void *fdt); int fdt_get_rcc_node(void *fdt);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count, int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
uint32_t *array); uint32_t *array);
int fdt_rcc_subnode_offset(const char *name); int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void); bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node); int fdt_get_clock_id(int node);
#endif /* STM32MP_CLKFUNC_H */ #endif /* STM32MP_CLKFUNC_H */
plat/st/common/include/stm32mp_dt.h
View file @ ade9ce03
...@@ -34,11 +34,7 @@ void dt_fill_device_info(struct dt_node_info *info, int node); ...@@ -34,11 +34,7 @@ void dt_fill_device_info(struct dt_node_info *info, int node);
int dt_get_node(struct dt_node_info *info, int offset, const char *compat); int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info); int dt_get_stdout_uart_info(struct dt_node_info *info);
uint32_t dt_get_ddr_size(void); uint32_t dt_get_ddr_size(void);
uintptr_t dt_get_ddrctrl_base(void);
uintptr_t dt_get_ddrphyc_base(void);
uintptr_t dt_get_pwr_base(void);
uint32_t dt_get_pwr_vdd_voltage(void); uint32_t dt_get_pwr_vdd_voltage(void);
uintptr_t dt_get_syscfg_base(void);
const char *dt_get_board_model(void); const char *dt_get_board_model(void);
int fdt_get_gpio_bank_pin_count(unsigned int bank); int fdt_get_gpio_bank_pin_count(unsigned int bank);
......
plat/st/common/stm32mp_common.c
View file @ ade9ce03
...@@ -39,54 +39,22 @@ uintptr_t stm32mp_get_boot_ctx_address(void) ...@@ -39,54 +39,22 @@ uintptr_t stm32mp_get_boot_ctx_address(void)
uintptr_t stm32mp_ddrctrl_base(void) uintptr_t stm32mp_ddrctrl_base(void)
{ {
static uintptr_t ddrctrl_base; return DDRCTRL_BASE;
if (ddrctrl_base == 0) {
ddrctrl_base = dt_get_ddrctrl_base();
assert(ddrctrl_base == DDRCTRL_BASE);
}
return ddrctrl_base;
} }
uintptr_t stm32mp_ddrphyc_base(void) uintptr_t stm32mp_ddrphyc_base(void)
{ {
static uintptr_t ddrphyc_base; return DDRPHYC_BASE;
if (ddrphyc_base == 0) {
ddrphyc_base = dt_get_ddrphyc_base();
assert(ddrphyc_base == DDRPHYC_BASE);
}
return ddrphyc_base;
} }
uintptr_t stm32mp_pwr_base(void) uintptr_t stm32mp_pwr_base(void)
{ {
static uintptr_t pwr_base; return PWR_BASE;
if (pwr_base == 0) {
pwr_base = dt_get_pwr_base();
assert(pwr_base == PWR_BASE);
}
return pwr_base;
} }
uintptr_t stm32mp_rcc_base(void) uintptr_t stm32mp_rcc_base(void)
{ {
static uintptr_t rcc_base; return RCC_BASE;
if (rcc_base == 0) {
rcc_base = fdt_rcc_read_addr();
assert(rcc_base == RCC_BASE);
}
return rcc_base;
} }
bool stm32mp_lock_available(void) bool stm32mp_lock_available(void)
......
plat/st/common/stm32mp_dt.c
View file @ ade9ce03
...@@ -113,26 +113,6 @@ static int fdt_get_node_parent_address_cells(int node) ...@@ -113,26 +113,6 @@ static int fdt_get_node_parent_address_cells(int node)
return fdt_address_cells(fdt, parent); return fdt_address_cells(fdt, parent);
} }
/*******************************************************************************
* This function returns the size cells from the node parent.
* Returns:
* - #size-cells value if success.
* - invalid value if error.
* - a default value if undefined #size-cells property as per libfdt
* implementation.
******************************************************************************/
static int fdt_get_node_parent_size_cells(int node)
{
int parent;
parent = fdt_parent_offset(fdt, node);
if (parent < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_size_cells(fdt, parent);
}
#endif #endif
/******************************************************************************* /*******************************************************************************
...@@ -240,81 +220,6 @@ uint32_t dt_get_ddr_size(void) ...@@ -240,81 +220,6 @@ uint32_t dt_get_ddr_size(void)
return fdt_read_uint32_default(fdt, node, "st,mem-size", 0); return fdt_read_uint32_default(fdt, node, "st,mem-size", 0);
} }
/*******************************************************************************
* This function gets DDRCTRL base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrctrl_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
assert((fdt_get_node_parent_address_cells(node) == 1) &&
(fdt_get_node_parent_size_cells(node) == 1));
if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
return 0;
}
return array[0];
}
/*******************************************************************************
* This function gets DDRPHYC base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrphyc_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
assert((fdt_get_node_parent_address_cells(node) == 1) &&
(fdt_get_node_parent_size_cells(node) == 1));
if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
return 0;
}
return array[2];
}
/*******************************************************************************
* This function gets PWR base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_pwr_base(void)
{
int node;
const fdt32_t *cuint;
node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read PWR node in DT\n", __func__);
return 0;
}
assert(fdt_get_node_parent_address_cells(node) == 1);
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/******************************************************************************* /*******************************************************************************
* This function gets PWR VDD regulator voltage information from the DT. * This function gets PWR VDD regulator voltage information from the DT.
* Returns value in microvolts on success, and 0 on failure. * Returns value in microvolts on success, and 0 on failure.
...@@ -354,31 +259,6 @@ uint32_t dt_get_pwr_vdd_voltage(void) ...@@ -354,31 +259,6 @@ uint32_t dt_get_pwr_vdd_voltage(void)
return fdt32_to_cpu(*cuint); return fdt32_to_cpu(*cuint);
} }
/*******************************************************************************
* This function gets SYSCFG base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_syscfg_base(void)
{
int node;
const fdt32_t *cuint;
node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT);
if (node < 0) {
INFO("%s: Cannot read SYSCFG node in DT\n", __func__);
return 0;
}
assert(fdt_get_node_parent_address_cells(node) == 1);
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/******************************************************************************* /*******************************************************************************
* This function retrieves board model from DT * This function retrieves board model from DT
* Returns string taken from model node, NULL otherwise * Returns string taken from model node, NULL otherwise
......
plat/st/stm32mp1/stm32mp1_def.h
View file @ ade9ce03
...@@ -506,6 +506,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx) ...@@ -506,6 +506,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
/******************************************************************************* /*******************************************************************************
* Miscellaneous STM32MP1 peripherals base address * Miscellaneous STM32MP1 peripherals base address
******************************************************************************/ ******************************************************************************/
#define BSEC_BASE U(0x5C005000)
#define CRYP1_BASE U(0x54001000) #define CRYP1_BASE U(0x54001000)
#define DBGMCU_BASE U(0x50081000) #define DBGMCU_BASE U(0x50081000)
#define HASH1_BASE U(0x54002000) #define HASH1_BASE U(0x54002000)
...@@ -514,6 +515,8 @@ static inline uint32_t tamp_bkpr(uint32_t idx) ...@@ -514,6 +515,8 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
#define RNG1_BASE U(0x54003000) #define RNG1_BASE U(0x54003000)
#define RTC_BASE U(0x5c004000) #define RTC_BASE U(0x5c004000)
#define SPI6_BASE U(0x5c001000) #define SPI6_BASE U(0x5c001000)
#define STGEN_BASE U(0x5c008000)
#define SYSCFG_BASE U(0x50020000)
/******************************************************************************* /*******************************************************************************
* Device Tree defines * Device Tree defines
...@@ -522,6 +525,5 @@ static inline uint32_t tamp_bkpr(uint32_t idx) ...@@ -522,6 +525,5 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg" #define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
#endif /* STM32MP1_DEF_H */ #endif /* STM32MP1_DEF_H */
plat/st/stm32mp1/stm32mp1_syscfg.c
View file @ ade9ce03
/* /*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -63,18 +63,17 @@ void stm32mp1_syscfg_init(void) ...@@ -63,18 +63,17 @@ void stm32mp1_syscfg_init(void)
uint32_t bootr; uint32_t bootr;
uint32_t otp = 0; uint32_t otp = 0;
uint32_t vdd_voltage; uint32_t vdd_voltage;
uintptr_t syscfg_base = dt_get_syscfg_base();
/* /*
* Interconnect update : select master using the port 1. * Interconnect update : select master using the port 1.
* LTDC = AXI_M9. * LTDC = AXI_M9.
*/ */
mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
/* Disable Pull-Down for boot pin connected to VDD */ /* Disable Pull-Down for boot pin connected to VDD */
bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) & bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
SYSCFG_BOOTR_BOOT_MASK; SYSCFG_BOOTR_BOOT_MASK;
mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
/* /*
...@@ -105,7 +104,7 @@ void stm32mp1_syscfg_init(void) ...@@ -105,7 +104,7 @@ void stm32mp1_syscfg_init(void)
if (vdd_voltage == 0U) { if (vdd_voltage == 0U) {
WARN("VDD unknown"); WARN("VDD unknown");
} else if (vdd_voltage < 2700000U) { } else if (vdd_voltage < 2700000U) {
mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR, mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
SYSCFG_IOCTRLSETR_HSLVEN_TRACE | SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH | SYSCFG_IOCTRLSETR_HSLVEN_ETH |
...@@ -129,8 +128,6 @@ void stm32mp1_syscfg_init(void) ...@@ -129,8 +128,6 @@ void stm32mp1_syscfg_init(void)
void stm32mp1_syscfg_enable_io_compensation(void) void stm32mp1_syscfg_enable_io_compensation(void)
{ {
uintptr_t syscfg_base = dt_get_syscfg_base();
/* /*
* Activate automatic I/O compensation. * Activate automatic I/O compensation.
* Warning: need to ensure CSI enabled and ready in clock driver. * Warning: need to ensure CSI enabled and ready in clock driver.
...@@ -138,20 +135,19 @@ void stm32mp1_syscfg_enable_io_compensation(void) ...@@ -138,20 +135,19 @@ void stm32mp1_syscfg_enable_io_compensation(void)
*/ */
stm32mp1_clk_enable_non_secure(SYSCFG); stm32mp1_clk_enable_non_secure(SYSCFG);
mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR, mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN); SYSCFG_CMPENSETR_MPU_EN);
while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) & while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
SYSCFG_CMPCR_READY) == 0U) { SYSCFG_CMPCR_READY) == 0U) {
; ;
} }
mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
} }
void stm32mp1_syscfg_disable_io_compensation(void) void stm32mp1_syscfg_disable_io_compensation(void)
{ {
uintptr_t syscfg_base = dt_get_syscfg_base();
uint32_t value; uint32_t value;
/* /*
...@@ -160,20 +156,18 @@ void stm32mp1_syscfg_disable_io_compensation(void) ...@@ -160,20 +156,18 @@ void stm32mp1_syscfg_disable_io_compensation(void)
* requested for other usages and always OFF in STANDBY. * requested for other usages and always OFF in STANDBY.
* Disable non-secure SYSCFG clock, we assume non-secure is suspended. * Disable non-secure SYSCFG clock, we assume non-secure is suspended.
*/ */
value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >> value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
SYSCFG_CMPCR_ANSRC_SHIFT; SYSCFG_CMPCR_ANSRC_SHIFT;
mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) | value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
(value << SYSCFG_CMPCR_RANSRC_SHIFT); (value << SYSCFG_CMPCR_RANSRC_SHIFT);
mmio_write_32(syscfg_base + SYSCFG_CMPCR, value); mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR, mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN); SYSCFG_CMPENSETR_MPU_EN);
stm32mp1_clk_disable_non_secure(SYSCFG); stm32mp1_clk_disable_non_secure(SYSCFG);
......
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