Merge pull request #1066 from islmit01/im/enable_cnp_bit

Enable CnP bit for ARMv8.2 CPUs 

docs/firmware-design.rst

@@ -2366,6 +2366,17 @@ This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
 -  The Compare and Swap instruction is used to implement spinlocks. Otherwise,
    the load-/store-exclusive instruction pair is used.
 
+ARMv8.2
+~~~~~~~
+
+This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and
+``ARM_ARCH_MINOR`` >= 2.
+
+-  The Common not Private (CnP) bit is enabled to indicate that multiple
+   Page Entries in the same Inner Shareable domain use the same translation
+   table entries for a given stage of translation for a particular translation
+   regime.
+
 Code Structure
 --------------
 

include/lib/aarch32/arch.h

@@ -322,6 +322,11 @@
 	((endian) & SPSR_E_MASK) << SPSR_E_SHIFT |	\
 	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
 
+/*
+ * TTBR definitions
+ */
+#define TTBR_CNP_BIT		0x1
+
 /*
  * CTR definitions
  */

include/lib/aarch64/arch.h

@@ -395,6 +395,11 @@
 	(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) |	\
 	(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
 
+/*
+ * TTBR Definitions
+ */
+#define TTBR_CNP_BIT		0x1
+
 /*
  * CTR_EL0 definitions
  */

include/lib/utils_def.h

@@ -73,4 +73,12 @@
 # define ULL(_x)	(_x##ull)
 #endif
 
+/*
+ * Test for the current architecture version to be at least the version
+ * expected.
+ */
+#define ARM_ARCH_AT_LEAST(_maj, _min) \
+	((ARM_ARCH_MAJOR > _maj) || \
+	 ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min)))
+
 #endif /* __UTILS_DEF_H__ */

lib/locks/exclusive/aarch64/spinlock.S

@@ -9,7 +9,7 @@
 	.globl	spin_lock
 	.globl	spin_unlock
 
-#if (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1))
+#if ARM_ARCH_AT_LEAST(8, 1)
 
 /*
  * When compiled for ARMv8.1 or later, choose spin locks based on Compare and

lib/xlat_tables_v2/aarch32/xlat_tables_arch.c

@@ -10,6 +10,7 @@
 #include <cassert.h>
 #include <platform_def.h>
 #include <utils.h>
+#include <utils_def.h>
 #include <xlat_tables_v2.h>
 #include "../xlat_tables_private.h"
 
@@ -153,6 +154,13 @@ void enable_mmu_arch(unsigned int flags,
 
 	/* Set TTBR0 bits as well */
 	ttbr0 = (uint64_t)(uintptr_t) base_table;
+#if ARM_ARCH_AT_LEAST(8, 2)
+	/*
+	 * Enable CnP bit so as to share page tables with all PEs.
+	 * Mandatory for ARMv8.2 implementations.
+	 */
+	ttbr0 |= TTBR_CNP_BIT;
+#endif
 
 	/* Now program the relevant system registers */
 	write_mair0(mair0);

lib/xlat_tables_v2/aarch64/xlat_tables_arch.c

@@ -13,6 +13,7 @@
 #include <platform_def.h>
 #include <sys/types.h>
 #include <utils.h>
+#include <utils_def.h>
 #include <xlat_tables_v2.h>
 #include "../xlat_tables_private.h"
 
@@ -166,6 +167,14 @@ uint64_t xlat_arch_get_xn_desc(int el)
 									\
 		write_mair_el##_el(mair);				\
 		write_tcr_el##_el(tcr);					\
+									\
+		/* Set TTBR bits as well */				\
+		if (ARM_ARCH_AT_LEAST(8, 2)) {				\
+			/* Enable CnP bit so as to share page tables */	\
+			/* with all PEs. This is mandatory for */	\
+			/* ARMv8.2 implementations. */			\
+			ttbr |= TTBR_CNP_BIT;				\
+		}							\
 		write_ttbr0_el##_el(ttbr);				\
 									\
 		/* Ensure all translation table writes have drained */	\