Merge changes from topic "bridge-en" into integration

* changes:
  intel: Add function to check fpga readiness
  intel: Add bridge control for FPGA reconfig
  intel: FPGA config_isdone() status query
  intel: System Manager refactoring
  intel: Refactor reset manager driver
  intel: Enable bridge access in Intel platform
  intel: Modify non secure access function

plat/intel/soc/stratix10/include/s10_reset_manager.h

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __S10_RESETMANAGER_H__
-#define __S10_RESETMANAGER_H__
-
-#define S10_RSTMGR_PER0MODRST				0xffd11024
-#define S10_RSTMGR_PER1MODRST				0xffd11028
-#define S10_RSTMGR_HDSKEN					0xffd11010
-
-#define S10_RSTMGR_PER0MODRST_EMAC0			0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1			0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2			0x00000004
-#define S10_RSTMGR_PER0MODRST_EMAC0OCP		0x00000100
-#define S10_RSTMGR_PER0MODRST_EMAC1OCP		0x00000200
-#define S10_RSTMGR_PER0MODRST_DMAOCP		0x00200000
-#define S10_RSTMGR_PER0MODRST_DMA			0x00010000
-#define S10_RSTMGR_PER0MODRST_EMAC0			0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1			0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2OCP		0x00000400
-#define S10_RSTMGR_PER0MODRST_EMAC2			0x00000004
-#define S10_RSTMGR_PER0MODRST_EMACPTP		0x00400000
-#define S10_RSTMGR_PER0MODRST_NANDOCP		0x00002000
-#define S10_RSTMGR_PER0MODRST_NAND			0x00000020
-#define S10_RSTMGR_PER0MODRST_SDMMCOCP		0x00008000
-#define S10_RSTMGR_PER0MODRST_SDMMC			0x00000080
-#define S10_RSTMGR_PER0MODRST_SPIM0			0x00020000
-#define S10_RSTMGR_PER0MODRST_SPIM1			0x00040000
-#define S10_RSTMGR_PER0MODRST_SPIS0			0x00080000
-#define S10_RSTMGR_PER0MODRST_SPIS1			0x00100000
-#define S10_RSTMGR_PER0MODRST_USB0OCP		0x00000800
-#define S10_RSTMGR_PER0MODRST_USB0			0x00000008
-#define S10_RSTMGR_PER0MODRST_USB1OCP		0x00001000
-#define S10_RSTMGR_PER0MODRST_USB1			0x00000010
-
-#define S10_RSTMGR_PER1MODRST_WATCHDOG0		0x1
-#define S10_RSTMGR_PER1MODRST_WATCHDOG1		0x2
-#define S10_RSTMGR_PER1MODRST_WATCHDOG2		0x4
-#define S10_RSTMGR_PER1MODRST_WATCHDOG3		0x8
-#define S10_RSTMGR_PER1MODRST_GPIO0			0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO0			0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO1			0x02000000
-#define S10_RSTMGR_PER1MODRST_GPIO1			0x02000000
-#define S10_RSTMGR_PER1MODRST_I2C0			0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C0			0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C1			0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C1			0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C2			0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C2			0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C3			0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C3			0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C4			0x00001000
-#define S10_RSTMGR_PER1MODRST_I2C4			0x00001000
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0	0x00000010
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1	0x00000020
-#define S10_RSTMGR_PER1MODRST_SPTIMER0		0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER0		0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER1		0x00000080
-#define S10_RSTMGR_PER1MODRST_SPTIMER1		0x00000080
-#define S10_RSTMGR_PER1MODRST_UART0			0x00010000
-#define S10_RSTMGR_PER1MODRST_UART0			0x00010000
-#define S10_RSTMGR_PER1MODRST_UART1			0x00020000
-#define S10_RSTMGR_PER1MODRST_UART1			0x00020000
-#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC		0x00020000
-#define S10_RSTMGR_HDSKEN_ETRSTALLEN		0x00000008
-#define S10_RSTMGR_HDSKEN_FPGAHSEN			0x00000004
-#define S10_RSTMGR_HDSKEN_L2FLUSHEN			0x00000100
-#define S10_RSTMGR_HDSKEN_L3NOC_DBG			0x00010000
-
-#define S10_RSTMGR_HDSKEN_SDRSELFREFEN		0x00000001
-#define S10_RSTMGR_PER0MODRST_DMAIF0		0x01000000
-#define S10_RSTMGR_PER0MODRST_DMAIF1		0x02000000
-#define S10_RSTMGR_PER0MODRST_DMAIF2		0x04000000
-#define S10_RSTMGR_PER0MODRST_DMAIF3		0x08000000
-#define S10_RSTMGR_PER0MODRST_DMAIF4		0x10000000
-#define S10_RSTMGR_PER0MODRST_DMAIF5		0x20000000
-#define S10_RSTMGR_PER0MODRST_DMAIF6		0x40000000
-#define S10_RSTMGR_PER0MODRST_DMAIF7		0x80000000
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-
-#endif
-

plat/intel/soc/stratix10/include/s10_system_manager.h

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
-#define S10_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
-#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
-#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
-#define S10_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
-#define S10_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
-#define S10_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
-#define S10_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
-#define S10_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
-#define S10_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
-#define S10_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
-#define S10_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
-#define S10_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
-#define S10_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
-#define S10_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
-#define S10_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
-#define S10_NOC_FW_L4_PER_SCR_UART1		0xffd21070
-
-#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
-#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
-#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
-#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
-#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
-#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
-#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
-#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
-#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
-#define S10_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
-#define S10_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
-#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
-#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
-#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
-#define S10_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
-
-#define S10_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
-#define S10_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
-
-#define S10_SYSMGR_CORE(x)			(0xffd12000 + (x))
-#define SYSMGR_MMC				0x28
-#define SYSMGR_MMC_DRVSEL(x)			(((x) & 0x7) << 0)
-#define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
-
-
-#define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
-

plat/intel/soc/stratix10/include/socfpga_plat_def.h

@@ -15,8 +15,14 @@
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE                    0xff808000
 
-#define SOCFPGA_RSTMGR_OFST                     0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST           0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
+
 
 #endif /* PLATSOCFPGA_DEF_H */
 

plat/intel/soc/stratix10/platform.mk

@@ -38,14 +38,14 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
 		plat/intel/soc/stratix10/soc/s10_memory_controller.c	\
 		plat/intel/soc/stratix10/soc/s10_pinmux.c		\
-		plat/intel/soc/stratix10/soc/s10_reset_manager.c	\
-		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
 		plat/intel/soc/common/socfpga_image_load.c		\
 		plat/intel/soc/common/socfpga_storage.c			\
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
+		plat/intel/soc/common/soc/socfpga_system_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 
@@ -59,6 +59,7 @@ BL31_SOURCES	+=	\
 		plat/intel/soc/common/socfpga_sip_svc.c			\
 		plat/intel/soc/common/socfpga_topology.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c
 
 PROGRAMMABLE_RESET_ADDRESS	:= 0
 BL2_AT_EL3			:= 1

plat/intel/soc/stratix10/soc/s10_clock_manager.c

@@ -12,8 +12,8 @@
 #include <platform_def.h>
 
 #include "s10_clock_manager.h"
-#include "s10_system_manager.h"
 #include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
 
 
 void wait_pll_lock(void)
@@ -190,9 +190,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
 			ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
 
 	/* Pass clock source frequency into scratch register */
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
 			hoff_ptr->hps_osc_clk_h);
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
 			hoff_ptr->fpga_clk_hz);
 
 }
@@ -205,14 +205,14 @@ uint32_t get_ref_clk(uint32_t pllglob)
 
 	switch (ALT_CLKMGR_PSRC(pllglob)) {
 	case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1:
-		scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC:
 		ref_clk = ALT_CLKMGR_INTOSC_HZ;
 		break;
 	case ALT_CLKMGR_PLLGLOB_PSRC_F2S:
-		scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	default:

plat/intel/soc/stratix10/soc/s10_memory_controller.c

@@ -15,6 +15,7 @@
 #include <string.h>
 
 #include "s10_memory_controller.h"
+#include "socfpga_reset_manager.h"
 
 #define ALT_CCU_NOC_DI_SET_MSK 0x10
 
@@ -184,7 +185,7 @@ int init_hard_memory_controller(void)
 		return status;
 	}
 
-	mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH);
+	mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_FIELD(BRG, DDRSCH));
 
 	status = mem_calibration();
 	if (status) {

plat/intel/soc/stratix10/soc/s10_reset_manager.c

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-#include "s10_reset_manager.h"
-
-void deassert_peripheral_reset(void)
-{
-	mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
-			S10_RSTMGR_PER1MODRST_WATCHDOG0 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG1 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG2 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG3 |
-			S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
-			S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
-			S10_RSTMGR_PER1MODRST_SPTIMER0 |
-			S10_RSTMGR_PER1MODRST_SPTIMER1 |
-			S10_RSTMGR_PER1MODRST_I2C0 |
-			S10_RSTMGR_PER1MODRST_I2C1 |
-			S10_RSTMGR_PER1MODRST_I2C2 |
-			S10_RSTMGR_PER1MODRST_I2C3 |
-			S10_RSTMGR_PER1MODRST_I2C4 |
-			S10_RSTMGR_PER1MODRST_UART0 |
-			S10_RSTMGR_PER1MODRST_UART1 |
-			S10_RSTMGR_PER1MODRST_GPIO0 |
-			S10_RSTMGR_PER1MODRST_GPIO1);
-
-	mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
-			S10_RSTMGR_PER0MODRST_EMAC0OCP |
-			S10_RSTMGR_PER0MODRST_EMAC1OCP |
-			S10_RSTMGR_PER0MODRST_EMAC2OCP |
-			S10_RSTMGR_PER0MODRST_USB0OCP |
-			S10_RSTMGR_PER0MODRST_USB1OCP |
-			S10_RSTMGR_PER0MODRST_NANDOCP |
-			S10_RSTMGR_PER0MODRST_SDMMCOCP |
-			S10_RSTMGR_PER0MODRST_DMAOCP);
-
-	mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
-			S10_RSTMGR_PER0MODRST_EMAC0 |
-			S10_RSTMGR_PER0MODRST_EMAC1 |
-			S10_RSTMGR_PER0MODRST_EMAC2 |
-			S10_RSTMGR_PER0MODRST_USB0 |
-			S10_RSTMGR_PER0MODRST_USB1 |
-			S10_RSTMGR_PER0MODRST_NAND |
-			S10_RSTMGR_PER0MODRST_SDMMC |
-			S10_RSTMGR_PER0MODRST_DMA |
-			S10_RSTMGR_PER0MODRST_SPIM0 |
-			S10_RSTMGR_PER0MODRST_SPIM1 |
-			S10_RSTMGR_PER0MODRST_SPIS0 |
-			S10_RSTMGR_PER0MODRST_SPIS1 |
-			S10_RSTMGR_PER0MODRST_EMACPTP |
-			S10_RSTMGR_PER0MODRST_DMAIF0 |
-			S10_RSTMGR_PER0MODRST_DMAIF1 |
-			S10_RSTMGR_PER0MODRST_DMAIF2 |
-			S10_RSTMGR_PER0MODRST_DMAIF3 |
-			S10_RSTMGR_PER0MODRST_DMAIF4 |
-			S10_RSTMGR_PER0MODRST_DMAIF5 |
-			S10_RSTMGR_PER0MODRST_DMAIF6 |
-			S10_RSTMGR_PER0MODRST_DMAIF7);
-
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
-	uint32_t or_mask = 0;
-
-	or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
-	or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
-	or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
-	or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
-	or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
-	or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
-	mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
-}
-

plat/intel/soc/stratix10/soc/s10_system_manager.c

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-#include "s10_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
-		DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-
-	mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
-	mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
-
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
-
-}
-