Merge changes from topic "rk3399q7" into integration

* changes:
  rockchip: Allow console device to be set by DTB.
  rockchip: Add params_setup to RK3328.
  rockchip: Streamline and complete UARTn_BASE macros.

plat/rockchip/common/bl31_plat_setup.c

@@ -78,7 +78,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				       coreboot_serial.baud,
 				       &console);
 #else
-	console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
+	console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
 			       PLAT_RK_UART_BAUDRATE, &console);
 #endif
 

plat/rockchip/common/include/plat_private.h

@@ -146,6 +146,8 @@ extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
 
 extern const mmap_region_t plat_rk_mmap[];
 
+uint32_t rockchip_get_uart_base(void);
+
 #endif /* __ASSEMBLY__ */
 
 /******************************************************************************

plat/rockchip/common/params_setup.c

@@ -28,6 +28,12 @@ static struct gpio_info *poweroff_gpio;
 static struct gpio_info suspend_gpio[10];
 uint32_t suspend_gpio_cnt;
 static struct apio_info *suspend_apio;
+static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
+
+uint32_t rockchip_get_uart_base(void)
+{
+	return rk_uart_base;
+}
 
 #if COREBOOT
 static int dt_process_fdt(void *blob)
@@ -42,6 +48,63 @@ void *plat_get_fdt(void)
 	return &fdt_buffer[0];
 }
 
+static void plat_rockchip_dt_process_fdt_uart(void *fdt)
+{
+	const char *path_name = "/chosen";
+	const char *prop_name = "stdout-path";
+	int node_offset;
+	int stdout_path_len;
+	const char *stdout_path;
+	char serial_char;
+	int serial_no;
+	uint32_t uart_base;
+
+	node_offset = fdt_path_offset(fdt, path_name);
+	if (node_offset < 0)
+		return;
+
+	stdout_path = fdt_getprop(fdt, node_offset, prop_name,
+				  &stdout_path_len);
+	if (stdout_path == NULL)
+		return;
+
+	/*
+	 * We expect something like:
+	 *   "serial0:...""
+	 */
+	if (strncmp("serial", stdout_path, 6) != 0)
+		return;
+
+	serial_char = stdout_path[6];
+	serial_no = serial_char - '0';
+
+	switch (serial_no) {
+	case 0:
+		uart_base = UART0_BASE;
+		break;
+	case 1:
+		uart_base = UART1_BASE;
+		break;
+	case 2:
+		uart_base = UART2_BASE;
+		break;
+#ifdef UART3_BASE
+	case 3:
+		uart_base = UART3_BASE;
+		break;
+#endif
+#ifdef UART4_BASE
+	case 4:
+		uart_base = UART4_BASE;
+		break;
+#endif
+	default:
+		return;
+	}
+
+	rk_uart_base = uart_base;
+}
+
 static int dt_process_fdt(void *blob)
 {
 	void *fdt = plat_get_fdt();
@@ -51,6 +114,8 @@ static int dt_process_fdt(void *blob)
 	if (ret < 0)
 		return ret;
 
+	plat_rockchip_dt_process_fdt_uart(fdt);
+
 	return 0;
 }
 #endif

plat/rockchip/common/sp_min_plat_setup.c

@@ -65,7 +65,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				       coreboot_serial.baud,
 				       &console);
 #else
-	console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
+	console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
 			       PLAT_RK_UART_BAUDRATE, &console);
 #endif
 	VERBOSE("sp_min_setup\n");

plat/rockchip/rk3288/drivers/soc/soc.c

@@ -34,7 +34,15 @@ const mmap_region_t plat_rk_mmap[] = {
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE,
+	MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART3_BASE, UART3_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART4_BASE, UART4_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),

plat/rockchip/rk3288/include/platform_def.h

@@ -87,7 +87,7 @@
 #define PLAT_RK_GICD_BASE		RK3288_GICD_BASE
 #define PLAT_RK_GICC_BASE		RK3288_GICC_BASE
 
-#define PLAT_RK_UART_BASE		RK3288_UART2_BASE
+#define PLAT_RK_UART_BASE		UART2_BASE
 #define PLAT_RK_UART_CLOCK		RK3288_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE		RK3288_BAUDRATE
 

plat/rockchip/rk3288/rk3288_def.h

@@ -28,8 +28,20 @@
 #define DDR_PHY1_BASE		0xff640000
 #define DDR_PHY1_SIZE		SIZE_K(64)
 
-#define UART_DBG_BASE		0xff690000
-#define UART_DBG_SIZE		SIZE_K(64)
+#define UART0_BASE		0xff180000
+#define UART0_SIZE		SIZE_K(64)
+
+#define UART1_BASE		0xff190000
+#define UART1_SIZE		SIZE_K(64)
+
+#define UART2_BASE		0xff690000
+#define UART2_SIZE		SIZE_K(64)
+
+#define UART3_BASE		0xff1b0000
+#define UART3_SIZE		SIZE_K(64)
+
+#define UART4_BASE		0xff1c0000
+#define UART4_SIZE		SIZE_K(64)
 
 /* 96k instead of 64k? */
 #define SRAM_BASE		0xff700000
@@ -71,7 +83,6 @@
 /**************************************************************************
  * UART related constants
  **************************************************************************/
-#define RK3288_UART2_BASE	UART_DBG_BASE
 #define RK3288_BAUDRATE		115200
 #define RK3288_UART_CLOCK	24000000
 

plat/rockchip/rk3328/drivers/soc/soc.c

@@ -19,6 +19,10 @@
 
 /* Table of regions to map using the MMU. */
 const mmap_region_t plat_rk_mmap[] = {
+	MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,

plat/rockchip/rk3328/include/platform_def.h

@@ -105,7 +105,7 @@
 #define PLAT_RK_GICD_BASE	RK3328_GICD_BASE
 #define PLAT_RK_GICC_BASE	RK3328_GICC_BASE
 
-#define PLAT_RK_UART_BASE	RK3328_UART2_BASE
+#define PLAT_RK_UART_BASE	UART2_BASE
 #define PLAT_RK_UART_CLOCK	RK3328_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE	RK3328_BAUDRATE
 

plat/rockchip/rk3328/platform.mk

@@ -40,6 +40,7 @@ BL31_SOURCES		+=	${RK_GIC_SOURCES}				\
 				lib/cpus/aarch64/cortex_a53.S			\
 				${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c	\
 				${RK_PLAT_COMMON}/aarch64/plat_helpers.S	\
+				${RK_PLAT_COMMON}/params_setup.c		\
 				${RK_PLAT_COMMON}/bl31_plat_setup.c		\
 				${RK_PLAT_COMMON}/aarch64/pmu_sram_cpus_on.S	\
 				${RK_PLAT_COMMON}/plat_pm.c			\

plat/rockchip/rk3328/rk3328_def.h

@@ -15,6 +15,12 @@
 /* Special value used to verify platform parameters from BL2 to BL3-1 */
 #define RK_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
 
+#define UART0_BASE		0xff110000
+#define UART0_SIZE		SIZE_K(64)
+
+#define UART1_BASE		0xff120000
+#define UART1_SIZE		SIZE_K(64)
+
 #define UART2_BASE		0xff130000
 #define UART2_SIZE		SIZE_K(64)
 
@@ -97,7 +103,6 @@
 /**************************************************************************
  * UART related constants
  **************************************************************************/
-#define RK3328_UART2_BASE	UART2_BASE
 #define RK3328_BAUDRATE	1500000
 #define RK3328_UART_CLOCK	24000000
 

plat/rockchip/rk3368/drivers/soc/soc.c

@@ -30,7 +30,15 @@ const mmap_region_t plat_rk_mmap[] = {
 			MT_MEMORY | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE,
+	MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART3_BASE, UART3_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(UART4_BASE, UART4_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),

plat/rockchip/rk3368/include/platform_def.h

@@ -106,7 +106,7 @@
 #define PLAT_RK_GICD_BASE	RK3368_GICD_BASE
 #define PLAT_RK_GICC_BASE	RK3368_GICC_BASE
 
-#define PLAT_RK_UART_BASE	RK3368_UART2_BASE
+#define PLAT_RK_UART_BASE	UART2_BASE
 #define PLAT_RK_UART_CLOCK	RK3368_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE	RK3368_BAUDRATE
 

plat/rockchip/rk3368/rk3368_def.h

@@ -35,8 +35,20 @@
 #define RK_INTMEM_BASE		0xff8c0000
 #define RK_INTMEM_SIZE		0x10000
 
-#define UART_DBG_BASE		0xff690000
-#define UART_DBG_SIZE		0x10000
+#define UART0_BASE		0xff180000
+#define UART0_SIZE		0x10000
+
+#define UART1_BASE		0xff190000
+#define UART1_SIZE		0x10000
+
+#define UART2_BASE		0xff690000
+#define UART2_SIZE		0x10000
+
+#define UART3_BASE		0xff1b0000
+#define UART3_SIZE		0x10000
+
+#define UART4_BASE		0xff1c0000
+#define UART4_SIZE		0x10000
 
 #define CRU_BASE		0xff760000
 
@@ -57,7 +69,6 @@
 /**************************************************************************
  * UART related constants
  **************************************************************************/
-#define RK3368_UART2_BASE	UART_DBG_BASE
 #define RK3368_BAUDRATE		115200
 #define RK3368_UART_CLOCK	24000000