Merge pull request #1250 from jollysxilinx/zynqmp-new-eemi-api

plat/xilinx: Add support for new platform management APIs for ZynqMP

plat/xilinx/zynqmp/include/platform_def.h

@@ -34,9 +34,14 @@
  * little space for growth.
  */
 #ifndef ZYNQMP_ATF_MEM_BASE
+#if !DEBUG
 # define BL31_BASE			0xfffea000
 # define BL31_LIMIT			0xffffffff
 #else
+# define BL31_BASE			0x1000
+# define BL31_LIMIT			0x7ffff
+#endif
+#else
 # define BL31_BASE			(ZYNQMP_ATF_MEM_BASE)
 # define BL31_LIMIT			(ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE

plat/xilinx/zynqmp/platform.mk

 #
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -77,6 +77,9 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				plat/xilinx/zynqmp/zynqmp_ipi.c		\
 				plat/xilinx/zynqmp/pm_service/pm_svc_main.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_sys.c	\
+				plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c	\
+				plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c	\
+				plat/xilinx/zynqmp/pm_service/pm_api_clock.c	\
 				plat/xilinx/zynqmp/pm_service/pm_ipi.c		\
 				plat/xilinx/zynqmp/pm_service/pm_client.c	\
 				plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c

plat/xilinx/zynqmp/pm_service/pm_api_clock.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for clock control.
+ */
+
+#ifndef _PM_API_CLOCK_H_
+#define _PM_API_CLOCK_H_
+
+#include <utils_def.h>
+#include "pm_common.h"
+
+#define CLK_NAME_LEN		U(15)
+#define MAX_PARENTS		U(100)
+#define CLK_NA_PARENT		-1
+#define CLK_DUMMY_PARENT	-2
+
+/* Flags for parent id */
+#define PARENT_CLK_SELF		U(0)
+#define PARENT_CLK_NODE1	U(1)
+#define PARENT_CLK_NODE2	U(2)
+#define PARENT_CLK_NODE3	U(3)
+#define PARENT_CLK_NODE4	U(4)
+#define PARENT_CLK_EXTERNAL	U(5)
+#define PARENT_CLK_MIO0_MIO77	U(6)
+
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+/* unused */
+#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
+#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
+#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
+#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE	BIT(12)
+#define CLK_FRAC		BIT(13)
+
+#define CLK_DIVIDER_ONE_BASED		BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
+#define CLK_DIVIDER_READ_ONLY		BIT(5)
+#define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
+
+#define END_OF_CLK     "END_OF_CLK"
+
+//CLock Ids
+enum {
+	CLK_IOPLL,
+	CLK_RPLL,
+	CLK_APLL,
+	CLK_DPLL,
+	CLK_VPLL,
+	CLK_IOPLL_TO_FPD,
+	CLK_RPLL_TO_FPD,
+	CLK_APLL_TO_LPD,
+	CLK_DPLL_TO_LPD,
+	CLK_VPLL_TO_LPD,
+	CLK_ACPU,
+	CLK_ACPU_HALF,
+	CLK_DBG_FPD,
+	CLK_DBG_LPD,
+	CLK_DBG_TRACE,
+	CLK_DBG_TSTMP,
+	CLK_DP_VIDEO_REF,
+	CLK_DP_AUDIO_REF,
+	CLK_DP_STC_REF,
+	CLK_GDMA_REF,
+	CLK_DPDMA_REF,
+	CLK_DDR_REF,
+	CLK_SATA_REF,
+	CLK_PCIE_REF,
+	CLK_GPU_REF,
+	CLK_GPU_PP0_REF,
+	CLK_GPU_PP1_REF,
+	CLK_TOPSW_MAIN,
+	CLK_TOPSW_LSBUS,
+	CLK_GTGREF0_REF,
+	CLK_LPD_SWITCH,
+	CLK_LPD_LSBUS,
+	CLK_USB0_BUS_REF,
+	CLK_USB1_BUS_REF,
+	CLK_USB3_DUAL_REF,
+	CLK_USB0,
+	CLK_USB1,
+	CLK_CPU_R5,
+	CLK_CPU_R5_CORE,
+	CLK_CSU_SPB,
+	CLK_CSU_PLL,
+	CLK_PCAP,
+	CLK_IOU_SWITCH,
+	CLK_GEM_TSU_REF,
+	CLK_GEM_TSU,
+	CLK_GEM0_REF,
+	CLK_GEM1_REF,
+	CLK_GEM2_REF,
+	CLK_GEM3_REF,
+	CLK_GEM0_TX,
+	CLK_GEM1_TX,
+	CLK_GEM2_TX,
+	CLK_GEM3_TX,
+	CLK_QSPI_REF,
+	CLK_SDIO0_REF,
+	CLK_SDIO1_REF,
+	CLK_UART0_REF,
+	CLK_UART1_REF,
+	CLK_SPI0_REF,
+	CLK_SPI1_REF,
+	CLK_NAND_REF,
+	CLK_I2C0_REF,
+	CLK_I2C1_REF,
+	CLK_CAN0_REF,
+	CLK_CAN1_REF,
+	CLK_CAN0,
+	CLK_CAN1,
+	CLK_DLL_REF,
+	CLK_ADMA_REF,
+	CLK_TIMESTAMP_REF,
+	CLK_AMS_REF,
+	CLK_PL0_REF,
+	CLK_PL1_REF,
+	CLK_PL2_REF,
+	CLK_PL3_REF,
+	CLK_WDT,
+	CLK_IOPLL_INT,
+	CLK_IOPLL_PRE_SRC,
+	CLK_IOPLL_HALF,
+	CLK_IOPLL_INT_MUX,
+	CLK_IOPLL_POST_SRC,
+	CLK_RPLL_INT,
+	CLK_RPLL_PRE_SRC,
+	CLK_RPLL_HALF,
+	CLK_RPLL_INT_MUX,
+	CLK_RPLL_POST_SRC,
+	CLK_APLL_INT,
+	CLK_APLL_PRE_SRC,
+	CLK_APLL_HALF,
+	CLK_APLL_INT_MUX,
+	CLK_APLL_POST_SRC,
+	CLK_DPLL_INT,
+	CLK_DPLL_PRE_SRC,
+	CLK_DPLL_HALF,
+	CLK_DPLL_INT_MUX,
+	CLK_DPLL_POST_SRC,
+	CLK_VPLL_INT,
+	CLK_VPLL_PRE_SRC,
+	CLK_VPLL_HALF,
+	CLK_VPLL_INT_MUX,
+	CLK_VPLL_POST_SRC,
+	CLK_CAN0_MIO,
+	CLK_CAN1_MIO,
+	END_OF_OUTPUT_CLKS,
+};
+
+#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
+
+//External clock ids
+enum {
+	EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
+	EXT_CLK_VIDEO,
+	EXT_CLK_PSS_ALT_REF,
+	EXT_CLK_AUX_REF,
+	EXT_CLK_GT_CRX_REF,
+	EXT_CLK_SWDT0,
+	EXT_CLK_SWDT1,
+	EXT_CLK_GEM0_EMIO,
+	EXT_CLK_GEM1_EMIO,
+	EXT_CLK_GEM2_EMIO,
+	EXT_CLK_GEM3_EMIO,
+	EXT_CLK_MIO50_OR_MIO51,
+	EXT_CLK_MIO0,
+	EXT_CLK_MIO1,
+	EXT_CLK_MIO2,
+	EXT_CLK_MIO3,
+	EXT_CLK_MIO4,
+	EXT_CLK_MIO5,
+	EXT_CLK_MIO6,
+	EXT_CLK_MIO7,
+	EXT_CLK_MIO8,
+	EXT_CLK_MIO9,
+	EXT_CLK_MIO10,
+	EXT_CLK_MIO11,
+	EXT_CLK_MIO12,
+	EXT_CLK_MIO13,
+	EXT_CLK_MIO14,
+	EXT_CLK_MIO15,
+	EXT_CLK_MIO16,
+	EXT_CLK_MIO17,
+	EXT_CLK_MIO18,
+	EXT_CLK_MIO19,
+	EXT_CLK_MIO20,
+	EXT_CLK_MIO21,
+	EXT_CLK_MIO22,
+	EXT_CLK_MIO23,
+	EXT_CLK_MIO24,
+	EXT_CLK_MIO25,
+	EXT_CLK_MIO26,
+	EXT_CLK_MIO27,
+	EXT_CLK_MIO28,
+	EXT_CLK_MIO29,
+	EXT_CLK_MIO30,
+	EXT_CLK_MIO31,
+	EXT_CLK_MIO32,
+	EXT_CLK_MIO33,
+	EXT_CLK_MIO34,
+	EXT_CLK_MIO35,
+	EXT_CLK_MIO36,
+	EXT_CLK_MIO37,
+	EXT_CLK_MIO38,
+	EXT_CLK_MIO39,
+	EXT_CLK_MIO40,
+	EXT_CLK_MIO41,
+	EXT_CLK_MIO42,
+	EXT_CLK_MIO43,
+	EXT_CLK_MIO44,
+	EXT_CLK_MIO45,
+	EXT_CLK_MIO46,
+	EXT_CLK_MIO47,
+	EXT_CLK_MIO48,
+	EXT_CLK_MIO49,
+	EXT_CLK_MIO50,
+	EXT_CLK_MIO51,
+	EXT_CLK_MIO52,
+	EXT_CLK_MIO53,
+	EXT_CLK_MIO54,
+	EXT_CLK_MIO55,
+	EXT_CLK_MIO56,
+	EXT_CLK_MIO57,
+	EXT_CLK_MIO58,
+	EXT_CLK_MIO59,
+	EXT_CLK_MIO60,
+	EXT_CLK_MIO61,
+	EXT_CLK_MIO62,
+	EXT_CLK_MIO63,
+	EXT_CLK_MIO64,
+	EXT_CLK_MIO65,
+	EXT_CLK_MIO66,
+	EXT_CLK_MIO67,
+	EXT_CLK_MIO68,
+	EXT_CLK_MIO69,
+	EXT_CLK_MIO70,
+	EXT_CLK_MIO71,
+	EXT_CLK_MIO72,
+	EXT_CLK_MIO73,
+	EXT_CLK_MIO74,
+	EXT_CLK_MIO75,
+	EXT_CLK_MIO76,
+	EXT_CLK_MIO77,
+	END_OF_CLKS,
+};
+
+#define CLK_MAX (unsigned int)(END_OF_CLKS)
+
+//CLock types
+#define CLK_TYPE_OUTPUT 0U
+#define	CLK_TYPE_EXTERNAL  1U
+
+//Topology types
+#define TYPE_INVALID 0U
+#define	TYPE_MUX 1U
+#define	TYPE_PLL 2U
+#define	TYPE_FIXEDFACTOR 3U
+#define	TYPE_DIV1 4U
+#define	TYPE_DIV2 5U
+#define	TYPE_GATE 6U
+
+
+enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
+enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
+					     unsigned int index,
+					     uint32_t *topology);
+enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
+						       uint32_t *mul,
+						       uint32_t *div);
+enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
+					    unsigned int index,
+					    uint32_t *parents);
+enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
+					       uint32_t *attr);
+enum pm_ret_status pm_api_clock_enable(unsigned int clock_id);
+enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
+enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
+					 unsigned int *state);
+enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
+					   unsigned int divider);
+enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
+					   unsigned int *divider);
+enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id,
+					uint64_t rate);
+enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id,
+					uint64_t *rate);
+enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id,
+					  unsigned int parent_idx);
+enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id,
+					  unsigned int *parent_idx);
+enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll,
+					   unsigned int mode);
+enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll,
+					   unsigned int *mode);
+enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
+						unsigned int data);
+enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
+						unsigned int *data);
+
+#endif /* _PM_API_CLOCK_H_ */

plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for ioctl.
+ */
+
+#include <arch_helpers.h>
+#include <delay_timer.h>
+#include <mmio.h>
+#include <platform.h>
+#include "pm_api_clock.h"
+#include "pm_api_ioctl.h"
+#include "pm_api_sys.h"
+#include "pm_client.h"
+#include "pm_common.h"
+#include "pm_ipi.h"
+#include "../zynqmp_def.h"
+
+/**
+ * pm_ioctl_get_rpu_oper_mode () - Get current RPU operation mode
+ * @mode	Buffer to store value of oper mode(Split/Lock-step)
+ *
+ * This function provides current configured RPU operational mode.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(unsigned int *mode)
+{
+	unsigned int val;
+
+	val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
+	val &= ZYNQMP_SLSPLIT_MASK;
+	if (val == 0)
+		*mode = PM_RPU_MODE_LOCKSTEP;
+	else
+		*mode = PM_RPU_MODE_SPLIT;
+
+	return PM_RET_SUCCESS;
+}
+
+/**
+ * pm_ioctl_set_rpu_oper_mode () - Configure RPU operation mode
+ * @mode	Value to set for oper mode(Split/Lock-step)
+ *
+ * This function configures RPU operational mode(Split/Lock-step).
+ * It also sets TCM combined mode in RPU lock-step and TCM non-combined
+ * mode for RPU split mode. In case of Lock step mode, RPU1's output is
+ * clamped.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode)
+{
+	unsigned int val;
+
+	if (mmio_read_32(CRL_APB_RST_LPD_TOP) && CRL_APB_RPU_AMBA_RESET)
+		return PM_RET_ERROR_ACCESS;
+
+	val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
+
+	if (mode == PM_RPU_MODE_SPLIT) {
+		val |= ZYNQMP_SLSPLIT_MASK;
+		val &= ~ZYNQMP_TCM_COMB_MASK;
+		val &= ~ZYNQMP_SLCLAMP_MASK;
+	} else if (mode == PM_RPU_MODE_LOCKSTEP) {
+		val &= ~ZYNQMP_SLSPLIT_MASK;
+		val |= ZYNQMP_TCM_COMB_MASK;
+		val |= ZYNQMP_SLCLAMP_MASK;
+	} else {
+		return PM_RET_ERROR_ARGS;
+	}
+
+	mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
+
+	return PM_RET_SUCCESS;
+}
+
+/**
+ * pm_ioctl_config_boot_addr() - Configure RPU boot address
+ * @nid		Node ID of RPU
+ * @value	Value to set for boot address (TCM/OCM)
+ *
+ * This function configures RPU boot address(memory).
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid,
+						    unsigned int value)
+{
+	unsigned int rpu_cfg_addr, val;
+
+	if (nid == NODE_RPU_0)
+		rpu_cfg_addr = ZYNQMP_RPU0_CFG;
+	else if (nid == NODE_RPU_1)
+		rpu_cfg_addr = ZYNQMP_RPU1_CFG;
+	else
+		return PM_RET_ERROR_ARGS;
+
+	val = mmio_read_32(rpu_cfg_addr);
+
+	if (value == PM_RPU_BOOTMEM_LOVEC)
+		val &= ~ZYNQMP_VINITHI_MASK;
+	else if (value == PM_RPU_BOOTMEM_HIVEC)
+		val |= ZYNQMP_VINITHI_MASK;
+	else
+		return PM_RET_ERROR_ARGS;
+
+	mmio_write_32(rpu_cfg_addr, val);
+
+	return PM_RET_SUCCESS;
+}
+
+/**
+ * pm_ioctl_config_tcm_comb() - Configure TCM combined mode
+ * @value	Value to set (Split/Combined)
+ *
+ * This function configures TCM to be in split mode or combined
+ * mode.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value)
+{
+	unsigned int val;
+
+	val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
+
+	if (value == PM_RPU_TCM_SPLIT)
+		val &= ~ZYNQMP_TCM_COMB_MASK;
+	else if (value == PM_RPU_TCM_COMB)
+		val |= ZYNQMP_TCM_COMB_MASK;
+	else
+		return PM_RET_ERROR_ARGS;
+
+	mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
+
+	return PM_RET_SUCCESS;
+}
+
+/**
+ * pm_ioctl_set_tapdelay_bypass() -  Enable/Disable tap delay bypass
+ * @type	Type of tap delay to enable/disable (e.g. QSPI)
+ * @value	Enable/Disable
+ *
+ * This function enable/disable tap delay bypass.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type,
+						       unsigned int value)
+{
+	if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
+	     value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX)
+		return PM_RET_ERROR_ARGS;
+
+	return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
+}
+
+/**
+ * pm_ioctl_set_sgmii_mode() -  Set SGMII mode for the GEM device
+ * @nid		Node ID of the device
+ * @value	Enable/Disable
+ *
+ * This function enable/disable SGMII mode for the GEM device.
+ * While enabling SGMII mode, it also ties the GEM PCS Signal
+ * Detect to 1 and selects EMIO for RX clock generation.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
+						  unsigned int value)
+{
+	unsigned int val, mask, shift;
+	enum pm_ret_status ret;
+
+	if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE)
+		return PM_RET_ERROR_ARGS;
+
+	switch (nid) {
+	case NODE_ETH_0:
+		shift = 0;
+		break;
+	case NODE_ETH_1:
+		shift = 1;
+		break;
+	case NODE_ETH_2:
+		shift = 2;
+		break;
+	case NODE_ETH_3:
+		shift = 3;
+		break;
+	default:
+		return PM_RET_ERROR_ARGS;
+	}
+
+	if (value == PM_SGMII_DISABLE) {
+		mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
+		ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U);
+	} else {
+		/* Tie the GEM PCS Signal Detect to 1 */
+		mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
+		val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
+		ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
+		if (ret != PM_RET_SUCCESS)
+			return ret;
+
+		/* Set the GEM to SGMII mode */
+		mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
+		val = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
+		val <<= GEM_CLK_CTRL_OFFSET * shift;
+		ret =  pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val);
+	}
+
+	return ret;
+}
+
+/**
+ * pm_ioctl_sd_dll_reset() -  Reset DLL logic
+ * @nid		Node ID of the device
+ * @type	Reset type
+ *
+ * This function resets DLL logic for the SD device.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid,
+						unsigned int type)
+{
+	unsigned int mask, val;
+	enum pm_ret_status ret;
+
+	if (nid == NODE_SD_0) {
+		mask = ZYNQMP_SD0_DLL_RST_MASK;
+		val = ZYNQMP_SD0_DLL_RST;
+	} else if (nid == NODE_SD_1) {
+		mask = ZYNQMP_SD1_DLL_RST_MASK;
+		val = ZYNQMP_SD1_DLL_RST;
+	} else {
+		return PM_RET_ERROR_ARGS;
+	}
+
+	switch (type) {
+	case PM_DLL_RESET_ASSERT:
+	case PM_DLL_RESET_PULSE:
+		ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
+		if (ret != PM_RET_SUCCESS)
+			return ret;
+
+		if (type == PM_DLL_RESET_ASSERT)
+			break;
+		mdelay(1);
+	case PM_DLL_RESET_RELEASE:
+		ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0);
+		break;
+	default:
+		ret = PM_RET_ERROR_ARGS;
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * pm_ioctl_sd_set_tapdelay() -  Set tap delay for the SD device
+ * @nid		Node ID of the device
+ * @type	Type of tap delay to set (input/output)
+ * @value	Value to set fot the tap delay
+ *
+ * This function sets input/output tap delay for the SD device.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
+						   enum tap_delay_type type,
+						   unsigned int value)
+{
+	unsigned int shift;
+	enum pm_ret_status ret;
+
+	if (nid == NODE_SD_0)
+		shift = 0;
+	else if (nid == NODE_SD_1)
+		shift = ZYNQMP_SD_TAP_OFFSET;
+	else
+		return PM_RET_ERROR_ARGS;
+
+	ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
+	if (ret != PM_RET_SUCCESS)
+		return ret;
+
+	if (type == PM_TAPDELAY_INPUT) {
+		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+				    (ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
+				    (ZYNQMP_SD_ITAPCHGWIN << shift));
+		if (ret != PM_RET_SUCCESS)
+			goto reset_release;
+		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+				    (ZYNQMP_SD_ITAPDLYENA_MASK << shift),
+				    (ZYNQMP_SD_ITAPDLYENA << shift));
+		if (ret != PM_RET_SUCCESS)
+			goto reset_release;
+		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+				    (ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
+				    (value << shift));
+		if (ret != PM_RET_SUCCESS)
+			goto reset_release;
+		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+				    (ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
+	} else if (type == PM_TAPDELAY_OUTPUT) {
+		ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
+				    (ZYNQMP_SD_OTAPDLYENA_MASK << shift),
+				    (ZYNQMP_SD_OTAPDLYENA << shift));
+		if (ret != PM_RET_SUCCESS)
+			goto reset_release;
+		ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
+				    (ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
+				    (value << shift));
+	} else {
+		ret = PM_RET_ERROR_ARGS;
+	}
+
+reset_release:
+	pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
+	return ret;
+}
+
+/**
+ * pm_ioctl_set_pll_frac_mode() -  Ioctl function for
+ *				   setting pll mode
+ * @pll     PLL id
+ * @mode    Mode fraction/integar
+ *
+ * This function sets PLL mode
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_pll_frac_mode
+			(unsigned int pll, unsigned int mode)
+{
+	return pm_api_clk_set_pll_mode(pll, mode);
+}
+
+/**
+ * pm_ioctl_get_pll_frac_mode() -  Ioctl function for
+ *				   getting pll mode
+ * @pll     PLL id
+ * @mode    Mode fraction/integar
+ *
+ * This function return current PLL mode
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_get_pll_frac_mode
+			(unsigned int pll, unsigned int *mode)
+{
+	return pm_api_clk_get_pll_mode(pll, mode);
+}
+
+/**
+ * pm_ioctl_set_pll_frac_data() -  Ioctl function for
+ *				   setting pll fraction data
+ * @pll     PLL id
+ * @data    fraction data
+ *
+ * This function sets fraction data.
+ * It is valid for fraction mode only.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_pll_frac_data
+			(unsigned int pll, unsigned int data)
+{
+	return pm_api_clk_set_pll_frac_data(pll, data);
+}
+
+/**
+ * pm_ioctl_get_pll_frac_data() -  Ioctl function for
+ *				   getting pll fraction data
+ * @pll     PLL id
+ * @data    fraction data
+ *
+ * This function returns fraction data value.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_get_pll_frac_data
+			(unsigned int pll, unsigned int *data)
+{
+	return pm_api_clk_get_pll_frac_data(pll, data);
+}
+
+/**
+ * pm_ioctl_write_ggs() - Ioctl function for writing
+ *			  global general storage (ggs)
+ * @index	GGS register index
+ * @value	Register value to be written
+ *
+ * This function writes value to GGS register.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index,
+					     unsigned int value)
+{
+	if (index >= GGS_NUM_REGS)
+		return PM_RET_ERROR_ARGS;
+
+	return pm_mmio_write(GGS_BASEADDR + (index << 2),
+			     0xFFFFFFFFU, value);
+}
+
+/**
+ * pm_ioctl_read_ggs() - Ioctl function for reading
+ *			 global general storage (ggs)
+ * @index	GGS register index
+ * @value	Register value
+ *
+ * This function returns GGS register value.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index,
+					    unsigned int *value)
+{
+	if (index >= GGS_NUM_REGS)
+		return PM_RET_ERROR_ARGS;
+
+	return pm_mmio_read(GGS_BASEADDR + (index << 2), value);
+}
+
+/**
+ * pm_ioctl_write_pggs() - Ioctl function for writing persistent
+ *			   global general storage (pggs)
+ * @index	PGGS register index
+ * @value	Register value to be written
+ *
+ * This function writes value to PGGS register.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_write_pggs(unsigned int index,
+					      unsigned int value)
+{
+	if (index >= PGGS_NUM_REGS)
+		return PM_RET_ERROR_ARGS;
+
+	return pm_mmio_write(PGGS_BASEADDR + (index << 2),
+			     0xFFFFFFFFU, value);
+}
+
+/**
+ * pm_ioctl_read_pggs() - Ioctl function for reading persistent
+ *			  global general storage (pggs)
+ * @index	PGGS register index
+ * @value	Register value
+ *
+ * This function returns PGGS register value.
+ *
+ * @return      Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_read_pggs(unsigned int index,
+					     unsigned int *value)
+{
+	if (index >= PGGS_NUM_REGS)
+		return PM_RET_ERROR_ARGS;
+
+	return pm_mmio_read(PGGS_BASEADDR + (index << 2), value);
+}
+
+/**
+ * pm_api_ioctl() -  PM IOCTL API for device control and configs
+ * @node_id	Node ID of the device
+ * @ioctl_id	ID of the requested IOCTL
+ * @arg1	Argument 1 to requested IOCTL call
+ * @arg2	Argument 2 to requested IOCTL call
+ * @value	Returned output value
+ *
+ * This function calls IOCTL to firmware for device control and configuration.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
+				unsigned int ioctl_id,
+				unsigned int arg1,
+				unsigned int arg2,
+				unsigned int *value)
+{
+	enum pm_ret_status ret;
+
+	switch (ioctl_id) {
+	case IOCTL_GET_RPU_OPER_MODE:
+		ret = pm_ioctl_get_rpu_oper_mode(value);
+		break;
+	case IOCTL_SET_RPU_OPER_MODE:
+		ret = pm_ioctl_set_rpu_oper_mode(arg1);
+		break;
+	case IOCTL_RPU_BOOT_ADDR_CONFIG:
+		ret = pm_ioctl_config_boot_addr(nid, arg1);
+		break;
+	case IOCTL_TCM_COMB_CONFIG:
+		ret = pm_ioctl_config_tcm_comb(arg1);
+		break;
+	case IOCTL_SET_TAPDELAY_BYPASS:
+		ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2);
+		break;
+	case IOCTL_SET_SGMII_MODE:
+		ret = pm_ioctl_set_sgmii_mode(nid, arg1);
+		break;
+	case IOCTL_SD_DLL_RESET:
+		ret = pm_ioctl_sd_dll_reset(nid, arg1);
+		break;
+	case IOCTL_SET_SD_TAPDELAY:
+		ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2);
+		break;
+	case IOCTL_SET_PLL_FRAC_MODE:
+		ret = pm_ioctl_set_pll_frac_mode(arg1, arg2);
+		break;
+	case IOCTL_GET_PLL_FRAC_MODE:
+		ret = pm_ioctl_get_pll_frac_mode(arg1, value);
+		break;
+	case IOCTL_SET_PLL_FRAC_DATA:
+		ret = pm_ioctl_set_pll_frac_data(arg1, arg2);
+		break;
+	case IOCTL_GET_PLL_FRAC_DATA:
+		ret = pm_ioctl_get_pll_frac_data(arg1, value);
+		break;
+	case IOCTL_WRITE_GGS:
+		ret = pm_ioctl_write_ggs(arg1, arg2);
+		break;
+	case IOCTL_READ_GGS:
+		ret = pm_ioctl_read_ggs(arg1, value);
+		break;
+	case IOCTL_WRITE_PGGS:
+		ret = pm_ioctl_write_pggs(arg1, arg2);
+		break;
+	case IOCTL_READ_PGGS:
+		ret = pm_ioctl_read_pggs(arg1, value);
+		break;
+	default:
+		ret = PM_RET_ERROR_NOTSUPPORTED;
+		break;
+	}
+
+	return ret;
+}

plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for pin control.
+ */
+
+#ifndef _PM_API_IOCTL_H_
+#define _PM_API_IOCTL_H_
+
+#include "pm_common.h"
+
+//ioctl id
+enum {
+	IOCTL_GET_RPU_OPER_MODE,
+	IOCTL_SET_RPU_OPER_MODE,
+	IOCTL_RPU_BOOT_ADDR_CONFIG,
+	IOCTL_TCM_COMB_CONFIG,
+	IOCTL_SET_TAPDELAY_BYPASS,
+	IOCTL_SET_SGMII_MODE,
+	IOCTL_SD_DLL_RESET,
+	IOCTL_SET_SD_TAPDELAY,
+	 /* Ioctl for clock driver */
+	IOCTL_SET_PLL_FRAC_MODE,
+	IOCTL_GET_PLL_FRAC_MODE,
+	IOCTL_SET_PLL_FRAC_DATA,
+	IOCTL_GET_PLL_FRAC_DATA,
+	IOCTL_WRITE_GGS,
+	IOCTL_READ_GGS,
+	IOCTL_WRITE_PGGS,
+	IOCTL_READ_PGGS,
+};
+
+//RPU operation mode
+#define	PM_RPU_MODE_LOCKSTEP 0U
+#define	PM_RPU_MODE_SPLIT 1U
+
+//RPU boot mem
+#define	PM_RPU_BOOTMEM_LOVEC 0U
+#define	PM_RPU_BOOTMEM_HIVEC 1U
+
+//RPU tcm mpde
+#define	PM_RPU_TCM_SPLIT 0U
+#define	PM_RPU_TCM_COMB 1U
+
+//tap delay signal type
+#define	PM_TAPDELAY_NAND_DQS_IN 0U
+#define	PM_TAPDELAY_NAND_DQS_OUT 1U
+#define	PM_TAPDELAY_QSPI 2U
+#define	PM_TAPDELAY_MAX 3U
+
+//tap delay bypass
+#define	PM_TAPDELAY_BYPASS_DISABLE 0U
+#define	PM_TAPDELAY_BYPASS_ENABLE 1U
+
+//sgmii mode
+#define	PM_SGMII_DISABLE 0U
+#define	PM_SGMII_ENABLE 1U
+
+enum tap_delay_type {
+	PM_TAPDELAY_INPUT,
+	PM_TAPDELAY_OUTPUT,
+};
+
+//dll reset type
+#define	PM_DLL_RESET_ASSERT 0U
+#define	PM_DLL_RESET_RELEASE 1U
+#define	PM_DLL_RESET_PULSE 2U
+
+enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
+				unsigned int ioctl_id,
+				unsigned int arg1,
+				unsigned int arg2,
+				unsigned int *value);
+#endif /* _PM_API_IOCTL_H_ */

plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for pin control.
+ */
+
+#ifndef _PM_API_PINCTRL_H_
+#define _PM_API_PINCTRL_H_
+
+#include "pm_common.h"
+
+#define FUNCTION_NAME_LEN		U(16)
+#define GROUPS_PAYLOAD_LEN		U(12)
+#define NUM_GROUPS_PER_RESP		U(6)
+#define END_OF_FUNCTION			"END_OF_FUNCTION"
+#define END_OF_GROUPS			-1
+#define PINCTRL_GRP_RESERVED		-2
+
+//pinctrl function ids
+enum {
+	PINCTRL_FUNC_CAN0,
+	PINCTRL_FUNC_CAN1,
+	PINCTRL_FUNC_ETHERNET0,
+	PINCTRL_FUNC_ETHERNET1,
+	PINCTRL_FUNC_ETHERNET2,
+	PINCTRL_FUNC_ETHERNET3,
+	PINCTRL_FUNC_GEMTSU0,
+	PINCTRL_FUNC_GPIO0,
+	PINCTRL_FUNC_I2C0,
+	PINCTRL_FUNC_I2C1,
+	PINCTRL_FUNC_MDIO0,
+	PINCTRL_FUNC_MDIO1,
+	PINCTRL_FUNC_MDIO2,
+	PINCTRL_FUNC_MDIO3,
+	PINCTRL_FUNC_QSPI0,
+	PINCTRL_FUNC_QSPI_FBCLK,
+	PINCTRL_FUNC_QSPI_SS,
+	PINCTRL_FUNC_SPI0,
+	PINCTRL_FUNC_SPI1,
+	PINCTRL_FUNC_SPI0_SS,
+	PINCTRL_FUNC_SPI1_SS,
+	PINCTRL_FUNC_SDIO0,
+	PINCTRL_FUNC_SDIO0_PC,
+	PINCTRL_FUNC_SDIO0_CD,
+	PINCTRL_FUNC_SDIO0_WP,
+	PINCTRL_FUNC_SDIO1,
+	PINCTRL_FUNC_SDIO1_PC,
+	PINCTRL_FUNC_SDIO1_CD,
+	PINCTRL_FUNC_SDIO1_WP,
+	PINCTRL_FUNC_NAND0,
+	PINCTRL_FUNC_NAND0_CE,
+	PINCTRL_FUNC_NAND0_RB,
+	PINCTRL_FUNC_NAND0_DQS,
+	PINCTRL_FUNC_TTC0_CLK,
+	PINCTRL_FUNC_TTC0_WAV,
+	PINCTRL_FUNC_TTC1_CLK,
+	PINCTRL_FUNC_TTC1_WAV,
+	PINCTRL_FUNC_TTC2_CLK,
+	PINCTRL_FUNC_TTC2_WAV,
+	PINCTRL_FUNC_TTC3_CLK,
+	PINCTRL_FUNC_TTC3_WAV,
+	PINCTRL_FUNC_UART0,
+	PINCTRL_FUNC_UART1,
+	PINCTRL_FUNC_USB0,
+	PINCTRL_FUNC_USB1,
+	PINCTRL_FUNC_SWDT0_CLK,
+	PINCTRL_FUNC_SWDT0_RST,
+	PINCTRL_FUNC_SWDT1_CLK,
+	PINCTRL_FUNC_SWDT1_RST,
+	PINCTRL_FUNC_PMU0,
+	PINCTRL_FUNC_PCIE0,
+	PINCTRL_FUNC_CSU0,
+	PINCTRL_FUNC_DPAUX0,
+	PINCTRL_FUNC_PJTAG0,
+	PINCTRL_FUNC_TRACE0,
+	PINCTRL_FUNC_TRACE0_CLK,
+	PINCTRL_FUNC_TESTSCAN0,
+	END_FUNCTION,
+};
+
+#define MAX_FUNCTION (unsigned int)(END_FUNCTION)
+
+// pinctrl pin numbers
+enum {
+	PINCTRL_PIN_0,
+	PINCTRL_PIN_1,
+	PINCTRL_PIN_2,
+	PINCTRL_PIN_3,
+	PINCTRL_PIN_4,
+	PINCTRL_PIN_5,
+	PINCTRL_PIN_6,
+	PINCTRL_PIN_7,
+	PINCTRL_PIN_8,
+	PINCTRL_PIN_9,
+	PINCTRL_PIN_10,
+	PINCTRL_PIN_11,
+	PINCTRL_PIN_12,
+	PINCTRL_PIN_13,
+	PINCTRL_PIN_14,
+	PINCTRL_PIN_15,
+	PINCTRL_PIN_16,
+	PINCTRL_PIN_17,
+	PINCTRL_PIN_18,
+	PINCTRL_PIN_19,
+	PINCTRL_PIN_20,
+	PINCTRL_PIN_21,
+	PINCTRL_PIN_22,
+	PINCTRL_PIN_23,
+	PINCTRL_PIN_24,
+	PINCTRL_PIN_25,
+	PINCTRL_PIN_26,
+	PINCTRL_PIN_27,
+	PINCTRL_PIN_28,
+	PINCTRL_PIN_29,
+	PINCTRL_PIN_30,
+	PINCTRL_PIN_31,
+	PINCTRL_PIN_32,
+	PINCTRL_PIN_33,
+	PINCTRL_PIN_34,
+	PINCTRL_PIN_35,
+	PINCTRL_PIN_36,
+	PINCTRL_PIN_37,
+	PINCTRL_PIN_38,
+	PINCTRL_PIN_39,
+	PINCTRL_PIN_40,
+	PINCTRL_PIN_41,
+	PINCTRL_PIN_42,
+	PINCTRL_PIN_43,
+	PINCTRL_PIN_44,
+	PINCTRL_PIN_45,
+	PINCTRL_PIN_46,
+	PINCTRL_PIN_47,
+	PINCTRL_PIN_48,
+	PINCTRL_PIN_49,
+	PINCTRL_PIN_50,
+	PINCTRL_PIN_51,
+	PINCTRL_PIN_52,
+	PINCTRL_PIN_53,
+	PINCTRL_PIN_54,
+	PINCTRL_PIN_55,
+	PINCTRL_PIN_56,
+	PINCTRL_PIN_57,
+	PINCTRL_PIN_58,
+	PINCTRL_PIN_59,
+	PINCTRL_PIN_60,
+	PINCTRL_PIN_61,
+	PINCTRL_PIN_62,
+	PINCTRL_PIN_63,
+	PINCTRL_PIN_64,
+	PINCTRL_PIN_65,
+	PINCTRL_PIN_66,
+	PINCTRL_PIN_67,
+	PINCTRL_PIN_68,
+	PINCTRL_PIN_69,
+	PINCTRL_PIN_70,
+	PINCTRL_PIN_71,
+	PINCTRL_PIN_72,
+	PINCTRL_PIN_73,
+	PINCTRL_PIN_74,
+	PINCTRL_PIN_75,
+	PINCTRL_PIN_76,
+	PINCTRL_PIN_77,
+	END_PINS,
+};
+
+#define MAX_PIN (unsigned int)(END_PINS)
+
+// pinctrl group ids
+enum  {
+	PINCTRL_GRP_ETHERNET0_0,
+	PINCTRL_GRP_ETHERNET1_0,
+	PINCTRL_GRP_ETHERNET2_0,
+	PINCTRL_GRP_ETHERNET3_0,
+	PINCTRL_GRP_GEMTSU0_0,
+	PINCTRL_GRP_GEMTSU0_1,
+	PINCTRL_GRP_GEMTSU0_2,
+	PINCTRL_GRP_MDIO0_0,
+	PINCTRL_GRP_MDIO1_0,
+	PINCTRL_GRP_MDIO1_1,
+	PINCTRL_GRP_MDIO2_0,
+	PINCTRL_GRP_MDIO3_0,
+	PINCTRL_GRP_QSPI0_0,
+	PINCTRL_GRP_QSPI_SS,
+	PINCTRL_GRP_QSPI_FBCLK,
+	PINCTRL_GRP_SPI0_0,
+	PINCTRL_GRP_SPI0_0_SS0,
+	PINCTRL_GRP_SPI0_0_SS1,
+	PINCTRL_GRP_SPI0_0_SS2,
+	PINCTRL_GRP_SPI0_1,
+	PINCTRL_GRP_SPI0_1_SS0,
+	PINCTRL_GRP_SPI0_1_SS1,
+	PINCTRL_GRP_SPI0_1_SS2,
+	PINCTRL_GRP_SPI0_2,
+	PINCTRL_GRP_SPI0_2_SS0,
+	PINCTRL_GRP_SPI0_2_SS1,
+	PINCTRL_GRP_SPI0_2_SS2,
+	PINCTRL_GRP_SPI0_3,
+	PINCTRL_GRP_SPI0_3_SS0,
+	PINCTRL_GRP_SPI0_3_SS1,
+	PINCTRL_GRP_SPI0_3_SS2,
+	PINCTRL_GRP_SPI0_4,
+	PINCTRL_GRP_SPI0_4_SS0,
+	PINCTRL_GRP_SPI0_4_SS1,
+	PINCTRL_GRP_SPI0_4_SS2,
+	PINCTRL_GRP_SPI0_5,
+	PINCTRL_GRP_SPI0_5_SS0,
+	PINCTRL_GRP_SPI0_5_SS1,
+	PINCTRL_GRP_SPI0_5_SS2,
+	PINCTRL_GRP_SPI1_0,
+	PINCTRL_GRP_SPI1_0_SS0,
+	PINCTRL_GRP_SPI1_0_SS1,
+	PINCTRL_GRP_SPI1_0_SS2,
+	PINCTRL_GRP_SPI1_1,
+	PINCTRL_GRP_SPI1_1_SS0,
+	PINCTRL_GRP_SPI1_1_SS1,
+	PINCTRL_GRP_SPI1_1_SS2,
+	PINCTRL_GRP_SPI1_2,
+	PINCTRL_GRP_SPI1_2_SS0,
+	PINCTRL_GRP_SPI1_2_SS1,
+	PINCTRL_GRP_SPI1_2_SS2,
+	PINCTRL_GRP_SPI1_3,
+	PINCTRL_GRP_SPI1_3_SS0,
+	PINCTRL_GRP_SPI1_3_SS1,
+	PINCTRL_GRP_SPI1_3_SS2,
+	PINCTRL_GRP_SPI1_4,
+	PINCTRL_GRP_SPI1_4_SS0,
+	PINCTRL_GRP_SPI1_4_SS1,
+	PINCTRL_GRP_SPI1_4_SS2,
+	PINCTRL_GRP_SPI1_5,
+	PINCTRL_GRP_SPI1_5_SS0,
+	PINCTRL_GRP_SPI1_5_SS1,
+	PINCTRL_GRP_SPI1_5_SS2,
+	PINCTRL_GRP_SDIO0_0,
+	PINCTRL_GRP_SDIO0_1,
+	PINCTRL_GRP_SDIO0_2,
+	PINCTRL_GRP_SDIO0_4BIT_0_0,
+	PINCTRL_GRP_SDIO0_4BIT_0_1,
+	PINCTRL_GRP_SDIO0_4BIT_1_0,
+	PINCTRL_GRP_SDIO0_4BIT_1_1,
+	PINCTRL_GRP_SDIO0_4BIT_2_0,
+	PINCTRL_GRP_SDIO0_4BIT_2_1,
+	PINCTRL_GRP_SDIO0_1BIT_0_0,
+	PINCTRL_GRP_SDIO0_1BIT_0_1,
+	PINCTRL_GRP_SDIO0_1BIT_0_2,
+	PINCTRL_GRP_SDIO0_1BIT_0_3,
+	PINCTRL_GRP_SDIO0_1BIT_0_4,
+	PINCTRL_GRP_SDIO0_1BIT_0_5,
+	PINCTRL_GRP_SDIO0_1BIT_0_6,
+	PINCTRL_GRP_SDIO0_1BIT_0_7,
+	PINCTRL_GRP_SDIO0_1BIT_1_0,
+	PINCTRL_GRP_SDIO0_1BIT_1_1,
+	PINCTRL_GRP_SDIO0_1BIT_1_2,
+	PINCTRL_GRP_SDIO0_1BIT_1_3,
+	PINCTRL_GRP_SDIO0_1BIT_1_4,
+	PINCTRL_GRP_SDIO0_1BIT_1_5,
+	PINCTRL_GRP_SDIO0_1BIT_1_6,
+	PINCTRL_GRP_SDIO0_1BIT_1_7,
+	PINCTRL_GRP_SDIO0_1BIT_2_0,
+	PINCTRL_GRP_SDIO0_1BIT_2_1,
+	PINCTRL_GRP_SDIO0_1BIT_2_2,
+	PINCTRL_GRP_SDIO0_1BIT_2_3,
+	PINCTRL_GRP_SDIO0_1BIT_2_4,
+	PINCTRL_GRP_SDIO0_1BIT_2_5,
+	PINCTRL_GRP_SDIO0_1BIT_2_6,
+	PINCTRL_GRP_SDIO0_1BIT_2_7,
+	PINCTRL_GRP_SDIO0_0_PC,
+	PINCTRL_GRP_SDIO0_0_CD,
+	PINCTRL_GRP_SDIO0_0_WP,
+	PINCTRL_GRP_SDIO0_1_PC,
+	PINCTRL_GRP_SDIO0_1_CD,
+	PINCTRL_GRP_SDIO0_1_WP,
+	PINCTRL_GRP_SDIO0_2_PC,
+	PINCTRL_GRP_SDIO0_2_CD,
+	PINCTRL_GRP_SDIO0_2_WP,
+	PINCTRL_GRP_SDIO1_0,
+	PINCTRL_GRP_SDIO1_4BIT_0_0,
+	PINCTRL_GRP_SDIO1_4BIT_0_1,
+	PINCTRL_GRP_SDIO1_4BIT_1_0,
+	PINCTRL_GRP_SDIO1_1BIT_0_0,
+	PINCTRL_GRP_SDIO1_1BIT_0_1,
+	PINCTRL_GRP_SDIO1_1BIT_0_2,
+	PINCTRL_GRP_SDIO1_1BIT_0_3,
+	PINCTRL_GRP_SDIO1_1BIT_0_4,
+	PINCTRL_GRP_SDIO1_1BIT_0_5,
+	PINCTRL_GRP_SDIO1_1BIT_0_6,
+	PINCTRL_GRP_SDIO1_1BIT_0_7,
+	PINCTRL_GRP_SDIO1_1BIT_1_0,
+	PINCTRL_GRP_SDIO1_1BIT_1_1,
+	PINCTRL_GRP_SDIO1_1BIT_1_2,
+	PINCTRL_GRP_SDIO1_1BIT_1_3,
+	PINCTRL_GRP_SDIO1_0_PC,
+	PINCTRL_GRP_SDIO1_0_CD,
+	PINCTRL_GRP_SDIO1_0_WP,
+	PINCTRL_GRP_SDIO1_1_PC,
+	PINCTRL_GRP_SDIO1_1_CD,
+	PINCTRL_GRP_SDIO1_1_WP,
+	PINCTRL_GRP_NAND0_0,
+	PINCTRL_GRP_NAND0_0_CE,
+	PINCTRL_GRP_NAND0_0_RB,
+	PINCTRL_GRP_NAND0_0_DQS,
+	PINCTRL_GRP_NAND0_1_CE,
+	PINCTRL_GRP_NAND0_1_RB,
+	PINCTRL_GRP_NAND0_1_DQS,
+	PINCTRL_GRP_CAN0_0,
+	PINCTRL_GRP_CAN0_1,
+	PINCTRL_GRP_CAN0_2,
+	PINCTRL_GRP_CAN0_3,
+	PINCTRL_GRP_CAN0_4,
+	PINCTRL_GRP_CAN0_5,
+	PINCTRL_GRP_CAN0_6,
+	PINCTRL_GRP_CAN0_7,
+	PINCTRL_GRP_CAN0_8,
+	PINCTRL_GRP_CAN0_9,
+	PINCTRL_GRP_CAN0_10,
+	PINCTRL_GRP_CAN0_11,
+	PINCTRL_GRP_CAN0_12,
+	PINCTRL_GRP_CAN0_13,
+	PINCTRL_GRP_CAN0_14,
+	PINCTRL_GRP_CAN0_15,
+	PINCTRL_GRP_CAN0_16,
+	PINCTRL_GRP_CAN0_17,
+	PINCTRL_GRP_CAN0_18,
+	PINCTRL_GRP_CAN1_0,
+	PINCTRL_GRP_CAN1_1,
+	PINCTRL_GRP_CAN1_2,
+	PINCTRL_GRP_CAN1_3,
+	PINCTRL_GRP_CAN1_4,
+	PINCTRL_GRP_CAN1_5,
+	PINCTRL_GRP_CAN1_6,
+	PINCTRL_GRP_CAN1_7,
+	PINCTRL_GRP_CAN1_8,
+	PINCTRL_GRP_CAN1_9,
+	PINCTRL_GRP_CAN1_10,
+	PINCTRL_GRP_CAN1_11,
+	PINCTRL_GRP_CAN1_12,
+	PINCTRL_GRP_CAN1_13,
+	PINCTRL_GRP_CAN1_14,
+	PINCTRL_GRP_CAN1_15,
+	PINCTRL_GRP_CAN1_16,
+	PINCTRL_GRP_CAN1_17,
+	PINCTRL_GRP_CAN1_18,
+	PINCTRL_GRP_CAN1_19,
+	PINCTRL_GRP_UART0_0,
+	PINCTRL_GRP_UART0_1,
+	PINCTRL_GRP_UART0_2,
+	PINCTRL_GRP_UART0_3,
+	PINCTRL_GRP_UART0_4,
+	PINCTRL_GRP_UART0_5,
+	PINCTRL_GRP_UART0_6,
+	PINCTRL_GRP_UART0_7,
+	PINCTRL_GRP_UART0_8,
+	PINCTRL_GRP_UART0_9,
+	PINCTRL_GRP_UART0_10,
+	PINCTRL_GRP_UART0_11,
+	PINCTRL_GRP_UART0_12,
+	PINCTRL_GRP_UART0_13,
+	PINCTRL_GRP_UART0_14,
+	PINCTRL_GRP_UART0_15,
+	PINCTRL_GRP_UART0_16,
+	PINCTRL_GRP_UART0_17,
+	PINCTRL_GRP_UART0_18,
+	PINCTRL_GRP_UART1_0,
+	PINCTRL_GRP_UART1_1,
+	PINCTRL_GRP_UART1_2,
+	PINCTRL_GRP_UART1_3,
+	PINCTRL_GRP_UART1_4,
+	PINCTRL_GRP_UART1_5,
+	PINCTRL_GRP_UART1_6,
+	PINCTRL_GRP_UART1_7,
+	PINCTRL_GRP_UART1_8,
+	PINCTRL_GRP_UART1_9,
+	PINCTRL_GRP_UART1_10,
+	PINCTRL_GRP_UART1_11,
+	PINCTRL_GRP_UART1_12,
+	PINCTRL_GRP_UART1_13,
+	PINCTRL_GRP_UART1_14,
+	PINCTRL_GRP_UART1_15,
+	PINCTRL_GRP_UART1_16,
+	PINCTRL_GRP_UART1_17,
+	PINCTRL_GRP_UART1_18,
+	PINCTRL_GRP_I2C0_0,
+	PINCTRL_GRP_I2C0_1,
+	PINCTRL_GRP_I2C0_2,
+	PINCTRL_GRP_I2C0_3,
+	PINCTRL_GRP_I2C0_4,
+	PINCTRL_GRP_I2C0_5,
+	PINCTRL_GRP_I2C0_6,
+	PINCTRL_GRP_I2C0_7,
+	PINCTRL_GRP_I2C0_8,
+	PINCTRL_GRP_I2C0_9,
+	PINCTRL_GRP_I2C0_10,
+	PINCTRL_GRP_I2C0_11,
+	PINCTRL_GRP_I2C0_12,
+	PINCTRL_GRP_I2C0_13,
+	PINCTRL_GRP_I2C0_14,
+	PINCTRL_GRP_I2C0_15,
+	PINCTRL_GRP_I2C0_16,
+	PINCTRL_GRP_I2C0_17,
+	PINCTRL_GRP_I2C0_18,
+	PINCTRL_GRP_I2C1_0,
+	PINCTRL_GRP_I2C1_1,
+	PINCTRL_GRP_I2C1_2,
+	PINCTRL_GRP_I2C1_3,
+	PINCTRL_GRP_I2C1_4,
+	PINCTRL_GRP_I2C1_5,
+	PINCTRL_GRP_I2C1_6,
+	PINCTRL_GRP_I2C1_7,
+	PINCTRL_GRP_I2C1_8,
+	PINCTRL_GRP_I2C1_9,
+	PINCTRL_GRP_I2C1_10,
+	PINCTRL_GRP_I2C1_11,
+	PINCTRL_GRP_I2C1_12,
+	PINCTRL_GRP_I2C1_13,
+	PINCTRL_GRP_I2C1_14,
+	PINCTRL_GRP_I2C1_15,
+	PINCTRL_GRP_I2C1_16,
+	PINCTRL_GRP_I2C1_17,
+	PINCTRL_GRP_I2C1_18,
+	PINCTRL_GRP_I2C1_19,
+	PINCTRL_GRP_TTC0_0_CLK,
+	PINCTRL_GRP_TTC0_0_WAV,
+	PINCTRL_GRP_TTC0_1_CLK,
+	PINCTRL_GRP_TTC0_1_WAV,
+	PINCTRL_GRP_TTC0_2_CLK,
+	PINCTRL_GRP_TTC0_2_WAV,
+	PINCTRL_GRP_TTC0_3_CLK,
+	PINCTRL_GRP_TTC0_3_WAV,
+	PINCTRL_GRP_TTC0_4_CLK,
+	PINCTRL_GRP_TTC0_4_WAV,
+	PINCTRL_GRP_TTC0_5_CLK,
+	PINCTRL_GRP_TTC0_5_WAV,
+	PINCTRL_GRP_TTC0_6_CLK,
+	PINCTRL_GRP_TTC0_6_WAV,
+	PINCTRL_GRP_TTC0_7_CLK,
+	PINCTRL_GRP_TTC0_7_WAV,
+	PINCTRL_GRP_TTC0_8_CLK,
+	PINCTRL_GRP_TTC0_8_WAV,
+	PINCTRL_GRP_TTC1_0_CLK,
+	PINCTRL_GRP_TTC1_0_WAV,
+	PINCTRL_GRP_TTC1_1_CLK,
+	PINCTRL_GRP_TTC1_1_WAV,
+	PINCTRL_GRP_TTC1_2_CLK,
+	PINCTRL_GRP_TTC1_2_WAV,
+	PINCTRL_GRP_TTC1_3_CLK,
+	PINCTRL_GRP_TTC1_3_WAV,
+	PINCTRL_GRP_TTC1_4_CLK,
+	PINCTRL_GRP_TTC1_4_WAV,
+	PINCTRL_GRP_TTC1_5_CLK,
+	PINCTRL_GRP_TTC1_5_WAV,
+	PINCTRL_GRP_TTC1_6_CLK,
+	PINCTRL_GRP_TTC1_6_WAV,
+	PINCTRL_GRP_TTC1_7_CLK,
+	PINCTRL_GRP_TTC1_7_WAV,
+	PINCTRL_GRP_TTC1_8_CLK,
+	PINCTRL_GRP_TTC1_8_WAV,
+	PINCTRL_GRP_TTC2_0_CLK,
+	PINCTRL_GRP_TTC2_0_WAV,
+	PINCTRL_GRP_TTC2_1_CLK,
+	PINCTRL_GRP_TTC2_1_WAV,
+	PINCTRL_GRP_TTC2_2_CLK,
+	PINCTRL_GRP_TTC2_2_WAV,
+	PINCTRL_GRP_TTC2_3_CLK,
+	PINCTRL_GRP_TTC2_3_WAV,
+	PINCTRL_GRP_TTC2_4_CLK,
+	PINCTRL_GRP_TTC2_4_WAV,
+	PINCTRL_GRP_TTC2_5_CLK,
+	PINCTRL_GRP_TTC2_5_WAV,
+	PINCTRL_GRP_TTC2_6_CLK,
+	PINCTRL_GRP_TTC2_6_WAV,
+	PINCTRL_GRP_TTC2_7_CLK,
+	PINCTRL_GRP_TTC2_7_WAV,
+	PINCTRL_GRP_TTC2_8_CLK,
+	PINCTRL_GRP_TTC2_8_WAV,
+	PINCTRL_GRP_TTC3_0_CLK,
+	PINCTRL_GRP_TTC3_0_WAV,
+	PINCTRL_GRP_TTC3_1_CLK,
+	PINCTRL_GRP_TTC3_1_WAV,
+	PINCTRL_GRP_TTC3_2_CLK,
+	PINCTRL_GRP_TTC3_2_WAV,
+	PINCTRL_GRP_TTC3_3_CLK,
+	PINCTRL_GRP_TTC3_3_WAV,
+	PINCTRL_GRP_TTC3_4_CLK,
+	PINCTRL_GRP_TTC3_4_WAV,
+	PINCTRL_GRP_TTC3_5_CLK,
+	PINCTRL_GRP_TTC3_5_WAV,
+	PINCTRL_GRP_TTC3_6_CLK,
+	PINCTRL_GRP_TTC3_6_WAV,
+	PINCTRL_GRP_TTC3_7_CLK,
+	PINCTRL_GRP_TTC3_7_WAV,
+	PINCTRL_GRP_TTC3_8_CLK,
+	PINCTRL_GRP_TTC3_8_WAV,
+	PINCTRL_GRP_SWDT0_0_CLK,
+	PINCTRL_GRP_SWDT0_0_RST,
+	PINCTRL_GRP_SWDT0_1_CLK,
+	PINCTRL_GRP_SWDT0_1_RST,
+	PINCTRL_GRP_SWDT0_2_CLK,
+	PINCTRL_GRP_SWDT0_2_RST,
+	PINCTRL_GRP_SWDT0_3_CLK,
+	PINCTRL_GRP_SWDT0_3_RST,
+	PINCTRL_GRP_SWDT0_4_CLK,
+	PINCTRL_GRP_SWDT0_4_RST,
+	PINCTRL_GRP_SWDT0_5_CLK,
+	PINCTRL_GRP_SWDT0_5_RST,
+	PINCTRL_GRP_SWDT0_6_CLK,
+	PINCTRL_GRP_SWDT0_6_RST,
+	PINCTRL_GRP_SWDT0_7_CLK,
+	PINCTRL_GRP_SWDT0_7_RST,
+	PINCTRL_GRP_SWDT0_8_CLK,
+	PINCTRL_GRP_SWDT0_8_RST,
+	PINCTRL_GRP_SWDT0_9_CLK,
+	PINCTRL_GRP_SWDT0_9_RST,
+	PINCTRL_GRP_SWDT0_10_CLK,
+	PINCTRL_GRP_SWDT0_10_RST,
+	PINCTRL_GRP_SWDT0_11_CLK,
+	PINCTRL_GRP_SWDT0_11_RST,
+	PINCTRL_GRP_SWDT0_12_CLK,
+	PINCTRL_GRP_SWDT0_12_RST,
+	PINCTRL_GRP_SWDT1_0_CLK,
+	PINCTRL_GRP_SWDT1_0_RST,
+	PINCTRL_GRP_SWDT1_1_CLK,
+	PINCTRL_GRP_SWDT1_1_RST,
+	PINCTRL_GRP_SWDT1_2_CLK,
+	PINCTRL_GRP_SWDT1_2_RST,
+	PINCTRL_GRP_SWDT1_3_CLK,
+	PINCTRL_GRP_SWDT1_3_RST,
+	PINCTRL_GRP_SWDT1_4_CLK,
+	PINCTRL_GRP_SWDT1_4_RST,
+	PINCTRL_GRP_SWDT1_5_CLK,
+	PINCTRL_GRP_SWDT1_5_RST,
+	PINCTRL_GRP_SWDT1_6_CLK,
+	PINCTRL_GRP_SWDT1_6_RST,
+	PINCTRL_GRP_SWDT1_7_CLK,
+	PINCTRL_GRP_SWDT1_7_RST,
+	PINCTRL_GRP_SWDT1_8_CLK,
+	PINCTRL_GRP_SWDT1_8_RST,
+	PINCTRL_GRP_SWDT1_9_CLK,
+	PINCTRL_GRP_SWDT1_9_RST,
+	PINCTRL_GRP_SWDT1_10_CLK,
+	PINCTRL_GRP_SWDT1_10_RST,
+	PINCTRL_GRP_SWDT1_11_CLK,
+	PINCTRL_GRP_SWDT1_11_RST,
+	PINCTRL_GRP_SWDT1_12_CLK,
+	PINCTRL_GRP_SWDT1_12_RST,
+	PINCTRL_GRP_GPIO0_0,
+	PINCTRL_GRP_GPIO0_1,
+	PINCTRL_GRP_GPIO0_2,
+	PINCTRL_GRP_GPIO0_3,
+	PINCTRL_GRP_GPIO0_4,
+	PINCTRL_GRP_GPIO0_5,
+	PINCTRL_GRP_GPIO0_6,
+	PINCTRL_GRP_GPIO0_7,
+	PINCTRL_GRP_GPIO0_8,
+	PINCTRL_GRP_GPIO0_9,
+	PINCTRL_GRP_GPIO0_10,
+	PINCTRL_GRP_GPIO0_11,
+	PINCTRL_GRP_GPIO0_12,
+	PINCTRL_GRP_GPIO0_13,
+	PINCTRL_GRP_GPIO0_14,
+	PINCTRL_GRP_GPIO0_15,
+	PINCTRL_GRP_GPIO0_16,
+	PINCTRL_GRP_GPIO0_17,
+	PINCTRL_GRP_GPIO0_18,
+	PINCTRL_GRP_GPIO0_19,
+	PINCTRL_GRP_GPIO0_20,
+	PINCTRL_GRP_GPIO0_21,
+	PINCTRL_GRP_GPIO0_22,
+	PINCTRL_GRP_GPIO0_23,
+	PINCTRL_GRP_GPIO0_24,
+	PINCTRL_GRP_GPIO0_25,
+	PINCTRL_GRP_GPIO0_26,
+	PINCTRL_GRP_GPIO0_27,
+	PINCTRL_GRP_GPIO0_28,
+	PINCTRL_GRP_GPIO0_29,
+	PINCTRL_GRP_GPIO0_30,
+	PINCTRL_GRP_GPIO0_31,
+	PINCTRL_GRP_GPIO0_32,
+	PINCTRL_GRP_GPIO0_33,
+	PINCTRL_GRP_GPIO0_34,
+	PINCTRL_GRP_GPIO0_35,
+	PINCTRL_GRP_GPIO0_36,
+	PINCTRL_GRP_GPIO0_37,
+	PINCTRL_GRP_GPIO0_38,
+	PINCTRL_GRP_GPIO0_39,
+	PINCTRL_GRP_GPIO0_40,
+	PINCTRL_GRP_GPIO0_41,
+	PINCTRL_GRP_GPIO0_42,
+	PINCTRL_GRP_GPIO0_43,
+	PINCTRL_GRP_GPIO0_44,
+	PINCTRL_GRP_GPIO0_45,
+	PINCTRL_GRP_GPIO0_46,
+	PINCTRL_GRP_GPIO0_47,
+	PINCTRL_GRP_GPIO0_48,
+	PINCTRL_GRP_GPIO0_49,
+	PINCTRL_GRP_GPIO0_50,
+	PINCTRL_GRP_GPIO0_51,
+	PINCTRL_GRP_GPIO0_52,
+	PINCTRL_GRP_GPIO0_53,
+	PINCTRL_GRP_GPIO0_54,
+	PINCTRL_GRP_GPIO0_55,
+	PINCTRL_GRP_GPIO0_56,
+	PINCTRL_GRP_GPIO0_57,
+	PINCTRL_GRP_GPIO0_58,
+	PINCTRL_GRP_GPIO0_59,
+	PINCTRL_GRP_GPIO0_60,
+	PINCTRL_GRP_GPIO0_61,
+	PINCTRL_GRP_GPIO0_62,
+	PINCTRL_GRP_GPIO0_63,
+	PINCTRL_GRP_GPIO0_64,
+	PINCTRL_GRP_GPIO0_65,
+	PINCTRL_GRP_GPIO0_66,
+	PINCTRL_GRP_GPIO0_67,
+	PINCTRL_GRP_GPIO0_68,
+	PINCTRL_GRP_GPIO0_69,
+	PINCTRL_GRP_GPIO0_70,
+	PINCTRL_GRP_GPIO0_71,
+	PINCTRL_GRP_GPIO0_72,
+	PINCTRL_GRP_GPIO0_73,
+	PINCTRL_GRP_GPIO0_74,
+	PINCTRL_GRP_GPIO0_75,
+	PINCTRL_GRP_GPIO0_76,
+	PINCTRL_GRP_GPIO0_77,
+	PINCTRL_GRP_USB0_0,
+	PINCTRL_GRP_USB1_0,
+	PINCTRL_GRP_PMU0_0,
+	PINCTRL_GRP_PMU0_1,
+	PINCTRL_GRP_PMU0_2,
+	PINCTRL_GRP_PMU0_3,
+	PINCTRL_GRP_PMU0_4,
+	PINCTRL_GRP_PMU0_5,
+	PINCTRL_GRP_PMU0_6,
+	PINCTRL_GRP_PMU0_7,
+	PINCTRL_GRP_PMU0_8,
+	PINCTRL_GRP_PMU0_9,
+	PINCTRL_GRP_PMU0_10,
+	PINCTRL_GRP_PMU0_11,
+	PINCTRL_GRP_PCIE0_0,
+	PINCTRL_GRP_PCIE0_1,
+	PINCTRL_GRP_PCIE0_2,
+	PINCTRL_GRP_PCIE0_3,
+	PINCTRL_GRP_PCIE0_4,
+	PINCTRL_GRP_PCIE0_5,
+	PINCTRL_GRP_PCIE0_6,
+	PINCTRL_GRP_PCIE0_7,
+	PINCTRL_GRP_CSU0_0,
+	PINCTRL_GRP_CSU0_1,
+	PINCTRL_GRP_CSU0_2,
+	PINCTRL_GRP_CSU0_3,
+	PINCTRL_GRP_CSU0_4,
+	PINCTRL_GRP_CSU0_5,
+	PINCTRL_GRP_CSU0_6,
+	PINCTRL_GRP_CSU0_7,
+	PINCTRL_GRP_CSU0_8,
+	PINCTRL_GRP_CSU0_9,
+	PINCTRL_GRP_CSU0_10,
+	PINCTRL_GRP_CSU0_11,
+	PINCTRL_GRP_DPAUX0_0,
+	PINCTRL_GRP_DPAUX0_1,
+	PINCTRL_GRP_DPAUX0_2,
+	PINCTRL_GRP_DPAUX0_3,
+	PINCTRL_GRP_PJTAG0_0,
+	PINCTRL_GRP_PJTAG0_1,
+	PINCTRL_GRP_PJTAG0_2,
+	PINCTRL_GRP_PJTAG0_3,
+	PINCTRL_GRP_PJTAG0_4,
+	PINCTRL_GRP_PJTAG0_5,
+	PINCTRL_GRP_TRACE0_0,
+	PINCTRL_GRP_TRACE0_0_CLK,
+	PINCTRL_GRP_TRACE0_1,
+	PINCTRL_GRP_TRACE0_1_CLK,
+	PINCTRL_GRP_TRACE0_2,
+	PINCTRL_GRP_TRACE0_2_CLK,
+	PINCTRL_GRP_TESTSCAN0_0,
+};
+
+// pinctrl config parameters
+enum {
+	PINCTRL_CONFIG_SLEW_RATE,
+	PINCTRL_CONFIG_BIAS_STATUS,
+	PINCTRL_CONFIG_PULL_CTRL,
+	PINCTRL_CONFIG_SCHMITT_CMOS,
+	PINCTRL_CONFIG_DRIVE_STRENGTH,
+	PINCTRL_CONFIG_VOLTAGE_STATUS,
+	PINCTRL_CONFIG_MAX,
+};
+
+// pinctrl slew rate
+#define	PINCTRL_SLEW_RATE_FAST 0U
+#define	PINCTRL_SLEW_RATE_SLOW 1U
+
+// pinctrl bias status
+#define	PINCTRL_BIAS_DISABLE 0U
+#define	PINCTRL_BIAS_ENABLE 1U
+
+// pinctrl pull control
+#define	PINCTRL_BIAS_PULL_DOWN 0U
+#define	PINCTRL_BIAS_PULL_UP 1U
+
+// pinctrl schmitt cmos type
+#define PINCTRL_INPUT_TYPE_CMOS 0U
+#define	PINCTRL_INPUT_TYPE_SCHMITT 1U
+
+//pinctrl drive strength values
+#define	PINCTRL_DRIVE_STRENGTH_2MA 0U
+#define	PINCTRL_DRIVE_STRENGTH_4MA 1U
+#define	PINCTRL_DRIVE_STRENGTH_8MA 2U
+#define	PINCTRL_DRIVE_STRENGTH_12MA 3U
+
+enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
+					       unsigned int fid);
+enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
+					       unsigned int *id);
+enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
+					     unsigned int param,
+					     unsigned int value);
+enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
+					     unsigned int param,
+					     unsigned int *value);
+enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
+						    char *name);
+enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
+						      unsigned int index,
+						      uint16_t *groups);
+enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin,
+						 unsigned int index,
+						 uint16_t *groups);
+enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins);
+enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs);
+enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
+						      unsigned int *ngroups);
+#endif /* _PM_API_PINCTRL_H_ */

plat/xilinx/zynqmp/pm_service/pm_api_sys.h

 /*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,21 @@
 #include <stdint.h>
 #include "pm_defs.h"
 
+enum pm_query_id {
+	PM_QID_INVALID,
+	PM_QID_CLOCK_GET_NAME,
+	PM_QID_CLOCK_GET_TOPOLOGY,
+	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
+	PM_QID_CLOCK_GET_PARENTS,
+	PM_QID_CLOCK_GET_ATTRIBUTES,
+	PM_QID_PINCTRL_GET_NUM_PINS,
+	PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
+	PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
+	PM_QID_PINCTRL_GET_FUNCTION_NAME,
+	PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
+	PM_QID_PINCTRL_GET_PIN_GROUPS,
+};
+
 /**********************************************************
  * System-level API function declarations
  **********************************************************/
@@ -93,5 +108,42 @@ enum pm_ret_status pm_fpga_get_status(unsigned int *value);
 
 enum pm_ret_status pm_get_chipid(uint32_t *value);
 void pm_get_callbackdata(uint32_t *data, size_t count);
-
+enum pm_ret_status pm_pinctrl_request(unsigned int pin);
+enum pm_ret_status pm_pinctrl_release(unsigned int pin);
+enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
+					   enum pm_node_id *nid);
+enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
+					   enum pm_node_id nid);
+enum pm_ret_status pm_pinctrl_get_config(unsigned int pin,
+					 unsigned int param,
+					 unsigned int *value);
+enum pm_ret_status pm_pinctrl_set_config(unsigned int pin,
+					 unsigned int param,
+					 unsigned int value);
+enum pm_ret_status pm_ioctl(enum pm_node_id nid,
+			    unsigned int ioctl_id,
+			    unsigned int arg1,
+			    unsigned int arg2,
+			    unsigned int *value);
+enum pm_ret_status pm_clock_enable(unsigned int clock_id);
+enum pm_ret_status pm_clock_disable(unsigned int clock_id);
+enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
+				     unsigned int *state);
+enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
+				       unsigned int divider);
+enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
+				       unsigned int *divider);
+enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
+				    uint64_t rate);
+enum pm_ret_status pm_clock_getrate(unsigned int clock_id,
+				    uint64_t *rate);
+enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
+				      unsigned int parent_id);
+enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
+				      unsigned int *parent_id);
+enum pm_ret_status pm_query_data(enum pm_query_id qid,
+				 unsigned int arg1,
+				 unsigned int arg2,
+				 unsigned int arg3,
+				 unsigned int *data);
 #endif /* _PM_API_SYS_H_ */

plat/xilinx/zynqmp/pm_service/pm_common.h

@@ -19,6 +19,11 @@
 #define PAYLOAD_ARG_CNT		6U
 #define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
 
+#define ZYNQMP_TZ_VERSION_MAJOR		1
+#define ZYNQMP_TZ_VERSION_MINOR		0
+#define ZYNQMP_TZ_VERSION		((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
+					ZYNQMP_TZ_VERSION_MINOR)
+
 /**
  * pm_ipi - struct for capturing IPI-channel specific info
  * @apu_ipi_id	APU IPI agent ID