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Unverified Commit c0ce16fb authored by Soby Mathew's avatar Soby Mathew Committed by GitHub
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Merge pull request #1878 from jts-arm/sctlr 

Apply stricter speculative load restriction
parents c61a807a 02b57943
master v2.5 v2.5-rc1 v2.5-rc0 v2.4 v2.4-rc2 v2.4-rc1 v2.4-rc0 v2.3 v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.2 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.1 v2.1-rc1 v2.1-rc0 arm_cca_v0.2 arm_cca_v0.1
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with 19 additions and 11 deletions
+19 -11
bl2/aarch32/bl2_entrypoint.S
View file @ c0ce16fb
...@@ -42,12 +42,13 @@ func bl2_entrypoint ...@@ -42,12 +42,13 @@ func bl2_entrypoint
stcopr r0, VBAR stcopr r0, VBAR
isb isb
/* ----------------------------------------------------- /* --------------------------------------------------------
* Enable the instruction cache * Enable the instruction cache - disable speculative loads
* ----------------------------------------------------- * --------------------------------------------------------
*/ */
ldcopr r0, SCTLR ldcopr r0, SCTLR
orr r0, r0, #SCTLR_I_BIT orr r0, r0, #SCTLR_I_BIT
bic r0, r0, #SCTLR_DSSBS_BIT
stcopr r0, SCTLR stcopr r0, SCTLR
isb isb
......
bl2/aarch64/bl2_entrypoint.S
View file @ c0ce16fb
...@@ -41,12 +41,14 @@ func bl2_entrypoint ...@@ -41,12 +41,14 @@ func bl2_entrypoint
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb
......
bl2u/aarch32/bl2u_entrypoint.S
View file @ c0ce16fb
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -41,12 +41,13 @@ func bl2u_entrypoint ...@@ -41,12 +41,13 @@ func bl2u_entrypoint
stcopr r0, VBAR stcopr r0, VBAR
isb isb
/* ----------------------------------------------------- /* --------------------------------------------------------
* Enable the instruction cache * Enable the instruction cache - disable speculative loads
* ----------------------------------------------------- * --------------------------------------------------------
*/ */
ldcopr r0, SCTLR ldcopr r0, SCTLR
orr r0, r0, #SCTLR_I_BIT orr r0, r0, #SCTLR_I_BIT
bic r0, r0, #SCTLR_DSSBS_BIT
stcopr r0, SCTLR stcopr r0, SCTLR
isb isb
......
bl2u/aarch64/bl2u_entrypoint.S
View file @ c0ce16fb
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -38,12 +38,14 @@ func bl2u_entrypoint ...@@ -38,12 +38,14 @@ func bl2u_entrypoint
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb
......
bl32/tsp/aarch64/tsp_entrypoint.S
View file @ c0ce16fb
...@@ -63,12 +63,14 @@ func tsp_entrypoint _align=3 ...@@ -63,12 +63,14 @@ func tsp_entrypoint _align=3
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb
......
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