Commit c478ff5d authored by Jon Medhurst's avatar Jon Medhurst Committed by Sandrine Bailleux
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juno: Port CCI

Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
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Showing with 3 additions and 8 deletions
+3 -8
...@@ -123,17 +123,12 @@ void bl1_platform_setup(void) ...@@ -123,17 +123,12 @@ void bl1_platform_setup(void)
******************************************************************************/ ******************************************************************************/
void bl1_plat_arch_setup(void) void bl1_plat_arch_setup(void)
{ {
unsigned long cci_setup;
/* /*
* Enable CCI-400 for this cluster. No need * Enable CCI-400 for this cluster. No need
* for locks as no other cpu is active at the * for locks as no other cpu is active at the
* moment * moment
*/ */
cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); cci_enable_coherency(read_mpidr());
if (cci_setup) {
cci_enable_coherency(read_mpidr());
}
configure_mmu(&bl1_tzram_layout, configure_mmu(&bl1_tzram_layout,
TZROM_BASE, TZROM_BASE,
......
...@@ -160,8 +160,8 @@ ...@@ -160,8 +160,8 @@
* CCI-400 related constants * CCI-400 related constants
******************************************************************************/ ******************************************************************************/
#define CCI400_BASE 0x2c090000 #define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 3 #define CCI400_SL_IFACE_CLUSTER0 4
#define CCI400_SL_IFACE_CLUSTER1 4 #define CCI400_SL_IFACE_CLUSTER1 3
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ #define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \ CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0) CCI400_SL_IFACE_CLUSTER0)
......
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