Commit d402f3dc authored by achingupta's avatar achingupta
Browse files

Merge pull request #213 from soby-mathew/sm/crash_reporting_fix

Remove BSS section access by 'plat_print_gic' during crash reporting
parents bcdbf945 6ab03912
...@@ -33,8 +33,8 @@ ...@@ -33,8 +33,8 @@
#include "../fvp_def.h" #include "../fvp_def.h"
.section .rodata.gic_reg_name, "aS" .section .rodata.gic_reg_name, "aS"
gic_regs: gicc_regs:
.asciz "gic_hppir", "gic_ahppir", "gic_ctlr", "" .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg: gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline: newline:
...@@ -46,19 +46,33 @@ spacer: ...@@ -46,19 +46,33 @@ spacer:
* The below macro prints out relevant GIC * The below macro prints out relevant GIC
* registers whenever an unhandled exception is * registers whenever an unhandled exception is
* taken in BL3-1. * taken in BL3-1.
* Clobbers: x0 - x10, x16, sp * Clobbers: x0 - x10, x16, x17, sp
* --------------------------------------------- * ---------------------------------------------
*/ */
.macro plat_print_gic_regs .macro plat_print_gic_regs
adr x0, plat_config mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
ldr w16, [x0, #CONFIG_GICC_BASE_OFFSET] ldr w16, [x0]
cbz x16, exit_print_gic_regs /* Extract BLD (12th - 15th bits) from the SYS_ID */
/* gic base address is now in x16 */ ubfx x16, x16, #SYS_ID_BLD_SHIFT, #4
adr x6, gic_regs /* Load the gic reg list to x6 */ /* Check if VE mmap */
/* Load the gic regs to gp regs used by str_in_crash_buf_print */ cmp w16, #BLD_GIC_VE_MMAP
ldr w8, [x16, #GICC_HPPIR] b.eq use_ve_mmap
ldr w9, [x16, #GICC_AHPPIR] /* Check if Cortex-A53/A57 mmap */
ldr w10, [x16, #GICC_CTLR] cmp w16, #BLD_GIC_A53A57_MMAP
b.ne exit_print_gic_regs
mov_imm x17, BASE_GICC_BASE
mov_imm x16, BASE_GICD_BASE
b print_gicc_regs
use_ve_mmap:
mov_imm x17, VE_GICC_BASE
mov_imm x16, VE_GICD_BASE
print_gicc_regs:
/* gicc base address is now in x17 */
adr x6, gicc_regs /* Load the gicc reg list to x6 */
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w8, [x17, #GICC_HPPIR]
ldr w9, [x17, #GICC_AHPPIR]
ldr w10, [x17, #GICC_CTLR]
/* Store to the crash buf and print to console */ /* Store to the crash buf and print to console */
bl str_in_crash_buf_print bl str_in_crash_buf_print
......
...@@ -34,8 +34,8 @@ ...@@ -34,8 +34,8 @@
#include "../juno_def.h" #include "../juno_def.h"
.section .rodata.gic_reg_name, "aS" .section .rodata.gic_reg_name, "aS"
gic_regs: gicc_regs:
.asciz "gic_hppir", "gic_ahppir", "gic_ctlr", "" .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg: gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline: newline:
...@@ -52,13 +52,14 @@ spacer: ...@@ -52,13 +52,14 @@ spacer:
* --------------------------------------------- * ---------------------------------------------
*/ */
.macro plat_print_gic_regs .macro plat_print_gic_regs
ldr x16, =GICC_BASE mov_imm x16, GICD_BASE
/* Load the gic reg list to x6 */ mov_imm x17, GICC_BASE
adr x6, gic_regs /* Load the gicc reg list to x6 */
/* Load the gic regs to gp regs used by str_in_crash_buf_print */ adr x6, gicc_regs
ldr w8, [x16, #GICC_HPPIR] /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w9, [x16, #GICC_AHPPIR] ldr w8, [x17, #GICC_HPPIR]
ldr w10, [x16, #GICC_CTLR] ldr w9, [x17, #GICC_AHPPIR]
ldr w10, [x17, #GICC_CTLR]
/* Store to the crash buf and print to console */ /* Store to the crash buf and print to console */
bl str_in_crash_buf_print bl str_in_crash_buf_print
......
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